KR100697379B1 - Method of manufacturing poly-Si TFT - Google Patents

Abstract

The present invention discloses a method for manufacturing a polysilicon thin film transistor of a liquid crystal display device. The disclosed method includes depositing an amorphous silicon layer on a glass substrate, forming an n + / p + doped layer on the surface of the amorphous silicon layer, and depositing a nickel film on the n + / p + doped layer. Forming a source electrode and a drain electrode spaced apart from each other by patterning the nickel film; etching a portion of the n + / p + doped layer between the source electrode and the drain electrode; and etching the substrate resultant at 450 to 500 ° C. The amorphous silicon layer is formed by thermally treating at a temperature of about to form nickel-silicide at the interface between the osodine / drain electrode and the n + / p + doped layer, and simultaneously form crystals through diffusion of nickel and lateral expansion of the crystal into the channel region. Crystallizing a polysilicon layer, depositing a gate insulating film on the resultant, and forming a gate electrode on the gate insulating film. It includes the system. According to the present invention, since crystallization of amorphous silicon is achieved by applying crystals extending in the lateral direction using a source / drain metal as a metal for crystallization, silicon contamination in the channel region can be prevented, and thus, amorphous silicon Reliability of crystallization can be secured.

Description

Method of manufacturing polycrystalline silicon thin film transistor {Method of manufacturing poly-Si TFT}

1A to 1E are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to an exemplary embodiment of the present invention.

2A to 2E are cross-sectional views of processes for explaining a method of manufacturing a polysilicon thin film transistor according to another exemplary embodiment of the present invention.

3A to 3D are cross-sectional views of processes for explaining a method of manufacturing a polysilicon thin film transistor according to still another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1,21,31: glass substrate 2,22,32: undoped amorphous silicon layer

3,22,32 n + / p + doped layer 4,24,34 nickel film

4a, 24a, 34a: source electrode 4b, 24b, 34b: drain electrode

5,25,35 nickel silicide 6,26,36 polysilicon layer

7,27,37: gate insulating film 8,28,38: gate

10: thin film transistor

The present invention relates to a method of manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of manufacturing a polysilicon thin film transistor using a MILC (Metal Induced Lateral Crystallization) method.

Liquid crystal displays have been developed in place of CRT (Cathode Ray Tube) based on the advantages of low weight, low voltage driving and low power consumption. In recent years, it has been widely used in various fields as well as the notebook PC and monitor market because it has realized large size and colorization.

The TFT-LCD includes a liquid crystal panel in which an array substrate including a thin film transistor and a pixel electrode, and a color filter substrate including a color filter and a counter electrode are bonded to each other through a liquid crystal layer, a drive driver IC connected to the liquid crystal panel; It includes a circuit board.

On the other hand, in such a TFT-LCD, the undoped amorphous silicon layer is used as the channel layer of the thin film transistor included in each pixel of the liquid crystal panel, whereas the polysilicon layer is used as the channel layer of the drive driver IC. .

Accordingly, conventionally, in order to manufacture a TFT-LCD module, a separate process is performed to manufacture a liquid crystal panel and a drive driver IC, respectively, and then, since they are connected to each other, the overall manufacturing process is complicated and in terms of integration degree. There was an undesirable problem.

Therefore, recently, a technique for applying a polysilicon layer as a channel layer of a thin film transistor has been proposed. When the polysilicon layer is applied as the channel layer, the thin film transistor and the driving drive IC can be formed on the same substrate at the same time, thereby simplifying the manufacturing process and improving the degree of integration.

As a method for applying a polysilicon layer as a channel layer of the thin film transistor, a method using a metal and a method using laser annealing are currently applied.

Here, the former method is a method of forming a polysilicon layer by forming a metal film on the amorphous silicon layer and performing a heat treatment to perform a crystal bonding through metal diffusion, thereby forming a polysilicon layer, the latter method of the amorphous silicon layer It is a method of forming a polysilicon layer by performing laser scanning after deposition so that amorphous silicon is crystallized into polycrystalline silicon.

However, although not described in detail, the method using metal has a problem of causing leakage current by contaminating the crystallized channel silicon with the metal used for the crystallization. Also, the method using the laser has the reliability of crystallization but its application There is a problem in that the equipment investment cost required to be high.

Accordingly, an object of the present invention is to provide a method for manufacturing a polysilicon thin film transistor capable of preventing contamination of channel silicon, as an object of the present invention.

In addition, another object of the present invention is to provide a method for manufacturing a polysilicon thin film transistor which can ensure the reliability while preventing the increase of the equipment investment cost.

Polycrystalline silicon thin film transistor manufacturing method according to the present invention for achieving the above object comprises the steps of depositing an amorphous silicon layer on a glass substrate; Forming an n + / p + doping layer on a surface of the amorphous silicon layer; Depositing a source / drain metal film on the n + / p + doped layer; Patterning the source / drain metal film to form source and drain electrodes spaced apart from each other to define a channel region; Etching the n + / p + doped layer of the channel region between the source electrode and the drain electrode so that the amorphous silicon layer is exposed; Heat treating the amorphous silicon layer to form a metal-silicide layer at an interface between the source and drain electrodes and the n + / p + doping layer, and simultaneously form crystals through diffusion of the source and drain metals and the channel region of the formed crystal Crystallizing the amorphous silicon layer into a polysilicon layer through lateral expansion into the polysilicon layer; Depositing a gate insulating film on the source and drain electrodes to cover the crystallized polysilicon layer of the channel region; And forming a gate electrode in the channel region on the gate insulating layer.

The n + / p + doping layer may be formed by depositing a dopant doping layer or by implanting a dopant on the surface of an amorphous silicon layer, and the dopant ion implantation may be accelerated at room temperature. It is carried out in a small ion shower.

The source / drain metal film is preferably a nickel (Ni) film, and the heat treatment is performed at a temperature of 450 to 500 ° C.

In addition, the method for manufacturing a polysilicon thin film transistor according to the present invention for achieving the above object comprises the steps of depositing an amorphous silicon layer, a gate insulating film and a gate metal film on a glass substrate; Patterning the gate metal film and the gate insulating film to expose the amorphous silicon layer to form a gate electrode; Performing dopant ion implantation using the gate electrode as a mask to form an n + / p + doping layer on the surfaces of the amorphous silicon layers on both sides of the gate electrode; Depositing a nickel film on the n + / p + doped layer to cover the gate electrode; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; And removing the nickel film remaining without reacting during the heat treatment.

Here, the dopant ion implantation is performed by an ion shower method at room temperature.

The nickel-silicide layer on the surface of the crystallized polysilicon layer may be used as a source / drain electrode, whereas after crystallizing the amorphous silicon layer with the polysilicon layer, a source may be formed on the nickel-silicide layer on both sides of the gate electrode. It is also possible to form the drain electrode.

The heat treatment is carried out at a temperature of 450 ~ 500 ℃.

In addition, the polysilicon thin film transistor manufacturing method according to the present invention for achieving the above object comprises the steps of depositing an amorphous silicon layer and a gate insulating film on a glass substrate; Patterning the gate insulating layer to expose the amorphous silicon layer to define a channel region; Forming an n + / p + doped layer by implanting dopant ions into the exposed portion of the amorphous silicon layer using the patterned gate insulating film as a mask; Depositing a nickel film on the n + / p + doped layer to cover the gate insulating film; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; Removing the nickel film remaining without reacting during the heat treatment; Depositing a metal film on the nickel-silicide layer to cover the gate insulating film; And forming a gate electrode on the gate insulating layer by patterning the metal layer, and simultaneously forming source and drain electrodes on the nickel-silicide layers on both sides of the gate electrode.

Here, the dopant ion implantation is performed by an ion shower method at room temperature, and the heat treatment is performed at a temperature of 450 ~ 500 ℃.

According to the present invention, since crystallization of amorphous silicon is achieved by applying crystals extending in the lateral direction using a source / drain metal as the metal for crystallization, silicon contamination in the channel region can be prevented. Reliability can be secured.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a polysilicon TFT according to an embodiment of the present invention.

Referring to FIG. 1A, after depositing an amorphous silicon layer 2 on a glass substrate 1, an n + / p + doped layer 3 is deposited on the surface thereof. Then, a nickel film 4 is deposited on the n + / p + doped layer 3 as a metal film for source / drain. At this time, the nickel (Ni) is not only easy to form silicide, it is advantageous in the formation of polycrystalline silicon during crystallization.

Herein, the n + / p + doped layer 3 may be formed by ion implantation of a dopant on the surface of the amorphous silicon layer 2, rather than general doping layer deposition. In this case, since the implantation depth of the conventional implantation is deep, it is preferable to dop the dopant thinly on the surface of the amorphous silicon layer 2 by an ion shower method having a small acceleration voltage.

In addition, it is preferable that the dopant ion implantation proceeds at room temperature. When the temperature of the dopant ion implantation is high, ion activation occurs and ion diffusion occurs. This is because all of the amorphous silicon layers may be ion contamination.

Referring to FIG. 1B, the nickel film is etched according to a known photolithography process, thereby forming source and drain electrodes 4a and 4b spaced apart from each other.

Referring to FIG. 1C, an n + / p + doped layer portion between the source electrode 4a and the drain electrode 4b is etched, thereby exposing an amorphous silicon layer portion corresponding to the channel region. At this time, during the etching of the n + / p + doped layer 3, it is preferable to slightly over-etch (over etch).

Referring to FIG. 1D, heat treatment is performed at a temperature sufficient to form MILC (Metal Induced Lateral Crystallization), for example, 450 to 500 ° C.

In this way, nickel (Ni), which is a source / drain metal, diffuses into the amorphous silicon layer thereunder, thereby forming a bond with silicon. Thus, the n + / p + doped layer 3 and the nickel / metal layer that are the source / drain metals are formed. Nickel-silicide (Ni-silicide) 5 is formed at the interface of the crystal, and the amorphous silicon layer is subsequently crystallized to form the polycrystalline silicon layer 6. At this time, the nickel-silicide (5) plays a large role in the crystallization of the amorphous silicon layer, and in general, since the silicide has a small resistance, the nickel-silicide (5) advantageously acts on ohmic contact (ohmic contact) do.

In addition, as the heat treatment is performed, activation of the doped region is performed.

Here, while the crystallization is in progress, the crystals are expanded to the channel region, where the laterally expanded region is very low in metal contamination. This is because most of the metal remaining after crystallization concentrates at the interface between the source / drain electrodes 4a and 4b and the polycrystalline silicon layer 6.

As a result, when the crystallization is performed according to the method of the present invention described above, the amorphous silicon layer portion under the source / drain electrode is crystallized in the form of MIC, and the channel region is crystallized in the form of MILC. There is little silicon contamination in the crystallized channel region.

On the other hand, when the heat treatment at 450 ~ 500 ℃ as described above, in the thin film transistor structure of the general reverse stagger type is not preferable because the other layers are subjected to heat stress. However, since the structure of the thin film transistor to be applied in the present invention is a coplanar structure, the stress caused by the heat of other layers is minimized so as not to affect the thin film transistor characteristics.

Referring to FIG. 1E, a gate insulating film 7 made of SiO 2 is deposited on the resultant to cover the source / drain electrodes 4a and 4b. Thereafter, a gate metal film is deposited on the gate insulating film 7, and then patterned to form a gate. As a result, the polysilicon thin film transistor 10 having a coplanar structure is completed.

According to the method of the present invention as described above, the channel region made of polycrystalline silicon is formed by applying a crystal extending out in the lateral direction of the amorphous silicon layer using a source / drain metal, so that the channel region by the remaining metal after crystallization Can minimize the contamination of silicon in the

As a result, reliability in forming a polysilicon thin film transistor can be ensured, and thus, a liquid crystal display device having a polysilicon thin film transistor can be stably manufactured.

Meanwhile, in the above-described embodiment of the present invention, the crystallization of the amorphous silicon layer is performed after the source / drain electrode is formed, but may be performed after the formation of the gate insulating film and the gate electrode. In this case, a thermal oxide film or a silicon oxide film should be used as the gate insulating film to minimize damage due to thermal stress.

2A to 2E are cross-sectional views for each process for explaining a method of manufacturing a polysilicon thin film transistor according to another embodiment of the present invention.

Referring to FIG. 2A, an amorphous silicon layer 22, a gate insulating layer 27, and a gate electrode metal layer 28a are sequentially deposited on the glass substrate 21.

Referring to FIG. 2B, the gate electrode metal film and the gate insulating film 27 are patterned according to a known process, thereby forming the gate electrode 28.

Referring to FIG. 2C, a dopant is implanted in an ion shower method at room temperature with respect to a substrate resultant according to a self-aligning method using the gate electrode 28 as an ion implantation mask, and thus, both sides of the gate electrode 28 are implanted. An n + / p + doped layer 23 is formed on the amorphous silicon layer portion surface.

Referring to FIG. 2D, not only silicide formation is easy on the entire region of the substrate, but also when the crystallization, a nickel film 24 advantageous for the formation of polycrystalline silicon is deposited. Then, the substrate resultant is heat-treated at 450 to 500 ° C., which is a temperature enough to form a MILC, and through this, nickel-silicide (25) at the interface between the nickel film 24 and the n + / p + doped layer 23. ), And the amorphous silicon layer is crystallized with the polycrystalline silicon layer 26.

Referring to FIG. 2E, the nickel film remaining without reacting during the heat treatment is removed. Then, a source / drain metal film is deposited on the substrate resultant, and then patterned to form a source electrode 24a and a drain electrode 24b on the nickel-silicide 25 on both sides of the gate electrode 28. This completes the manufacture of the polysilicon thin film transistor.

In this case, the source / drain electrodes 24a and 24b may be omitted. This is because the nickel-silicide 25 formed on the surface of the polysilicon layer on both sides of the gate electrode 28 may be used as an electrode because the resistance is very low, such as 2 to 20 mA.

The method of forming a polysilicon thin film transistor according to this embodiment forms a n + / p + doped layer by performing dopant ion implantation by self-alignment, so that the process can be simplified, and in particular, the doped layer is activated and recombined during subsequent crystallization. And since the diffusion, it is possible to form an excellent ohmic contact.

3A to 3D are cross-sectional views of processes for describing a method of manufacturing a polysilicon thin film transistor according to still another embodiment of the present invention.

Referring to FIG. 3A, an amorphous silicon layer 32 and a gate insulating film 37 are sequentially deposited on the glass substrate 31.

Referring to FIG. 3B, the gate insulating film 37 is patterned according to a known process. Then, the dopant is implanted in the ion shower method at room temperature in accordance with a self-alignment method using the patterned gate insulating layer 37 as an ion implantation mask, thereby allowing both sides of the patterned gate insulating layer 27 to be implanted. An n + / p + doped layer 33 is formed on the surface of the amorphous silicon layer portion of.

Referring to FIG. 3C, not only silicide formation is easy on the entire region of the substrate, but also when the crystallization, a nickel film 34 which is advantageous for the formation of polycrystalline silicon is deposited. Then, the substrate resultant is heat treated at 450 to 500 ° C., thereby forming nickel-silicide 35 at the interface between the nickel film 34 and the n + / p + doped layer 33, and furthermore, the amorphous silicon. The layer is crystallized with a polysilicon layer 36.

Referring to FIG. 3D, the nickel film remaining without reacting during the heat treatment is removed. Then, a metal film, for example, a nickel film, is deposited on the substrate resultant, and then patterned to form a gate electrode 38 on the patterned gate insulating film 37, and at the same time, nickel-on both sides of the gate electrode 38. A source electrode 34a and a drain electrode 34b are formed on the silicide 35, and as a result, the production of the polysilicon thin film transistor is completed.

Here, it is also possible to use this as an electrode material without removing the nickel film remaining without reacting during the heat treatment. In this case, it is important to ensure electrical insulation between the gate electrode and the source / drain electrodes.

In addition, when a low resistance metal is to be used as an electrode material, the low resistance metal may be deposited on the unreacted and remaining nickel film, and then patterned to form electrodes.

As described above, the present invention achieves crystallization of amorphous silicon by a method using a metal, but crystallization by applying a crystal extending in the lateral direction using a source / drain metal as a metal for crystallization, thereby achieving It is possible to prevent the silicon contamination, thereby ensuring the reliability of crystallization and to prevent the occurrence of leakage current can ensure the reliability of the thin film transistor.                     

In addition, since the crystallization method using a metal and the crystallization method using a laser form a thin film transistor after the formation of the polysilicon layer, the manufacturing process of the polysilicon thin film transistor is classified into two parts, a crystallization part and a thin film transistor manufacturing part. Therefore, the overall process is complicated, but the present invention can simultaneously achieve the process simplification because the crystallization and thin film transistor fabrication is performed at the same time.

In addition, by adding only the heat treatment equipment, it is possible to manufacture a polysilicon thin film transistor using the existing equipment as it is, it is also possible to prevent the increase in equipment investment costs.

In addition, since a thin film transistor is formed with a coplanar structure, a low-resistance metal can be used as the gate metal, and thus, it can be advantageously applied to the manufacture of a large-screen TFT-LCD.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (15)

Depositing an amorphous silicon layer on a glass substrate; Forming an n + / p + doping layer on a surface of the amorphous silicon layer; Depositing a source / drain metal film on the n + / p + doped layer; Patterning the source / drain metal film to form source and drain electrodes spaced apart from each other to define a channel region; Etching the n + / p + doped layer of the channel region between the source electrode and the drain electrode so that the amorphous silicon layer is exposed; Heat treating the amorphous silicon layer to form a metal-silicide layer at an interface between the source and drain electrodes and the n + / p + doping layer, and simultaneously form crystals through diffusion of the source and drain metals and the channel region of the formed crystal Crystallizing the amorphous silicon layer into a polysilicon layer through lateral expansion into the polysilicon layer; Depositing a gate insulating film on the source and drain electrodes to cover the crystallized polysilicon layer of the channel region; And And forming a gate electrode in the channel region on the gate insulating film. The method of claim 1, wherein the n + / p + doped layer A method of manufacturing a polysilicon thin film transistor, characterized in that formed by depositing a dopant doping layer. The method of claim 1, wherein the n + / p + doped layer A method of manufacturing a polysilicon thin film transistor, characterized in that formed by ion implantation of a dopant on the surface of the amorphous silicon layer. The method of claim 3, wherein the dopant ion implantation is performed by an ion shower method having a small acceleration voltage. The method of claim 4, wherein the dopant ion implantation is performed at room temperature. The method of claim 1, wherein the source / drain metal film is a nickel (Ni) film. The method of claim 1, wherein the heat treatment is performed at a temperature of 450 ~ 500 ℃ polycrystalline silicon thin film transistor manufacturing method. delete Sequentially depositing an amorphous silicon layer, a gate insulating film, and a gate metal film on a glass substrate; Patterning the gate metal film and the gate insulating film to expose the amorphous silicon layer to form a gate electrode; Performing dopant ion implantation using the gate electrode as a mask to form an n + / p + doping layer on the surfaces of the amorphous silicon layers on both sides of the gate electrode; Depositing a nickel film on the n + / p + doped layer to cover the gate electrode; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; And Removing the nickel film remaining unreacted during the heat treatment; The dopant ion implantation is a polysilicon thin film transistor manufacturing method characterized in that carried out by the ion shower method at room temperature. Sequentially depositing an amorphous silicon layer, a gate insulating film, and a gate metal film on a glass substrate; Patterning the gate metal film and the gate insulating film to expose the amorphous silicon layer to form a gate electrode; Performing dopant ion implantation using the gate electrode as a mask to form an n + / p + doping layer on the surfaces of the amorphous silicon layers on both sides of the gate electrode; Depositing a nickel film on the n + / p + doped layer to cover the gate electrode; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; And Removing the nickel film remaining unreacted during the heat treatment; The nickel-silicide film on the surface of the crystallized polysilicon layer is used as a source / drain electrode, polysilicon thin film transistor manufacturing method. Sequentially depositing an amorphous silicon layer, a gate insulating film, and a gate metal film on a glass substrate; Patterning the gate metal film and the gate insulating film to expose the amorphous silicon layer to form a gate electrode; Performing dopant ion implantation using the gate electrode as a mask to form an n + / p + doping layer on the surfaces of the amorphous silicon layers on both sides of the gate electrode; Depositing a nickel film on the n + / p + doped layer to cover the gate electrode; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; And Removing the nickel film remaining unreacted during the heat treatment; And removing source and drain electrodes on the nickel-silicide film on both sides of the gate electrode after removing the nickel film remaining unreacted at the time of heat treatment. . Sequentially depositing an amorphous silicon layer, a gate insulating film, and a gate metal film on a glass substrate; Patterning the gate metal film and the gate insulating film to expose the amorphous silicon layer to form a gate electrode; Performing dopant ion implantation using the gate electrode as a mask to form an n + / p + doping layer on the surfaces of the amorphous silicon layers on both sides of the gate electrode; Depositing a nickel film on the n + / p + doped layer to cover the gate electrode; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; And 10. The method of claim 8, comprising removing the nickel film remaining unreacted during the heat treatment. 10. The method of claim 8, wherein the heat treatment is performed at a temperature of 450 to 500 [deg.] C. Sequentially depositing an amorphous silicon layer and a gate insulating film on the glass substrate; Patterning the gate insulating layer to expose the amorphous silicon layer to define a channel region; Forming a n + / p + doped layer by implanting dopant ions into the exposed portion of the amorphous silicon layer using the patterned gate insulating film as a mask; Depositing a nickel film on the n + / p + doped layer to cover the gate insulating film; Heat-treating the amorphous silicon layer to form a nickel-silicide layer at an interface between the nickel film and the n + / p + doped layer, and at the same time, crystal formation through diffusion of the nickel film component and lateral expansion of the formed crystal into the channel region Crystallizing the amorphous silicon layer into a polycrystalline silicon layer through; Removing the nickel film remaining without reacting during the heat treatment; Depositing a metal film on the nickel-silicide layer to cover the gate insulating film; And And forming a source electrode and a drain electrode on the nickel-silicide layer on both sides of the gate electrode by patterning the metal layer to form a gate electrode on the gate insulating film. The method of claim 13, wherein the dopant ion implantation is performed by an ion shower method at room temperature. The method of claim 13, wherein the heat treatment is performed at a temperature of 450 to 500 ° C. 15.

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