KR20020076791A - Method for crystallizing a silicone layer and method for fabricating a thin film transistor using the same - Google Patents

Abstract

PURPOSE: A method for crystallizing a silicon thin film is provided to minimize the influence of Ni existing inside silicon and to completely eliminate the influence of Ni in a subsequent process, by minimizing formation of Ni to form a uniform thin film and by completely removing the Ni in an unnecessary portion. CONSTITUTION: An amorphous silicon thin film is formed on a substrate(40). A crystallizing acceleration material is formed in a part of the amorphous silicon thin film. The crystallizing acceleration material is etched. A heat treatment process is performed on the substrate to crystallize the amorphous silicon thin film.

Description

Crystallization method of silicon thin film and thin film transistor manufacturing method using same {METHOD FOR CRYSTALLIZING A SILICONE LAYER AND METHOD FOR FABRICATING A THIN FILM TRANSISTOR USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to thin film transistors (TFTs) fabricated using metal induced lateral crystallization (MILC) technology, and more particularly, to active layers forming the source, drain and channel of the thin film transistors. layer) and a method of manufacturing a TFT through this crystallization method.

Thin film transistors used in display devices, such as liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs), generally form a gate insulating layer and a gate electrode after depositing silicon on a transparent substrate such as glass or quartz. The dopant is injected into the drain and then annealed to activate the active layer. The active layer constituting the source, drain and channel of the thin film transistor is usually formed by depositing a silicon layer on a transparent substrate such as glass by using a chemical vapor deposition (CVD) method. However, the silicon layer deposited directly on the substrate by a method such as CVD has a low electron mobility as an amorphous silicon film. As display devices using thin film transistors require fast operation speeds and are miniaturized, the integration degree of the driving IC is increased and the aperture ratio of the pixel area is reduced. Therefore, the driving circuit is formed simultaneously with the pixel TFT by increasing the electron mobility of the silicon film, It is necessary to increase the pixel aperture ratio. For this purpose, a technique is used in which an amorphous silicon layer is heat-treated to crystallize into a crystalline silicon layer having a crystalline structure having high electron mobility.

A thin film transistor using a crystalline silicon thin film is a well-known device, and is manufactured by forming a semiconductor thin film such as silicon on or on a semiconductor substrate on which an insulating layer is formed. Thin film transistors are used in various integrated circuits, and in particular, switching elements formed in respective pixels of LCDs, drive circuits formed in peripheral circuits, and the like.

In order to obtain a polycrystalline silicon thin film used in such a device, as is well known, the deposited amorphous silicon should be heat treated at a temperature of 600 ° C. or higher. However, since the polycrystalline silicon thin film transistor as a device for driving the LCD must be formed on the glass substrate, the heat treatment temperature should be a low temperature of 600 ° C. or less, which is below the deformation temperature of the glass substrate. Therefore, in order to solve this problem, researches have been conducted in the following two directions.

The first direction is a method of melting and crystallizing a part of a silicon thin film by irradiating a laser. This method does not raise the temperature of the substrate and heats only a part of the silicon thin film, so crystallization is possible without deformation of the substrate, but there are problems such as crystallization uniformity, expensive manufacturing cost, and yield.

The second direction is a method called metal induced lateral crystallization (MILC) that reduces the crystallization temperature below 500 ° C by depositing a thin metal film on the amorphous silicon thin film. This method is a method of crystallizing amorphous silicon by depositing a metal thin film on an amorphous silicon thin film and then performing heat treatment in a blast furnace (furnace). This method has solved many problems such as crystallization uniformity and yield, which is a problem of the laser heat treatment method.

The method of manufacturing a conventional thin film transistor using MILC technology is as follows.

1A to 1F are process diagrams showing a process for manufacturing a conventional TFT using MILC technology.

FIG. 1A is a cross-sectional view of an amorphous silicon layer constituting an active layer of a thin film transistor formed on an insulating substrate 10 and patterned. Substrate 10 is comprised of an insulating material, such as Corning 1737 glass, quartz or silicon oxide, or oxidized silicon wafer. Optionally, a lower insulating layer (not shown) may be formed on the substrate 10 to prevent diffusion of contaminants from the substrate 10 into the active layer 11. The lower insulating layer may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof, such as PECVD (Plasma-Enhanced Chemical Vapor Deposition), LPCVD (Low-Pressure Chemical Vapor Deposition), or APCVD. (Atmosphere Pressure Chemical Vapor Deposition), ECR CVD (Electron Cyclotron Resonance CVD) using a deposition method such as a deposition of 300 to 10,000 Pa, preferably 500 to 3,000 Pa thickness at a temperature of 600 ℃ or less. The active layer 11 is formed by depositing amorphous silicon in a thickness of 100 to 3,000 Å, preferably 500 to 1,000 Å, using PECVD, LPCVD or sputtering. The active layer 11 includes a source region, a drain region and a channel region, and other element / electrode regions to be formed later. The active layer 11 formed on the substrate 10 is patterned to meet the specifications of the TFT to be manufactured.

FIG. 1B is a cross-sectional view of a structure in which a gate insulating layer 12 and a gate electrode 13 are formed on an active layer 11 that is panned with the substrate 10. The gate insulating layer 12 may be formed using a deposition method such as PECVD, LPCVD, APCVD, or ECR CVD to form silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof in a range of 300 to 3,000 Å It is preferably formed by deposition to a thickness of 500 to 1,000 mm 3. A conductive material such as a metal material or doped polysilicon on the gate insulating layer 12 was sputtered, evaporated, PECVD, LPCVD, APCVD, ECR CVD or the like by using a method such as 1,000 to 8,000 Å preferably 2,000. The gate electrode layer 13 is formed by depositing and patterning the gate electrode layer to a thickness of about 4,000 μm. The gate insulating layer 12 and the gate electrode 13 are patterned and etched using one mask. At this time, by overetching the gate electrode 13, as shown in FIG. 1B, the structure in which the gate electrode 13 cannot cover the outer part of the gate insulating layer 12 is obtained.

FIG. 1C is a view showing a step of doping the source region 11S and the drain region 11D of the active layer 11 using the gate electrode 13 as a mask. In manufacturing N-MOS TFTs, dopants such as PH ₃ , P, and As are ion-doped or ion implanted using an energy of 10 to 200 KeV (preferably 30 to 100 KeV) at 1E11 to 1E22 / cm ³ (good). For example, when doping with a dose of 1E15 to 1E21 / cm ³ ) and manufacturing a P-MOS TFT, dopants such as B ₂ H ₆ , B, and BH ₃ may be charged with energy of 1E11 to 1E22 / cm ^{3 at} an energy of 11 to 200 KeV. Doping is carried out with a dose of (preferably 1E14 to 1E21 / cm ³ ). In this case, a lightly doped drain (LDD) or an junction having an offset region may be formed in the drain region 11D. In the case of forming a CMOS, several doping processes using an additional mask may be performed.

1D is a cross-sectional view of the Ni metal layer 14 formed by depositing Ni thereon after the dopant is doped. The Ni metal layer 14 is offset from the channel region 11C covered by the gate insulating layer 12 and the gate electrode 13. Instead of Ni, metals such as Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt may be used, and one or more of these metals may be used. do. The crystallization-inducing metal including Ni may be applied by sputtering, heat deposition, PECVD or ion implantation, but sputtering is generally used. At this time, the deposition thickness of the Ni metal layer 14 should be a thickness that can form a metal thin film on the silicon surface to cause metal induced crystallization (Metal Induced Crystallization (MIC)) should be several tens of Å ~ hundreds of Å.

Thereafter, heat treatment is performed to induce crystallization of the active layer 11 and to activate dopants implanted into the source region 11S and the drain region 11D of the active layer 11. This process involves the use of tungsten-halogen or xenon arc heating lamps for short periods of time within a few minutes at temperatures of around 700 to 800 ° C, or ELCs for very short periods of time using excimer lasers. Law, a method of using a furnace, or the like can be used.

Then, the Ni metal layer 14 must be removed as shown in FIG. 1E. However, since Ni in contact with silicon or a silicon oxide film reacts with the underlying layer, removal is not easy. Thereafter, a transistor as shown in FIG. 1F is manufactured by a conventional method.

In the case of manufacturing the transistor by the conventional method as described above has the following problems. First, in order for the Ni metal layer 14 to be uniformly formed on the silicon thin film, it must be formed to have a thickness of at least 30 mm 3 or more. However, the amount of Ni required to generate the actual MIC or MILC is very small. Therefore, in order to form a uniform thin film, there is a problem in that Ni must be formed to a thickness greater than necessary, and when Ni deposited more than necessary is diffused into silicon during heat treatment, it may adversely affect the characteristics of the transistor. In order to solve such a problem, when Ni is formed very thin, uniformity may occur. In addition, in removing Ni after the heat treatment, Ni reacts with the underlying layer during the heat treatment, so that the removal is not easy. Therefore, Ni remaining unremoved may affect later manufacturing processes and may affect the characteristics and reliability of the transistor.

2 shows the crystallinity of the silicon thin film according to the thickness of Ni, a MILC source metal. As shown in the graph of FIG. 2, it can be seen that crystallization easily occurs even at a Ni thickness of 1 GPa. FIG. 3 shows the characteristics of a TFT composed of crystalline silicon which is crystallized by heat treatment after deposition of 1 Mb of Ni, a MILC source metal. As shown in the graph of FIG. 3, it can be seen that the TFT characteristics are also excellent even when 1 Å of Ni is formed. As such, although the deposition thickness of Ni for MILC is very thin, there is no problem, but the reason why Ni cannot be formed thin is due to uniformity.

Therefore, the present invention can minimize the influence of the MILC source metal present in the silicon by etching and heat treatment after forming the MILC source metal to a thickness capable of forming a uniform thin film, and the influence of the MILC source metal in subsequent processes An object of the present invention is to provide a method for crystallizing a silicon thin film that can be completely removed and a method for manufacturing a TFT through the crystallization method.

1A to 1F are process diagrams showing a method for manufacturing a conventional thin film transistor using MILC technology.

Figure 2 is a graph showing the crystallinity of the silicon thin film according to the thickness of Ni, a MILC elemental metal.

3 is a graph showing the characteristics of a TFT composed of crystalline silicon crystallized by heat treatment after depositing 1 Å of Ni, a MILC elemental metal.

4A to 4F are flowcharts illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

5A to 5E are process diagrams illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention.

6a to 6e is a process chart showing a manufacturing method of a thin film transistor according to another embodiment of the present invention.

7A to 7E are process diagrams illustrating a method of manufacturing a thin film transistor according to still another embodiment of the present invention.

8 is a graph showing the characteristics of the TFT produced by the method of the present invention.

♠ Explanation of symbols on the main parts of the drawing ♠

40: insulating substrate 41: amorphous silicon layer

41C: channel region 41D: drain region

41S: source region 42: gate insulating layer

43 gate electrode 44 Ni metal layer

45: Ni silicide thin film

According to a first aspect of the present invention for achieving the above object, a method of crystallizing a silicon thin film constituting the active layer of a thin film transistor, the method comprising the steps of: forming an amorphous silicon thin film on a substrate; Forming a crystallization promoting material on at least a portion of the amorphous silicon thin film; Etching the crystallization promoter; And crystallizing the amorphous silicon thin film into a crystalline silicon thin film by heat treating the substrate.

According to a second aspect of the present invention, a method of manufacturing a thin film transistor including a silicon thin film, comprising: forming an amorphous silicon thin film as an active layer constituting a source, a drain, and a channel region of a thin film transistor (TFT) on a substrate ; Forming a gate insulating layer and a gate electrode on the substrate and the active layer; Implanting dopants into the source and drain regions of the active layer and applying a crystallization promoting material; Etching the crystallization promoter; Heat-treating the substrate and the active layer formed on the substrate to crystallize the amorphous silicon thin film constituting the active layer into a crystalline silicon thin film; Forming a contact insulating layer on the substrate, the active layer and the gate electrode, and forming a contact hole in the contact insulating layer to expose a portion of the source region and the drain region; And forming a contact electrode electrically connecting the source region and the drain region to the outside through the contact hole.

According to a third aspect of the present invention, a method of manufacturing a thin film transistor including a silicon thin film, comprising: forming an amorphous silicon thin film as an active layer constituting a source, a drain, and a channel region of a thin film transistor (TFT) on a substrate ; Forming a gate insulating layer and a gate electrode on the substrate and the active layer; Implanting dopants into source and drain regions of the active layer; Forming a contact insulating layer on the substrate, the active layer and the gate electrode, and forming a contact hole in the contact insulating layer to expose a portion of the source region and the drain region; Applying a crystallization promoting material to the source and drain regions through the contact hole; Etching the crystallization promoter; Heat-treating the substrate and the active layer formed on the substrate to crystallize the amorphous silicon thin film constituting the active layer into a crystalline silicon thin film; And forming a contact electrode electrically connecting the source region and the drain region to the outside through the contact hole.

Hereinafter, with reference to the accompanying drawings will be described specific embodiments of the present invention.

4A to 4F are process diagrams illustrating a method of manufacturing a TFT using a MILC phenomenon according to an embodiment of the present invention. As shown in Figs. 4A to 4F, the TFT manufacturing method according to the present invention, unlike the conventional technique, is etched immediately after forming Ni metal layer by depositing Ni.

4A is a cross-sectional view of an amorphous silicon layer constituting an active layer of a thin film transistor formed on an insulating substrate 40 and patterned. Substrate 40 is comprised of an insulating material, such as Corning 1737 glass, quartz or silicon oxide, or oxidized silicon wafer. Optionally, a lower insulating layer (not shown) may be formed over the substrate 40 to prevent the diffusion of contaminants from the substrate 40 into the active layer 41. The lower insulating layer may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof, such as PECVD (Plasma-Enhanced Chemical Vapor Deposition), LPCVD (Low-Pressure Chemical Vapor Deposition), or APCVD. (Atmosphere Pressure Chemical Vapor Deposition), ECR CVD (Electron Cyclotron Resonance CVD) using a deposition method such as a deposition of 300 to 10,000 Pa, preferably 500 to 3,000 Pa thickness at a temperature of 600 ℃ or less. The active layer 41 is formed by depositing amorphous silicon in a thickness of 100 to 3,000 Å, preferably 500 to 1,000 Å, using PECVD, LPCVD or sputtering. The active layer 41 includes a source region, a drain region and a channel region, and other element / electrode regions to be formed later. The active layer 41 formed on the substrate 40 is patterned to meet the specifications of the TFT to be manufactured.

4B is a cross-sectional view of a structure in which a gate insulating layer 42 and a gate electrode 43 are formed on the substrate 40 and the active layer 41 that is panned. The gate insulating layer 42 may be formed using a deposition method such as PECVD, LPCVD, APCVD, or ECR CVD to form silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof in a range of 300 to 3,000 Å It is preferably formed by deposition to a thickness of 500 to 1,000 mm 3. A conductive material such as a metal material or doped polysilicon on the gate insulating layer 42 may be sputtered, evaporated, PECVD, LPCVD, APCVD, ECR CVD, or the like by using 1,000 to 8,000 Å preferably 2,000. A gate electrode 43 is formed by depositing and patterning the gate electrode layer to a thickness of about 4,000 μm. The gate insulating layer 42 and the gate electrode 43 are patterned and etched using one mask. At this time, by overetching the gate electrode 43, as shown in FIG. 4B, the structure in which the gate electrode 43 cannot cover the outer part of the gate insulating layer 42 is obtained.

4C is a diagram showing a step of doping the source region 41S and the drain region 41D of the active layer 41 using the gate electrode 43 as a mask. In manufacturing N-MOS TFTs, dopants such as PH ₃ , P, and As are ion-doped or ion implanted using an energy of 10 to 200 KeV (preferably 30 to 100 KeV) at 1E11 to 1E22 / cm ³ (good). For example, when doping with a dose of 1E15 to 1E21 / cm ³ ) and manufacturing a P-MOS TFT, dopants such as B ₂ H ₆ , B, and BH ₃ may be charged with energy of 1E11 to 1E22 / cm ^{3 at} an energy of 11 to 200 KeV. Doping is carried out with a dose of (preferably 1E14 to 1E21 / cm ³ ).

4D is a cross-sectional view of the Ni metal layer 44 formed by depositing Ni, which is a crystallization promoter, after doping the dopant. The Ni metal layer 44 is offset from the channel region 41C covered by the gate insulating layer 42 and the gate electrode 43. Thus, no additional photoresist process is required to offset the Ni metal layer 44 from the channel region 41C. Instead of Ni, metals such as Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt may be used, and one or more of these metals may be used. do. The crystallization promoter containing Ni may be applied by sputtering, heat deposition, PECVD or ion implantation, but sputtering is generally used. The thickness of the applied Ni metal layer 44 can be arbitrarily selected within the limits necessary to induce crystallization of the amorphous silicon layer, but is preferably formed in a thickness of approximately 1 to 10,000 mW, preferably 10 to 200 mW.

Then, the Ni metal layer 44 is etched. When the Ni metal layer 44 is etched, Ni in contact with the silicon surface reacts with the silicon to be changed into silicide and is not removed. Are all removed during the etching process. In addition, Ni formed more than necessary on the silicon surface is also removed during the etching process. At this time, the etching solution should have a selectivity between Ni and Ni silicide, for example, ferric chloride, 1HNO ₃ / 5HCl, 150CH ₃ COOH / 50HNO ₃ / 3HCl and the like. When the Ni metal layer 44 is etched as described above, a uniform Ni silicide thin film 45 is formed only on the silicon thin film as shown in FIG. 4E. As such, through the etching process of the Ni metal layer 44, the Ni metal layer may be formed to a minimum to form a uniform thin film, and the Ni metal layer of the unnecessary portion may be completely removed. As a result, the influence of Ni present in the silicon can be minimized, and the influence of Ni can be completely eliminated in subsequent processes.

Thereafter, heat treatment is performed to induce crystallization of the active layer 41 and to activate dopants implanted into the source region 41S and the drain region 41D of the active layer 41. This process involves the use of tungsten-halogen or xenon arc heating lamps for short periods of time within a few minutes at temperatures of around 700 to 800 ° C, or ELCs for very short periods of time using excimer lasers. Law, a method of using a furnace, or the like can be used. In an embodiment of the present invention, the active layer is crystallized using MILC which can crystallize amorphous silicon into crystalline silicon at a temperature of 300 to 700 ° C. lower than RTA. Crystallization of the active layer is preferably carried out in a furnace at a temperature of 300 to 700 ° C. for 0.1 to 50 hours, preferably 0.5 to 20 hours. At this time, the silicon in contact with the Ni silicide thin film 45 layer undergoes crystallization by MIC, and the rest of the silicon proceeds by MILC.

Thereafter, after forming the contact insulating layer on the substrate, the active layer and the gate electrode as in the conventional method, a contact hole is formed in the contact insulating layer so that a part of the source region and the drain region are exposed, and through the contact hole A transistor is fabricated as shown in FIG. 4F by forming a contact electrode which electrically connects the region and the drain region to the outside.

The present invention proceeds in the manner described above may change the order of the step of implanting the dopant and the process of forming the Ni metal layer of the MILC source metal.

Although the configuration of the present invention has been described with reference to the above embodiments, the present invention may be implemented in the form of other embodiments described below. Specific process conditions of other embodiments of the present invention may be executed under the same conditions as the above embodiment unless otherwise described.

5A to 5E are flowcharts illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention. As shown in FIG. 5A, an amorphous silicon layer is deposited on an insulating substrate 50 on which a buffer layer (not shown) is formed, and an active layer 51 is formed by patterning amorphous silicon by photolithography. Gate insulating layer 52 and gate electrode 53 are formed over active layer 50 using conventional methods.

As shown in FIG. 5B, the entire insulating substrate 50 is doped with a dopant using the gate electrode 53 as a mask to form a source region 51S, a channel region 51C, and a drain region 51D in the active layer 51. do. Then, as shown in FIG. 5C, the photoresist 54 is formed to cover the gate electrode 52, the source region 51S and the drain region 51D around the gate electrode, and the substrate 50 and the photoresist ( Ni metal layer 55 is deposited by depositing Ni, which is a crystallization promoting material, on the entire surface of 54).

Then, the Ni metal layer 55 is etched. When the Ni metal layer 55 is etched, Ni, which is in contact with the silicon surface, reacts with the silicon, changes into silicide, and is not removed. Both Ni and photoresist are removed during the etching process. In addition, Ni formed more than necessary on the silicon surface is also removed during the etching process. At this time, the etching solution should have a selectivity between Ni and Ni silicide, for example, ferric chloride, 1HNO ₃ / 5HCl, 150CH ₃ COOH / 50HNO ₃ / 3HCl and the like. When the Ni metal layer 54 is etched as described above, a uniform Ni silicide thin film 56 is formed only on the silicon thin film as shown in FIG. 5D.

Thereafter, heat treatment is performed to induce crystallization of the active layer 51 and to activate dopants injected into the source region 51S and the drain region 51D of the active layer 51. Then, the silicon in contact with the Ni silicide thin film 56 layer is crystallized by MIC, and the other portions are crystallized by MILC.

Thereafter, after forming the contact insulating layer on the substrate, the active layer and the gate electrode as in the conventional method, a contact hole is formed in the contact insulating layer so that a part of the source region and the drain region are exposed, and through the contact hole A transistor is fabricated as shown in FIG. 5E by forming a contact electrode for electrically connecting the region and the drain region to the outside.

The present invention proceeds in the manner described above may change the order of the step of implanting the dopant and the process of forming the Ni metal layer of the MILC source metal.

6A to 6F are flowcharts illustrating a method of manufacturing a thin film transistor according to still another embodiment of the present invention. 6A illustrates that an amorphous silicon layer 61 constituting an active layer of a thin film transistor is formed and patterned on an insulating substrate 60, and a gate insulating layer 62, a lower gate electrode 63, and an upper gate electrode 64 are formed thereon. ) Is a cross-sectional view.

FIG. 6B illustrates a process of using the upper gate electrode 64 as a mask to dop the dopant to the amorphous silicon layer 61 at a high concentration to form the source region 61S and the drain region 61D. After the doping with the dopant, as shown in FIG. 6C, the Ni metal layer 65 is formed by depositing Ni, which is a MILC source metal that promotes crystallization of the amorphous silicon layer 61, using the upper gate electrode 64 as a mask. At this time, if the width of the upper gate electrode 64 is made larger than the width of the lower gate electrode 63, since the crystallization inducing metal layer is not formed in the portion masked by the upper gate electrode 64, the channel region 61C is removed from the channel region 61C. There is an effect that the crystallization induced metal is offset by a certain distance.

After the Ni metal layer 65 is formed as described above, the upper gate electrode 64 is removed as shown in FIG. 6D. Then, the Ni metal layer 65 is etched. When the Ni metal layer 65 is etched, Ni, which is in contact with the silicon surface, reacts with the silicon, changes into silicide, and is not removed. Ni is all removed during the etching process. In addition, Ni formed more than necessary on the silicon surface is also removed during the etching process. At this time, the etching solution should have a selectivity between Ni and Ni silicide, for example, ferric chloride, 1HNO ₃ / 5HCl, 150CH ₃ COOH / 50HNO ₃ / 3HCl and the like. When the Ni metal layer 65 is etched as described above, a uniform Ni silicide thin film 66 is formed only on the silicon thin film as shown in FIG. 6E.

In the present invention, the step of doping the dopant and the step of forming the Ni metal layer, which is a MILC source metal, may be performed in a reversed order.

Thereafter, heat treatment is performed to induce crystallization of the active layer 61 and to activate dopants injected into the source region 61S and the drain region 61D of the active layer 61. Then, the silicon in contact with the Ni silicide thin film 66 layer is crystallized by MIC, and the other portions are crystallized by MILC.

Thereafter, after forming a contact insulating layer on the substrate, the active layer and the gate electrode as in the conventional method, a contact hole is formed in the contact insulating layer so that a part of the source region and the drain region are exposed, and through the contact hole A transistor is fabricated as shown in FIG. 6F by forming a contact electrode for electrically connecting the region and the drain region to the outside.

7A to 7F are flowcharts illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention. As shown in FIG. 7A, an amorphous silicon layer is deposited on an insulating substrate 70 on which a buffer layer (not shown) is formed, and an active layer 71 is formed by patterning amorphous silicon by photolithography. Gate insulating layer 72 and gate electrode 73 are formed over active layer 70 using conventional methods. As shown in FIG. 7B, the entire insulating substrate 70 is doped with a dopant using the gate electrode 73 as a mask to form a source region 71S, a channel region 71C, and a drain region 71D in the active layer 71. do.

FIG. 7C is a cross-sectional view of a structure in which a contact hole 75 is formed by forming and patterning a contact insulating layer 74 on the gate insulating layer 72 and the gate electrode 73 after the active layer 71 is doped. The contact insulating layer 74 is formed by depositing a method such as PECVD, LPCVD, APCVD, ECR CVD, sputtering, or the like to form a silicon oxide, silicon nitride, silicon oxynitride, or a composite layer thereof in a thickness of 1,000 to 15,000 Å, preferably 3,000 to 7,000 Å. It is formed by vapor deposition. The contact insulating layer 74 is wet or dry etched using a pattern formed by photolithography as a mask to form a contact hole 75 which provides a path for contact electrode contact with the source and drain regions of the active layer.

FIG. 7D shows that the Ni metal layer 76 is applied by depositing Ni, a MILC source metal that promotes crystallization of amorphous silicon constituting the active layer, in the source region 71S and the drain region 71D exposed in the contact hole 75. It is a cross section of the condition. FIG. 7E illustrates a state in which the Ni metal layer applied in the contact hole 75 is etched. When the Ni metal layer 76 is etched in this way, Ni in contact with the silicon surface reacts with the silicon to be changed into silicide, but is not removed. Ni formed more than necessary on the silicon surface is also removed during the etching process. At this time, the etching solution should have a selectivity between Ni and Ni silicide, for example, ferric chloride, 1HNO ₃ / 5HCl, 150CH ₃ COOH / 50HNO ₃ / 3HCl and the like. When the Ni metal layer 76 is etched as described above, a uniform Ni silicide thin film 77 is formed only on the silicon thin film as shown in FIG. 7E.

Thereafter, heat treatment is performed to induce crystallization of the active layer 71 and to activate dopants injected into the source region 71S and the drain region 71D of the active layer 71. Then, the silicon in contact with the Ni silicide thin film 77 layer is crystallized by MIC, and the other portions are crystallized by MILC. Thereafter, a contact electrode for electrically connecting the source region and the drain region to the outside through the contact hole 75 is formed to fabricate a transistor as shown in FIG. 7F.

8 is a graph showing the characteristics of a TFT manufactured by the method of the present invention. Each curve shown in Fig. 8 shows the characteristics of the TFTs of different portions of the substrate, and it can be seen that the characteristics of the TFTs are very excellent and the characteristics are very uniform throughout the substrate.

The present invention is a method of etching and heat-treating immediately after depositing Ni, a MILC source metal, to a thickness capable of forming a uniform thin film. Ni, which is in contact with the silicon surface when Ni is etched, reacts with silicon and converts it into Ni silicide. Although not removed, Ni formed in other portions and Ni formed more than necessary on the silicon surface are removed in the etching process. Therefore, by using the method of the present invention it is possible to form a uniform thin film by forming a minimum of Ni, there is an advantage that can be completely removed Ni of the unnecessary portion. Therefore, the present invention can minimize the influence of Ni present in the silicon, and has the effect of completely eliminating the influence of Ni in the subsequent process.

Although the contents of the present invention have been described with reference to the embodiments, the embodiments of the present invention are merely illustrative of the present invention and should not be construed as limiting the scope of the present invention. Those skilled in the art to which the present invention pertains may modify or alter the present invention in various forms within the principles and scope described in the claims herein.

Claims (22)

In the method of crystallizing the silicon thin film constituting the active layer of the thin film transistor, Forming an amorphous silicon thin film on the substrate; Forming a crystallization promoting material on at least a portion of the amorphous silicon thin film; Etching the crystallization promoter; And Heat treating the substrate to crystallize the amorphous silicon thin film into a crystalline silicon thin film. The method of claim 1, wherein the crystallization promoter is at least one metal of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt Silicon thin film crystallization method used. The method of claim 1, wherein the crystallization promoting material is formed by sputtering, evaporation, CVD, or ion implantation. 4. The method of claim 3, wherein the crystallization promoting substance is formed to a thickness of 10 to 200 GPa. The method of claim 1, wherein the heat treatment is performed by heat treatment using a blast furnace, RTA, or ELC. The silicon thin film crystallization method according to claim 5, wherein the silicon thin film is heat-treated at a temperature of 300 to 700 ° C in the blast furnace. The method of claim 1, wherein after the etching of the crystallization promoting material, the crystallization promoting material, which is in contact with the amorphous silicon thin film, remains as a silicide thin film. The method of claim 1, wherein the etching is performed with Ferric chloride, 1HNO ₃ / 5HCl or 150CH ₃ COOH / 50HNO ₃ / 3HCl. In the method for manufacturing a thin film transistor comprising a silicon thin film, Forming an amorphous silicon thin film as an active layer constituting a source, drain, and channel region of a thin film transistor (TFT) on a substrate; Forming a gate insulating layer and a gate electrode on the substrate and the active layer; Implanting dopants into the source and drain regions of the active layer and applying a crystallization promoting material; Etching the crystallization promoter; Heat-treating the substrate and the active layer formed on the substrate to crystallize the amorphous silicon thin film constituting the active layer into a crystalline silicon thin film; Forming a contact insulating layer on the substrate, the active layer and the gate electrode, and forming a contact hole in the contact insulating layer to expose a portion of the source region and the drain region; And And forming a contact electrode electrically connecting the source region and the drain region to the outside through the contact hole. 10. The method of claim 9, wherein the gate electrode is overetched to expose the gate insulating layer, and the crystallization promoting material is applied using the exposed gate insulating layer as a mask. The thin film transistor manufacturing method of claim 9, wherein the gate electrode is configured as a multi-gate electrode, and the crystallization promoting material is applied using a gate electrode having the largest area among the multiple gate electrodes as a mask. The method of claim 9, wherein the crystallization promoting material is applied using a photoresist formed on the gate insulating layer and the gate electrode as a mask. The thin film transistor manufacturing method according to any one of claims 8 to 12, wherein the dopant is injected after the crystallization promoting substance is applied. In the method for manufacturing a thin film transistor comprising a silicon thin film, Forming an amorphous silicon thin film as an active layer constituting a source, drain, and channel region of a thin film transistor (TFT) on a substrate; Forming a gate insulating layer and a gate electrode on the substrate and the active layer; Implanting dopants into source and drain regions of the active layer; Forming a contact insulating layer on the substrate, the active layer and the gate electrode, and forming a contact hole in the contact insulating layer to expose a portion of the source region and the drain region; Applying a crystallization promoting material to the source and drain regions through the contact hole; Etching the crystallization promoter; Heat-treating the substrate and the active layer formed on the substrate to crystallize the amorphous silicon thin film constituting the active layer into a crystalline silicon thin film; And And forming a contact electrode electrically connecting the source region and the drain region to the outside through the contact hole. The method according to claim 9 or 14, wherein the crystallization promoting material, Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt A thin film transistor manufacturing method using more than two kinds of metals. 15. The method of claim 9 or 14, wherein the crystallization promoting material is formed by sputtering, evaporation, CVD, or ion implantation. The method of claim 16, wherein the crystallization promoting material is formed to a thickness of 10 to 200 kPa. 15. The method of claim 9 or 14, wherein the heat treatment is performed by heat treatment using a blast furnace, RTA, or ELC method. The method of claim 18, wherein the thin film transistor is heat-treated at a temperature of 300 to 700 ° C. in the blast furnace. 15. The method of claim 9 or 14, wherein the crystallization promoter, which contacts the amorphous silicon thin film after etching the crystallization promoter, remains as a silicide thin film. 15. The method of claim 9 or 14, wherein the dopant is implanted using an ion implantation method or an ion shower doping method. 15. The method of claim 9 or 14, wherein the etching is performed with ferric chloride, 1HNO ₃ / 5HCl or 150CH ₃ COOH / 50HNO ₃ / 3HCl.