KR100599926B1 - Method for fabricating a thin film transistor including crystalline active layer and a semiconductor device - Google Patents

Abstract

In the present invention, the amorphous silicon thin film, the gate insulating layer, and the gate metal layer are sequentially stacked on the substrate in the process of manufacturing the crystalline silicon thin film transistor using MILC, and then the gate metal layer is patterned to form a gate electrode. The insulating layer and the amorphous silicon thin film are patterned to form an island type silicon active layer. According to the present invention, since the gate insulating layer and the amorphous silicon under the gate electrode are not removed in the process of patterning the active layer, the gate insulating layer and the amorphous silicon have a flat structure in which no step between the gate insulating layer and the gate electrode is formed at both ends of the active layer. In addition, amorphous silicon extends on both sides of the channel region of the active layer to absorb metal components used for crystallization of silicon, thereby improving operation characteristics of the thin film transistor.

Thin Film Transistors, MILC, Crystallization, Gate Electrode

Description

Method for manufacturing thin film transistor including crystalline active layer and semiconductor device {METHOD FOR FABRICATING A THIN FILM TRANSISTOR INCLUDING CRYSTALLINE ACTIVE LAYER AND A SEMICONDUCTOR DEVICE}             

1A to 5 are views for explaining an example of a conventional manufacturing process for manufacturing a crystalline silicon thin film transistor.

6 to 9 show another method of the conventional manufacturing process for manufacturing a crystalline silicon thin film transistor.

10 to 17 are views for explaining a process of manufacturing a crystalline silicon thin film transistor according to the present invention.

18 shows the shape and crystallization state of a silicon thin film formed in accordance with the present invention.

The present invention relates to a method of manufacturing a thin film transistor (Thin Film Transistor) including a crystalline silicon active layer and a semiconductor device manufactured through the same, and more particularly, to form a gate electrode after the active layer of the thin film transistor to form a gate electrode to form a gate The feature is that the silicon thin film under the electrode remains. According to the present invention, since the gate insulating layer and the gate metal layer are deposited without patterning the amorphous silicon thin film, there is an advantage that there is no contamination of the interface between the silicon and the gate insulating layer, and a step does not occur in the gate insulating layer and the gate electrode. In addition, there is an advantage that the amorphous silicon is extended in the channel region of the crystallized active layer to reduce the metal component concentration of the active layer.

As the current devices become larger and more integrated, transistor devices become thinner, and thus, amorphous silicon thin film transistors used in display devices are being replaced by polycrystalline silicon thin film transistors. Amorphous silicon thin film transistors can be easily made in transparent substrates such as glass and quartz with a process temperature of 350 ^° C. or lower, but they are difficult to use in high-speed operation circuits due to their low electron mobility. However, since polycrystalline silicon has higher electron mobility than amorphous silicon, a driving circuit can be formed on a substrate, which is advantageous as a transistor of a high resolution and large area device.

Crystallization into polycrystals after deposition of amorphous silicon includes solid phase crystallization (SPC), excimer laser annealing (ELA), and metal induced crystallization (MIC). . Here, the SPC method is a relatively simple crystallization method for producing a polycrystalline silicon thin film by heat treatment for a long time in the furnace (furnace) of 600 ^° C or more, but high crystallization temperature and long heat treatment time is essential. In addition, there are many defects inside the crystallized crystal grains, which makes it difficult to fabricate the device, and there is a disadvantage that the glass substrate cannot be used due to the high crystallization temperature which is higher than the deformation temperature of the glass substrate.

The ELA method is a method of crystallizing a thin film by instantaneously irradiating an excimer laser having a short wavelength of strong energy, capable of low-temperature crystallization of 400 ^° C. or below, and the production of crystal grains having large crystal grains and excellent characteristics. Due to uneven crystallization and expensive auxiliary equipment, mass production and large area devices are difficult to manufacture.

Metal Induced Lateral Crystallization (MILC) is a method of crystallizing amorphous silicon by depositing a metal thin film on an amorphous silicon thin film and then performing heat treatment in a furnace. This method has solved many problems such as crystallization uniformity and yield, which is a problem of laser heat treatment method, but it takes a lot of time for heat treatment because it requires several hours of heat treatment time at a temperature of about 500 ^o C in order to apply them in actual process. There is a problem. In addition, in the crystalline silicon manufactured by MILC, metal components such as nickel or nickel silicide that induce MILC remain, which causes current leakage, particularly in the channel region of the transistor.

1A to 5 are views for explaining a conventional process of manufacturing a crystalline thin film transistor using a metal-induced side crystallization method.

FIG. 1A is a plan view of an amorphous silicon thin film 11 constituting an active layer of a thin film transistor formed on an insulating substrate 10 and patterned. FIG. 1B illustrates one amorphous silicon island and a substrate of FIG. Sectional section cut along the. As illustrated, the amorphous silicon thin film 11 constituting the active layers of the plurality of thin film transistors connected to one word line (ie, the gate electrode) is patterned on the substrate 10 in a plurality of islands in a line. Although only four silicon islands are shown in the figures for convenience, those skilled in the art will recognize that additional amorphous silicon islands connected to one wordline on the substrate and amorphous silicon islands connected to adjacent wordlines are formed simultaneously. I can tell. 1A and 2A, only four silicon islands are shown connected to one gate electrode for convenience of description.

The substrate 10 is made of a transparent insulating material such as alkali free glass, quartz or silicon oxide. Optionally, a lower insulating layer (not shown) may be formed between the substrate and the amorphous silicon thin film to prevent contaminants from diffusing from the substrate into the amorphous silicon thin film. The lower insulating layer is formed of silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or APCVD. (Atmosphere Pressure Chemical Vapor Deposition), ECR CVD (Electron Cyclotron Resonance CVD), sputtering, etc., by using a deposition method such as deposition to a thickness of 300 to 10,000 Pa, preferably 500 to 3,000 Pa at a temperature of 600 ^° C or less. The amorphous silicon thin film 11 is formed by depositing amorphous silicon in a thickness of 100 to 3,000 Å, preferably 500 to 1,000 Å using PECVD, LPCVD or sputtering. The amorphous silicon thin film includes a source, a drain, and a channel region, and then includes other device / electrode regions to be formed. The amorphous silicon thin film formed on the substrate is patterned to meet the specifications of the TFT to be manufactured. In other words, the amorphous silicon thin film 11 is patterned by dry etching with plasma of etching gas using a pattern made by photolithography.

2A is a plan view illustrating a state in which the gate insulating layer 12 and the gate electrode 13 are sequentially stacked on the patterned amorphous silicon thin film 11, and FIG. 2B is cut along the line a-a ′ of FIG. 2A. One is a cross-sectional view of a silicon island and a substrate. The patterned gate insulating layer 12 and the gate electrode 13 extend across a number of amorphous silicon islands in a line providing an active layer of thin film transistors connected to one word line. The gate insulating layer 12 may be formed using a deposition method such as PECVD, LPCVD, APCVD, ECR CVD, and the like to form a silicon oxide, silicon nitride (SiNx), silicon oxynitride (SiOxNy) or a composite layer thereof in a range of 300 to 3,000 kPa, preferably It is formed by depositing to a thickness of 500 to 1,000Å. A conductive material such as a metal material or a doped polysilicon is formed on the gate insulating film using a method such as sputtering, heat evaporation, PECVD, LPCVD, APCVD, ECR CVD, sputtering, or the like, preferably 2,000 to 2,000 The gate electrode 13 is formed by depositing a gate metal layer with a thickness of 4,000 kHz and patterning it simultaneously with the gate insulating layer 12. The gate electrode 13 is patterned by wet or dry etching using a pattern made by photolithography.

FIG. 2C is a cross-sectional view taken along the line b-b 'of FIG. 2A. In the related art, since the gate insulating layer 12 and the gate metal layer 13 are formed after the island-type silicon thin film 11 is first patterned, the gate insulating layer 12 and the gate metal layer 13 are stepped on both sides of the silicon thin film. Will be achieved. Therefore, there is a high possibility that breakage occurs in the gate insulating layer or cracks occur in the gate metal layer at the stepped portion. In particular, cracking in the gate metal layer may cause a problem in signal transmission of the word line, which may cause a defect in the function of the thin film transistor panel. Accordingly, an object of the present invention is to increase the durability and reliability of the thin film transistor by preventing a problem in which a step difference between the gate insulating layer and the gate metal layer occurs on both sides of the silicon active layer as shown in FIG. 2C.

3 is a diagram illustrating a doping process for implanting impurities into the source 11S and the drain region 11D of the silicon thin film using the gate electrode 13 formed as shown in FIG. 2B as a mask. In case of manufacturing N-MOS TFT, dopant such as PH ₃ , P, As, etc. is converted into 1E11-1E22 / cm by energy of 10-200KeV (preferably 30-100KeV) using ion shower doping or ion implantation method. ³ (preferably 1E15-1E21 / cm ³ ) of doping, and when producing a P-MOS TFT, impurities such as B ₂ H ₆ , B, BH _3, etc., are charged at 1E11-1E22 with an energy of 20-70 KeV. doping with a dose of / cm ³ (preferably 1E14-1E21 / cm ³ ). In the case of forming a junction having, for example, a lightly doped region or an offset region in the drain region, or forming a CMOS, several doping processes using an additional mask are required. Figure 3 shows a process of doping an amorphous silicon island with impurities, but in practice impurity doping is done for all amorphous silicon islands formed on the substrate.

4 is a cross-sectional view of a metal layer 14 that induces MIC (Metal Induced Crystallization) or MILC of amorphous silicon after the silicon thin film is doped. Nickel (Ni), palladium (Pd), or cobalt (Co) is preferably used as the metal inducing MIC or MILC in amorphous silicon, but also Ti, Ag, Au, Al, Sn, Sb, Cu, Cr, Metals such as Mo, Tr, Ru, Rh, Cd, Pt can be used. MILC-derived metals such as nickel or palladium may be applied to amorphous silicon by sputtering, heat evaporation, PECVD or ion implantation, but sputtering is generally used. The thickness of the applied metal layer may be arbitrarily selected within the limits necessary to induce MIC or MILC of the amorphous conducting cone, and is formed to a thickness of about 1-10,000 mW, preferably 10-200 mW. In this process, since the channel region 11C is covered by the gate insulating film 12 and the gate electrode 13, the metal layer 14 is not applied to the channel region, and the metal layer is applied only to the source region 11S and the drain region 11D. do.

FIG. 5 shows a process of applying a metal layer 14 on a substrate and then performing a heat treatment to crystallize the amorphous silicon to induce crystallization of the amorphous silicon and simultaneously activate impurities implanted in the source and drain regions of the silicon. This process uses a tungsten-halogen or xenon arc heating lamp to heat for a very short time using a rapid annealing (RTA) method or an excimer laser that heats for a short time within minutes at temperatures of 700 or 800 ^o C. The ELC method or the like may be used, and is preferably performed in a furnace at a temperature of 400-600 ^° C. for 0.1-50 hours, preferably 0.5-20 hours. Through the heat treatment process in the reactor, the source and drain region to which the MIC source metal is applied is crystallized by MIC phenomenon, and the source and drain region and channel region to which the MILC source metal is not applied are MILC propagated from the portion where the metal layer is applied. Crystallized by Arrows of Figure 5 indicate the direction in which the MILC proceeds during the heat treatment process.

When the impurity implantation and crystallization heat treatment of the active layer is completed, as shown in FIG. 5, an overcoat is formed on the substrate, a contact hole for electrical connection is formed, and a contact electrode for connecting the source and drain regions of the amorphous silicon thin film to an external circuit through the contact hole. To form a thin film transistor. Since the process after Figure 5 is the same as the conventional thin film transistor process, a detailed description thereof will be omitted.

6 through 9 form a contact hole in the overcoat instead of applying the crystallization inducing metal to the active layer using the gate electrode as a mask as shown in FIG. 4 and crystallization inducing metal in the source region and the drain region of the active layer through the contact hole. Another conventional process for crystallizing the active layer by applying is shown.

6 is a cross-sectional view of a structure in which an overcoat 16 serving as a contact insulating layer is formed on the gate insulating film 12 and the gate electrode 13 after the silicon thin film is doped, and then patterned to form the contact hole 15. . FIG. 7 is a cross-sectional view of a metal layer 14 for inducing MIC (Metal Induced Crystallization) or MILC of amorphous silicon constituting an active layer to a source region 11S and a drain region 11D exposed in a contact hole. FIG. 8 illustrates a process of forming a MIC source metal layer 14 in a contact hole and then performing heat treatment to induce crystallization of amorphous silicon and to activate impurities implanted into the source and drain regions of silicon. Arrows in FIG. 8 indicate the direction of the MILC. 9 is a cross-sectional view of a state in which a contact electrode 20 is formed to connect an external circuit with a source and drain region of an amorphous silicon thin film through a contact hole after crystallizing amorphous silicon through heat treatment.

Using the process of FIGS. 6 to 9 has the advantage that the crystallization induction metal can be offset from the channel region of the active layer without using a separate mask. Techniques and advantages of applying a crystallization inducing metal to a portion of a source region and a channel region through a contact hole are described in detail in Korean Patent Application No. 2000-64352 of the applicant.

The conventional process described above uses a process of depositing and patterning amorphous silicon on a substrate as shown in FIGS. 1A and 1B and then depositing and patterning a gate insulating layer and a gate electrode as shown in FIGS. 2A and 2B. In the conventional process, the deposition and patterning process of the amorphous silicon and the deposition process of the gate insulating layer and the gate metal layer are discontinuous, so that the patterned amorphous silicon is exposed to the air and contaminated, thus degrading the characteristics of the transistor and forming the gate insulating layer. There was a problem of cleaning the substrate before the following. In addition, in the conventional process, the gate insulating layer and the gate metal layer are deposited after the amorphous silicon thin film is patterned in an island form in order to provide an active layer of the thin film transistor. Thus, the step difference between the gate insulating layer and the gate metal layer is formed at both ends of the active layer as shown in FIG. There was a problem that the probability of occurrence of mechanical defects increased. In addition, according to the conventional process, a metal component such as nickel or nickel silicide used to induce crystallization of amorphous silicon is introduced into the channel region while crystallizing the amorphous silicon on both sides of the channel, and remains in the crystallized channel region, particularly the crystallization interface, to form a thin film. There is a problem of deteriorating operating characteristics such as off current of a transistor.

The present invention is to solve the problems of the prior art as described above, the present invention after the continuous deposition of the amorphous silicon thin film, the gate insulating layer and the gate metal layer on the substrate patterning the gate metal layer and the amorphous silicon thin film and the amorphous silicon and It is an object of the present invention to provide a thin film transistor manufacturing process and structure capable of preventing interfacial contamination between gate insulating layers and omitting a cleaning process. In addition, an object of the present invention is to improve the durability and reliability of the thin film transistor by preventing the step difference between the gate insulating layer and the gate metal layer on both sides of the active layer. In addition, an object of the present invention is to significantly reduce the concentration in the channel of the metal component used to induce crystallization of the active layer to improve the operating characteristics of the thin film transistor.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment for achieving the object of the present invention. In the following drawings, like elements are indicated using like reference numerals. In addition, it is to be understood that the process conditions used in the embodiments of the present invention described below are the same as those described in connection with the prior art unless otherwise stated.

As shown in FIG. 10, the amorphous silicon thin film 21 is deposited on the substrate 20, and the gate insulating layer 22 and the gate metal layer 23 are successively deposited without patterning the amorphous silicon thin film. The amorphous silicon thin film 21, the gate insulating layer 22, and the gate metal layer 23 are deposited under the same conditions as described above with respect to the prior art, and the substrate is exposed to the atmosphere to deposit and pattern the amorphous silicon on the substrate. There is a difference from the prior art in that the gate insulating layer 22 and the gate metal layer 23 are continuously deposited without being made. In order to pattern the amorphous silicon thin film, the substrate must be taken out of the deposition apparatus to perform the photolithography and etching process. However, in the present invention, the amorphous silicon thin film, the gate insulating layer, and the gate metal layer may be continuously deposited on the substrate while maintaining the vacuum state in the evaporator. Alternatively, before depositing a silicon thin film on the substrate, a buffer layer may be deposited to prevent diffusion of contaminants. According to the present invention, a gate metal layer may be formed from the buffer layer by a continuous deposition process. Cluster type evaporator capable of performing such a continuous deposition process is described in detail in the Patent Application Publication No. 2002-62463, etc. filed by the present applicant, a detailed description of the continuous evaporator used in the present invention will be omitted. Continuously depositing the gate insulating layer and the gate metal layer on the amorphous silicon as in the present invention, since the insulating layer is coated in a state where the amorphous silicon is not exposed to the outside, it is possible to prevent contamination of the interface between the amorphous silicon and the gate insulating layer at the source. And, even without using a separate cleaning process there is an advantage that can provide a high purity silicon layer. In the present exemplary embodiment, the gate insulating layer and the gate metal layer are continuously deposited on the silicon thin film, but a person having ordinary knowledge in the art to which the present invention pertains continuously forms the silicon thin film and the gate insulating layer within the scope of the present invention. After deposition, it can be seen that the gate metal layer may be deposited using a separate deposition process.

The gate metal layer 23 is then patterned in the form of a gate electrode, as shown in FIG. 11A. The patterned gate electrode constitutes a word line of the thin film transistor array. The gate electrode 23 is patterned by wet or dry etching, which can selectively remove only the gate metal using a pattern made by photolithography. FIG. 11B is a cross-sectional view taken along the line c-c 'of FIG. 11A.

After the gate electrode 23 is patterned, impurities are doped in the entire substrate as shown in FIG. 12. Since the impurity must be injected into the source region and the drain region on both sides of the gate electrode 23 through the gate insulating layer 22, the impurity is implanted using a relatively high energy that can pass through the gate insulating layer. A person skilled in the art can appropriately adjust the impurity implantation energy according to the type of impurity and the type and thickness of the gate electrode. The concentration of the impurity and the method of implanting the amorphous silicon thin film according to the impurity type are the same as described above with respect to the prior art. In the present embodiment, it has been described that the impurity is implanted after patterning the gate electrode, but the impurity may be implanted after patterning the active layer as shown in FIGS. 13A to 13C within the principles and range of the present invention.

FIG. 13A shows a state in which an amorphous silicon thin film which provides an active layer of a thin film transistor using a photoresist as a mask after implanting impurities is patterned in an island form. Silicon islands are formed in an appropriate size to form an active layer and are formed in an appropriate number along the gate electrode 23 providing a word line. Patterning the silicon islands consists of etching the gate insulating layer 22 using dry or wet etching and a two step etching process of etching the amorphous silicon 21. In the present exemplary embodiment, since the gate insulating layer 22 and the silicon thin film 21 are patterned in the same shape, they may be sequentially patterned using one photoresist. In this etching step, the gate electrode 23 is not affected during the etching process by using an etchant that selectively removes only the gate insulating layer and the amorphous silicon without using an etchant that reacts with the gate metal. Optionally, when the photoresist for patterning the silicon island is further formed on the gate electrode 23 without removing the photoresist used for patterning the gate electrode 23, the gate metal layer may be formed regardless of the type of etching agent used. It is not affected by the etching process.

FIG. 13B is a cross-sectional view of one silicon island cut along the line d-d 'in FIG. 13A. When the gate insulating layer and the silicon thin film on both sides of the gate electrode are patterned as shown in FIG. 13B, the basic structure of the thin film transistor in which the silicon active layer 21, the gate insulating layer 22, and the gate metal layer 23 are sequentially provided is provided.

FIG. 13C is a cross-sectional view taken along the line e-e ′ in the longitudinal direction of the gate electrode in FIG. 13A. As shown in FIG. 13C, the present invention is a patterned gate metal layer because the silicon thin film 21, the gate insulating layer 22, and the gate metal layer 23 are sequentially deposited on the substrate 20 and the gate electrode and the silicon island are patterned. That is, the silicon thin film and the gate insulating layer under the gate electrode remain intact in the silicon island patterning process. Therefore, according to the present invention, a step between the silicon thin film 21 and the gate insulating layer 22 is not formed along the length direction of the gate electrode 23, and thus a flat stacked structure is formed as shown in FIG. 13C. Compared with FIG. 2C and FIG. 13C, the difference between the prior art and the present invention can be more clearly understood. In the related art, since the gate insulating layer 12 and the gate metal layer 13 are laminated after the silicon active layer 11 is patterned in an island form, a step between the gate insulating layer and the gate metal layer is formed at both ends of the silicon active layer as shown in FIG. 2C. There was no choice but to be. According to the present invention, since the silicon thin film under the gate metal layer remains to extend between the island-type silicon thin films as shown in FIG. 13C, it is possible to prevent a problem in which a step between the gate insulating layer and the gate metal layer is formed on both sides of the silicon thin film. When the gate insulating layer is deposited on the silicon thin film in which the step is formed, it is difficult to control the deposition thickness and uniformity of the insulating material at the corners of the step. In addition, it is difficult to maintain the deposition thickness and uniformity of the gate metal layer at the stepped corners, thereby increasing the risk of disconnection of the metal layer. According to the present invention, since the gate insulating layer and the metal layer are deposited on the flat amorphous silicon layer, it is possible to fundamentally prevent a problem that defects occur in the gate insulating layer and the gate metal layer at the stepped portion.

According to the present invention, the amorphous silicon thin film under the gate metal layer providing the word line remains so that the active layers of adjacent thin film transistors using the common gate electrode are connected by amorphous silicon without being separated from each other. In this case, there may be a problem of leakage of current between adjacent thin film transistors. However, since amorphous silicon has a very high resistivity compared to the crystalline silicon active layer provided by the present invention, the transistor is actually formed as compared to the case where the active layer of the thin film transistor is formed in an island form. There is little difference in operation and function. The method according to the invention is much more advantageous than the drawback of current leakage between the silicon islands without forming a step between the gate metal layer and the gate insulation layer. Meanwhile, as will be described later, the present invention greatly reduces a metal component remaining in a thin film transistor by dispersing metal or metal silicide remaining in a channel region of a thin film transistor crystallized using a crystallization inducing metal into an amorphous silicon extending between active layers. There is an advantage to improve the operating characteristics, in particular the off current characteristics.

When the doping process is completed, the overcoat 24 serving as the contact insulating layer is formed on the gate insulating film 22 and the gate electrode 23 as shown in FIG. 14, and the overcoat is patterned as shown in FIG. 15 to form the contact hole 25. do. The overcoat is formed by depositing silicon oxide, silicon nitride, silicon oxynitride or a composite layer thereof in a thickness of 1,000 to 15,000 Å, preferably 3,000 to 7,000 하여 using a deposition method such as PECVD, LPCVD, APCVD, ECR CVD, sputtering, or the like. do. The overcoat is wet or dry etched using a pattern formed by a method such as photolithography as a mask, thereby forming a contact hole 25 which provides a path for contact electrode contact with the source and drain regions of the silicon thin film.

FIG. 16 is a cross-sectional view of a metal layer 26 for inducing MIC (Metal Induced Crystallization) or MILC of amorphous silicon to a part of a source region and a drain region of an active layer through a contact hole. Nickel (Ni), palladium (Pd), and cobalt (Co) are preferably used as metals that induce MIC or MILC in amorphous silicon, but Ti, Ag, Au, Al, Sn, Sb, Cu, Cr, Metals such as Mo, Tr, Ru, Rh, Cd, Pt can be used. MILC-derived metals such as nickel or palladium may be applied to amorphous silicon by sputtering, heat evaporation, PECVD or ion implantation, but sputtering is generally used. The thickness of the applied metal layer may be arbitrarily selected within the limits necessary to induce MIC or MILC of the amorphous conducting cone, and is formed to a thickness of about 1-10,000 mW, preferably 10-200 mW. The metal layer applied to the portions other than the contact holes may be removed at the same time when the photoresist or the like used as a mask is removed by a method such as lift off to form the contact holes in the overcoat.

FIG. 17 illustrates a process of forming a crystallization inducing metal layer 26 inside a contact hole and then performing heat treatment to induce crystallization of amorphous silicon and to activate impurities implanted into the source and drain regions of silicon. This process uses a tungsten-halogen or xenon arc heating lamp to heat for a very short time using a rapid annealing (RTA) method or an excimer laser that heats for a short time within minutes at temperatures of 700 or 800 ^o C. The method and the like may also be used, preferably in a furnace at a temperature of 400-600 ^° C. for 0.1-50 hours, preferably 0.5-20 hours. Source and drain regions where MIC source metal 26 is directly applied through contact holes are crystallized by MIC phenomenon, and source and drain regions and channel regions where MILC source metal is not applied propagate from portions where source metal is applied. The crystallization phenomenon is propagated by MILC. Arrows in FIG. 17 indicate the progress direction of the MILC.

After the heat treatment is completed, a thin film transistor is completed by forming a contact electrode through a contact hole according to a conventional method.

18 is a view showing a state of a silicon thin film in a state where crystallization is completed. According to the present invention, since the island-type silicon thin film providing the active layer is patterned after forming the gate metal layer, the silicon thin film having a shape corresponding to the gate metal layer remains between the active layer islands. In the heat treatment process described with reference to FIG. 17, crystallization proceeds from the portion to which the crystallization induction metal 26 is applied to form a crystallization interface at the center of the active layer. MILC induces crystallization of silicon while crystallization inducing metals such as nickel react with amorphous silicon to form silicides, and induce crystallization of silicon laterally as the silicide propagates along the crystallization tip. Therefore, in FIG. 18, a relatively high concentration of the metal component remains in the channel region under the gate electrode, particularly in the crystallization interface. This residual metal component acts as a factor in lowering the operating characteristics of the thin film transistor crystallized using MILC, in particular, the off current characteristic. Therefore, in the conventional technology of manufacturing crystalline silicon TFTs using MILC, it is an important technical problem to lower the concentration of metal components remaining in the channel region.

The active layer of the thin film transistor fabricated according to the present invention is connected by an amorphous silicon connection part 27 extending between channel portions of adjacent active layers as shown in FIG. Therefore, when the crystallization proceeding from both sides of the active layer reaches the center portion of the active layer, the crystallization proceeds into the amorphous silicon connecting portion 27 connected to the active layer. As is well known, since amorphous silicon has a much higher solubility of metal components than crystalline silicon, the metal components remaining in the channel region of the active layer are rapidly absorbed into the amorphous silicon connection and lead to crystallization of this region. When the heat treatment is terminated when the crystallization proceeds by a predetermined distance into the amorphous silicon connection portion, a constant region of the connection portion may remain as amorphous silicon to provide insulation between the active layer islands. The present invention allows the metal component introduced into the channel region to rapidly diffuse into the amorphous silicon connection connected to the side of the channel region as the MILC progresses, thereby significantly reducing the concentration of the metal component remaining in the crystallized active layer, particularly the channel region. It is possible to prevent the problem of deterioration of the operating characteristics of the thin film transistor.

While the content of the present invention has been described by way of examples, the embodiments of the present invention are merely illustrative of the present invention and should not be construed as limiting the scope of the present invention. For example, the above embodiment has been described using two processes of manufacturing a thin film transistor as an example, but the present invention may be used in other types of manufacturing processes. Those skilled in the art to which the present invention pertains may modify or alter the present invention in various forms within the principles and scope described in the claims herein.

For example, in the embodiment described above, as shown in FIG. 13B, the gate insulating layer and the amorphous silicon thin film are patterned in the same form. However, within the principles and scope of the present invention, in the process of patterning the gate insulating layer and the amorphous silicon thin film, the gate insulating layer of all regions except the lower region of the gate electrode may be removed, and only the amorphous silicon thin film may be patterned in an island form. In this case, instead of applying the crystallization inducing metal to the amorphous silicon thin film through the contact hole, as shown in FIGS. 3 to 5 can be used to crystallize by directly applying the crystallization inducing metal to the amorphous silicon. In addition, in the above embodiment, only one gate electrode is formed in the thin film transistor, but it is apparent that the gate electrode may be formed in a dual manner within the principle and scope of the present invention.

According to the present invention, amorphous silicon, a gate insulating layer and a gate metal layer are sequentially deposited on the substrate without a patterning process. Therefore, as compared with the conventional process of patterning the amorphous silicon layer before depositing the gate insulating layer and the gate metal, the interface between the amorphous silicon and the gate insulating layer is not exposed to the air, thereby preventing contamination of the interface. In addition, since the silicon layer under the gate insulating layer and the gate metal layer is not removed, a step difference between the gate insulating layer and the gate metal layer is not formed at both sides of the active layer, thereby preventing a problem that a defect occurs at the step portions of the gate insulating layer and the gate metal layer. have. The present invention can also effectively reduce the metal component remaining in the channel portion of the active layer to improve the operating characteristics of the thin film transistor.

Claims (13)

In the method of forming a crystalline silicon thin film transistor on a substrate, Continuously depositing an amorphous silicon thin film and a gate insulating layer on the substrate; Forming a gate electrode on the gate insulating layer; Patterning the gate insulating layer and the amorphous silicon thin film to form a plurality of island-type silicon active layers; Applying a crystallization inducing metal to at least a portion of the silicon active layer; Thermally treating the substrate to crystallize the silicon active layer; And the gate electrode extends across the channel regions of the plurality of island-like active layers, and the amorphous silicon thin film remains on the entire lower region of the gate electrode during the patterning of the silicon active layer. delete The method of claim 1, wherein a buffer layer to prevent diffusion of contaminants on the substrate is continuously deposited together with the amorphous silicon thin film and the gate insulating layer. 4. The method of claim 1 or 3, wherein the gate electrode is formed by successively depositing a gate metal layer on the gate insulating layer and patterning only the gate metal layer. The method of claim 1, further comprising forming an overcoat on the substrate and forming a contact hole in the overcoat after patterning the amorphous silicon thin film, wherein the crystallization inducing metal is formed in the silicon active layer through the contact hole. Applied. The method of claim 1, wherein after forming the gate electrode, impurities are implanted into the amorphous silicon before or after patterning the silicon active layer. The method of claim 1, wherein at least a portion of the amorphous silicon thin film in the lower region of the gate electrode extending outside the silicon active layer is crystallized during the heat treatment. The method of claim 1, wherein the crystallization inducing metal comprises at least one of Ni, Pd, and Co, and heat treatment of the substrate is performed using a blast furnace. 2. The method of claim 1, wherein at least two gate electrodes are formed in each thin film transistor in parallel. A plurality of island-like crystalline silicon active layers formed on the substrate; In the crystalline silicon thin film transistor panel comprising a gate insulating layer and a gate electrode formed on the crystalline silicon active layer, The silicon active layer is crystallized by applying a crystallization inducing metal to at least a portion of the silicon active layer and heat treatment, the gate electrode extends across the channel region of the plurality of island-type silicon active layer and in all regions below the gate nationwide A crystalline silicon thin film transistor panel, wherein a silicon thin film remains. The crystalline thin film transistor panel of claim 10, wherein an overcoat is formed on the silicon active layer and the crystallization inducing metal is applied to the active layer through a contact hole formed in the overcoat. The crystalline thin film transistor panel according to claim 10, wherein the gate electrode is formed of parallel double gate electrodes. The crystalline thin film transistor panel according to claim 10, wherein at least a portion of the silicon thin film remaining in the lower region of the gate electrode extending outside of the active layer is crystallized.

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