JP3613221B2 - Thin film transistor manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a top gate type thin film transistor, and more particularly to a method for manufacturing a top gate type thin film transistor formed on an insulating substrate such as a liquid crystal display and a contact image sensor.
[0002]
[Prior art]
In a liquid crystal display device (LCD), an amorphous silicon thin film transistor (TFT) -LCD is the mainstream. However, with amorphous silicon TFTs, it is difficult to realize a high-definition LCD with a large screen. Therefore, TFTs having a higher mobility polysilicon thin film as an active layer are attracting attention.
[0003]
On the other hand, due to the diversification of applications in LCDs, there are strong demands for thinning and miniaturization, and in order to meet these demands, attempts have been made to form drive circuits with TFTs on an active matrix substrate as well. . However, it is not preferable to form the TFT for driving circuit using an amorphous silicon thin film in terms of operation speed and driving capability, and it is required to form the TFT using a polysilicon thin film. As a method for producing a polysilicon thin film, a laser annealing method capable of forming a polysilicon thin film on an inexpensive low-temperature glass substrate is becoming mainstream from the viewpoint of lowering the process temperature, improving the throughput, and reducing the cost.
[0004]
However, in the general polysilicon TFT, there are problems that the reliability of the gate wiring is low, it is difficult to reduce the resistance, and it is difficult to increase the definition of the LCD. In order to avoid this problem, for example, as disclosed in JP-A-5-235353, it is conceivable that the gate wiring is a two-layer wiring of a polysilicon thin film and a metal thin film.
[0005]
FIG. 6 is a cross-sectional view showing the structure of a polysilicon TFT in which the gate wiring is made into two layers. A base oxide film 2 is formed on a low-temperature glass substrate 1, a polysilicon thin film 3 is selectively formed on the base oxide film 2, and source / drain regions 7 are formed on both sides thereof. A gate insulating film 4 is formed so as to cover the polysilicon thin film 3 and the source / drain regions 7, and the source is formed through contact holes formed in the gate insulating film 4 and the interlayer insulating film 9 thereabove. A metal wiring 10 is formed so as to be in contact with the drain region 7. Further, a two-layer gate electrode composed of a lower polysilicon thin film 11 and an upper metal thin film 6 is formed on the gate insulating film 4 at a position matching the polysilicon thin film 3. These layers are covered with an interlayer insulating film 9.
[0006]
However, in the conventional thin film transistor in which the gate wiring is made into two layers using this polysilicon thin film 11, the process temperature of the gate formation reaches an extremely high temperature of 600 ° C. in the film forming process and 850 ° C. in the phosphorus diffusion process. In addition, there is a problem that the substrate heating and cooling time is large, and the throughput is lowered. Further, the temperature of 600 ° C. or higher is a temperature higher than the softening point of an inexpensive low-temperature glass substrate. For this reason, since it is necessary to use an expensive quartz substrate for the TFT substrate, the manufacturing cost increases.
[0007]
Further, one of the serious problems of the polysilicon TFT is a large leakage current. In order to avoid this problem, for example, as disclosed in JP-A-58-204570, JP-A-1-125866, JP-A-5-152326, JP-A-7-106582, etc. A so-called LDD (Lightly Doped Drain) structure having a low-concentration impurity region at the drain end of a TFT, or an overlap as disclosed in, for example, JP-A-6-37314 and JP-A-7-202210 It is conceivable to adopt an LDD structure.
[0008]
FIG. 7 shows these LDD-TFT structures. A low-concentration LDD region 8 is formed between the polysilicon thin film 3 and the source / drain region 7, and a gate insulating film 4 is formed on the LDD region 8 and the polysilicon thin film 3. A metal gate electrode 6 is formed in a selected region on the film 4.
[0009]
FIG. 8 shows another conventional LDD-TFT structure. In this LDD-TFT, a gate insulating film 4 is formed so as to cover the source / drain region 7, the LDD region 8 and the polysilicon thin film 3, and the LDD region 8 and the polysilicon thin film 3 on the gate insulating film 4 are formed. A gate electrode made of a lower polysilicon thin film 11 is formed in a region immediately above, and a gate electrode made of an upper polysilicon thin film 11 having a narrower width than the lower layer is formed thereon.
[0010]
[Problems to be solved by the invention]
However, the LDD-TFT including the conventional overlap LDD structure has a problem that the number of steps increases and throughput decreases. For example, in Japanese Patent Laid-Open No. 58-204570 and Japanese Patent Laid-Open No. 7-106582, an impurity introduction step is required twice. For example, in Japanese Patent Laid-Open No. The gate electrode formation process up to the above is required twice. For example, in Japanese Patent Application Laid-Open No. 7-202219, the anodization process of the upper gate electrode and the removal process of the anodized part are necessary.
[0011]
Further, in these LDD-TFTs, it is difficult to improve the reliability and lower the resistance of the gate wiring described above. For example, in Japanese Patent Application Laid-Open Nos. 58-204570, 1-125866, and 6-37314, only a polysilicon thin film that has a high resistance and is formed by a high-temperature process is used as a gate electrode. For example, in Japanese Patent Laid-Open Nos. 5-152326 and 7-202210, only a thin metal film having low reliability is used for the gate electrode (FIG. 7).
[0012]
An activation step needs to be performed after the impurity implantation step including LDD, and the process temperature of the activation step is also one of the problems of the polysilicon TFT. For example, in JP-A-1-125866 and JP-A-5-235353, the activation process temperature is 1000 ° C., which makes it impossible to use an inexpensive low-temperature glass substrate. As a low temperature activation method, for example, Japanese Patent Application Laid-Open No. 5-152326 uses a laser annealing method, but the laser annealing method is more expensive than the heat treatment method. In addition, since the laser annealing method generates excessive thermal shock, there is a problem that the reliability of the gate electrode is lowered due to peeling or cracking of the film.
[0013]
The present invention has been made in view of such problems, and can improve the reliability of the gate electrode, reduce the resistance, further reduce the leakage current, and increase the throughput of the thin film transistor manufacturing process. It is another object of the present invention to provide a method for manufacturing a top gate type thin film transistor that can simultaneously satisfy the reduction in cost.
[0014]
[Means for Solving the Problems]
The thin film transistor manufacturing method according to the present invention includes a step of forming a polysilicon thin film on an insulating substrate, a step of forming a gate insulating film on the polysilicon thin film, and a lower gate electrode on the gate insulating film. A step of forming a microcrystalline silicon thin film at a temperature of 350 ° C. or less by plasma CVD, and a metal thin film serving as an upper gate electrode is sputtered on the microcrystalline silicon thin film. A step of selectively forming a photoresist on the metal thin film, and a step of selectively etching the upper metal thin film and the lower microcrystalline silicon thin film using the photoresist as a mask by dry etching under the same mask. Continuous etching to form a two-layer gate electrode And the extent,The metal thin filmAnd a step of side-etching only the side surface of the substrate, and a step of introducing an impurity into the polysilicon thin film through the gate insulating film, wherein the impurity is introduced through the gate insulating film. And simultaneously forming a low concentration impurity introduction region into which impurities are introduced through the gate insulating film and the lower gate electrode, and the structure of the polysilicon thin film in the low concentration impurity introduction region and the high concentration impurity introduction region, The upper part is amorphized and the polysilicon layer remains in the lower part.
[0015]
thisIn the method of manufacturing a thin film transistor,The concentration of the impurity on the substrate-side surface of the polysilicon thin film is 3 × 10¹⁹cm^-3 Less thanImpurities are introduced so that
[0016]
Also,The impurity concentration in the polysilicon film can be high above the film and low below the film.AndThe impurity can be introduced after forming an insulating film above the polysilicon thin film. Further, the impurity introduction method is, for example, an ion doping method.
[0017]
In the present invention, by applying the microcrystalline silicon thin film to the lower layer of the two-layered gate electrode, a low-resistance gate wiring having high reliability and low cost is formed. The microcrystalline silicon thin film is disclosed in Journal of Non-Crystaline Solids, Volumes 59 & 60, p. 767 (J. Non-Cryst. Solids, Vol. 59 & 60, p. 767.). A silicon thin film formed by a plasma CVD method, which is a silicon thin film in which extremely fine crystal grains having a particle size of 10 nm or less and amorphous are mixed. Since the deposition temperature of the microcrystal silicon thin film is about 300 ° C., the deposition temperature of the low pressure CVD method and the atmospheric pressure CVD method used for the conventional polysilicon thin film deposition is about 600 ° C. Compared to the above, the throughput and manufacturing cost of the film formation process are extremely excellent. In addition, since the microcrystalline silicon thin film has fine crystal grains, the resistance can be reduced to the same level as the polysilicon thin film. Therefore, by using a microcrystalline silicon thin film as a lower layer and a metal thin film as an upper layer as a TFT gate electrode, a low-resistance gate wiring having high reliability can be formed at low cost.
[0018]
Further, in the present invention, an overlap LDD structure that can be activated at a low temperature in one impurity introduction step through the gate insulating film by side-etching only the upper metal gate electrode when forming the two-layer gate electrode. Is formed.
[0019]
At the portion where the lower gate electrode is exposed, impurities are introduced into the polysilicon thin film through the lower gate electrode and the gate insulating film. On the other hand, in the portion where the gate electrode does not exist, impurities are introduced into the polysilicon thin film only through the gate insulating film. Therefore, the region immediately below the portion where the lower gate electrode of the polysilicon thin film is exposed becomes an LDD region where the amount of introduced impurities is smaller than the region immediately below the portion where the gate electrode does not exist. It should be noted that no impurity is introduced into the region immediately below the portion where the upper gate insulating film of the polysilicon thin film exists because of the shielding effect of the upper gate electrode.
[0020]
The activation temperature after the introduction of impurities depends on the structural change of the polysilicon thin film accompanying the introduction of impurities. When the impurities are introduced, the polysilicon thin film is changed into an amorphous phase because the atomic structure is disturbed. Activation after the introduction of impurities means that the amorphous phase containing the impurities is crystallized again. Here, when the polysilicon thin film is amorphized in all regions in the film thickness direction from the insulating film interface to the substrate interface, a heat treatment temperature of 600 ° C. or higher, preferably about 1000 ° C. is required for crystallization. In order for the amorphous phase to crystallize, both nucleation and grain growth processes must be performed, but nucleation requires a latency time that depends on the heat treatment temperature. In the case of silicon, a temperature of 1000 ° C. is necessary to cause nucleation in a time range of about several hours suitable for the manufacturing process. Further, when the heat treatment temperature is lowered to 600 ° C., the time required for nucleation increases to 20 hours, and the throughput increases remarkably.
[0021]
However, when only the surface of the polysilicon film becomes amorphous after the introduction of impurities and polysilicon remains in the vicinity of the substrate interface, activation can be achieved by heat treatment at a low temperature of about 500 ° C. for several hours. This is because crystallization progresses only in the grain growth process because crystal nuclei already exist. In the present invention, by introducing the impurity through the insulating film, the impurity concentration profile in the film thickness direction of the polysilicon film can be controlled, and it can be easily controlled so that the polysilicon remains after the impurity is introduced. Therefore, low-temperature activation to the extent that an inexpensive low-temperature glass substrate can be used is possible, and throughput is increased.
[0022]
As described above, according to the present invention, only the upper metal gate electrode is side-etched when forming the two-layer gate electrode, thereby enabling low-temperature activation in one impurity introduction step through the gate insulating film. An overlap LDD-TFT having a low resistance and high reliability gate electrode is formed.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing a top gate type thin film transistor manufactured by the method of the first embodiment of the present invention. This transistor can be manufactured as follows. First, the base insulating film 2 is deposited on the insulating substrate 1. Next, a silicon thin film is deposited on the entire surface, a polysilicon thin film 3 is formed by a laser annealing method using CW laser light or pulsed laser light, patterned into an island shape, and then a gate insulating film 4 is deposited thereon. To do. Next, after depositing a microcrystalline silicon thin film 5 as a lower gate electrode at a temperature of 350 ° C. or less by a plasma CVD method so that the film thickness becomes 70 nm or more, a metal thin film 6 is continuously deposited as an upper gate electrode. Patterning is performed to form a two-layer gate electrode.
[0024]
Impurities are activated by selectively introducing impurities into the polysilicon thin film 3 through the gate insulating film 4 by an ion doping method or the like to form the source / drain regions 7 and performing a heat treatment at 500 ° C., for example. Subsequently, an interlayer insulating film 9 is deposited, and contact holes that expose the source / drain regions 7 are opened. Finally, a metal thin film such as aluminum is formed and patterned to form a metal wiring 10 in contact with the source / drain region 7 to complete the thin film transistor formation process.
[0025]
In this way, a channel region composed of the polysilicon thin film 3, source / drain regions 7 on both sides thereof, and a gate electrode having a two-layer structure laminated with the gate insulating film 4 between these regions are formed. A top-gate thin film transistor having the same is obtained. The two-layer gate electrode is composed of a lower microcrystalline silicon thin film 5 and an upper metal thin film 6. Since the microcrystalline silicon thin film 5 has a low film formation temperature, the throughput of the film formation process is better than the conventional polysilicon thin film, and the manufacturing cost is reduced. Further, since the microcrystalline silicon thin film 5 has fine crystal grains, the resistance can be reduced to the same level as that of the polysilicon thin film. Therefore, a highly reliable low resistance gate wiring can be formed at low cost.
[0026]
Next, the method of the second embodiment of the present invention will be described with reference to FIG. In this embodiment, the manufacturing process is the same as that of the first embodiment until the deposition process of the microcrystal silicon thin film 5 and the metal thin film 6. In this embodiment, when the two-layer gate electrode is formed by patterning, the gate electrode is side-etched by over-etching both layers. Then, with the resist held on the gate electrode, an impurity is selectively introduced into the polysilicon thin film 3 through the gate insulating film 4 by ion doping or the like, thereby forming the source / drain regions 7.
[0027]
Next, after removing the resist, a low concentration impurity is introduced to form an LDD region (low concentration region) 8. Thereafter, the steps after impurity activation are the same as those in the first embodiment, and the thin film transistor is completed by these steps.
[0028]
In this embodiment, in addition to the same effects as in the first embodiment, the source / drain region has an LDD region (low concentration region) 8, thereby obtaining a thin film transistor having an LDD structure.
[0029]
FIG. 3 is a cross-sectional view showing a top gate type thin film transistor manufactured by the method of the third embodiment of the present invention. The steps up to the deposition of the microcrystalline silicon thin film 5 and the metal thin film 6 are the same as in the first embodiment. In this embodiment, when the two-layer gate electrode is formed by patterning, the upper-layer metal thin film 6 and the lower-layer microcrystal silicon thin film 5 have different widths by over-etching only the metal thin film 6. Is formed.
[0030]
Then, after removing the resist on the gate electrode, the gate insulating film 4 is inserted by ion doping or the like, and when impurities are selectively introduced into the polysilicon thin film 3, it passes through the microcrystal silicon thin film 5 of the lower gate electrode. As a result, the concentration is reduced to form a low concentration LDD region 8, and the one that has passed through the region outside the lower microcrystal silicon thin film 5 forms a high concentration source / drain region 7. In this way, in this embodiment, the source / drain region 7 and the LDD region 8 can be formed simultaneously. The steps after impurity activation are the same as those in the first embodiment, and the thin film transistor forming step is completed. In this embodiment, in addition to the same effects as those of the first and second embodiments, low temperature activation can be performed by a single impurity introduction step through the gate insulating film 4 and the lower microcrystal silicon thin film 5. An overlapping LDD structure can be formed.
[0031]
【Example】
Next, a result of actually manufacturing a top gate type thin film transistor by the method of this embodiment and evaluating its characteristics will be described. First, the result of manufacturing the thin film transistor having the structure of the first embodiment will be described. An OA-2 substrate manufactured by Nippon Electric Glass Co., Ltd. was used as the low temperature glass substrate. SiH by plasma CVD method₄And N₂A silicon dioxide thin film as a base insulating film was deposited to a thickness of 100 nm using O as a source gas.
[0032]
Next, Si is formed by a low pressure CVD method.₂H₆As a source gas, an amorphous silicon thin film was deposited to 75 nm. The deposition conditions are Si₂H₆The deposition was performed for 70 minutes under the conditions of a flow rate of 150 sccm, a pressure of 8 Pa, and a substrate temperature of 450 ° C. A polysilicon thin film was formed by using a laser annealing method of irradiating the amorphous silicon thin film with XeCl excimer laser light having a wavelength of 308 nm. As laser irradiation conditions, an energy density of 420 mJ / cm²The beam was scanned and irradiated under the condition of a beam overlap rate of 90%. The polysilicon thin film was formed into an island by dry etching after patterning by a normal photoresist process.
[0033]
Next, SiH is formed on the island-formed polysilicon thin film by a low pressure CVD method.₄And O₂A silicon dioxide thin film serving as a gate insulating film was deposited to a thickness of 40 nm using as a source gas. The deposition condition is SiH₄The flow rate of 35 sccm, O₂Deposition was performed for 20 minutes under conditions of a flow rate of 140 sccm, a pressure of 30 Pa, and a substrate temperature of 400 ° C.
[0034]
Next, SiH is formed by plasma CVD.₄And PH₃(H₂Dilution 0.5%) and H₂Was used as a source gas, and a microcrystalline silicon thin film serving as a lower gate electrode was deposited to a thickness of 70 nm. As deposition conditions, SiH₄Flow rate 20sccm, PH₃Flow rate 40sccm, H₂Flow rate 1000sccm, pressure 50Pa, discharge power density 0.13W / cm²The film was deposited for 19 minutes at a substrate temperature of 350 ° C.
[0035]
The resistivity of the microcrystal silicon thin film greatly depends on the film thickness as shown in FIG. This is because the crystal component in the microcrystal silicon grows as the film thickness increases. That is, in the lower microcrystalline silicon thin film, the growth of crystal components progresses from the bottom to the top. As the crystal component grows, the resistivity decreases. In consideration of application to the lower gate electrode, the resistivity of the film is desirably 1 Ωcm or less. Therefore, the thickness of the microcrystal silicon thin film needs to be 70 nm or more. In addition, since the growth of crystal components is promoted when the substrate temperature is high, it is desirable that the substrate temperature be high. However, an excessive temperature causes a decrease in throughput and an increase in apparatus cost and process cost. Therefore, the substrate temperature is suitably up to about 350 ° C. that can be realized by a normal plasma CVD apparatus.
[0036]
Next, a tungsten silicide thin film serving as an upper gate electrode was deposited to a thickness of 100 nm by sputtering. Ar is used as the sputtering gas, and the deposition conditions are Ar flow rate 100 sccm, pressure 0.3 Pa, 2 W / cm.²The substrate was deposited for 0.3 minutes at a substrate temperature of 150 ° C. At this time, the resistivity of the film is 5 × 10^-5The value was Ωcm.
[0037]
The microcrystalline silicon thin film and the tungsten silicide thin film were successively deposited using different chambers in the same vacuum apparatus in order to suppress the generation of a natural oxide film on the surface of the microcrystalline silicon thin film. When each thin film was formed with a different vacuum apparatus, a natural oxide film was generated on the surface of the microcrystal silicon thin film, and the resistivity of the entire two-layer gate electrode was increased. As a result, the TFT characteristics were reduced by about 4%.
[0038]
Next, the gate electrode was patterned by a normal photoresist method. Next, CF by dry etching₄And O₂Thus, the tungsten silicide thin film was dry etched. Etching conditions include CF₄Flow rate 40sccm, O₂Flow rate 10sccm, pressure 6Pa, discharge power density 0.3W / cm²Etching was performed for 1.5 minutes under the following conditions. After completion of the etching of the tungsten silicide thin film, the etching chamber is temporarily set to 10^-4Vacuum is pulled to Pa, followed by Cl₂And SF₆And H₂Then, dry etching of the microcrystal silicon thin film was performed. Etching conditions include Cl₂Flow rate 40sccm, SF₆Flow rate 10sccm, H₂Flow rate 10sccm, pressure 10Pa, discharge power density 0.35W / cm²Etching was performed for 6 minutes under the following conditions.
[0039]
The etching gas for the tungsten silicide thin film can provide a high etching rate.₄And O₂It was used. The dry etching gas for the microcrystalline silicon thin film is required to have a high selectivity between the microcrystalline silicon thin film and the silicon dioxide thin film.₂And SF₆And H₂By using this, the ability to remove residual tungsten silicon was excellent, and a high selectivity of 20 or more was obtained between the microcrystal silicon thin film and the silicon dioxide thin film. Further, it is advantageous in terms of throughput to dry-etch the tungsten silicide thin film and the microcrystal silicon thin film in the same vacuum apparatus.
[0040]
After removing the resist on the gate electrode, PH₃(H₂(5% dilution), self-aligned impurities were introduced using the gate electrode as a mask. The doping conditions are an acceleration voltage of 50 keV and a dose amount of 3 × 10.¹⁵cm^-2The pressure was 0.02 Pa.
[0041]
FIG. 5 shows a P concentration profile in silicon obtained as a result of doping. The P concentration that causes amorphization of the silicon thin film is 3 × 10¹⁹cm^-3This is the result of the experiment. Therefore, when doping a 75 nm polysilicon thin film through a 40 nm insulating film, polysilicon remains for about half of the film thickness, and the impurity activation temperature may be low. In fact, activation was achieved under conditions of a heat treatment temperature of 500 ° C. and a heat treatment time of 2 hours. The resistivity of the impurity introduction part at this time is 2 × 10^-3It was Ωcm. Moreover, although 2 ppm distortion was recognized in the board | substrate after an activation process, there was no trouble in the subsequent TFT manufacturing process.
[0042]
On the other hand, when the doping is performed directly without going through the insulating film, the polysilicon thin film becomes amorphous over almost the entire film thickness. At this time, activation was not achieved at a heat treatment temperature of 500 ° C. even at a heat treatment time of 50 hours, and activation was first achieved at a heat treatment temperature of 600 ° C. and a heat treatment time of 20 hours. Further, distortion of as much as 40 ppm occurred in the substrate after the activation process, and there was a problem in the subsequent TFT manufacturing process, particularly in the reticle alignment in the photoresist process and the substrate transport in the film forming process. As a result, throughput and yield decreased.
[0043]
Next, SiH is performed by plasma CVD.₄And NH₃And N₂Thus, a silicon nitride film was deposited to 300 nm. After opening the contact hole by dry etching, an aluminum film was deposited to 400 nm by sputtering and patterned to form a metal wiring. Finally, hydrogen annealing was performed to complete the TFT.
[0044]
The TFT thus completed has a lower process temperature than a conventional TFT, is manufactured with high throughput and low cost, and the gate electrode has high reliability.
[0045]
Next, the result of manufacturing a thin film transistor by the method of the second embodiment of the present invention will be described. As a low-temperature glass substrate, a 1737 substrate manufactured by Corning was used. Next, SiH is performed by plasma CVD.₄And N₂A silicon dioxide thin film as a base insulating film was deposited to 100 nm by O.
[0046]
Next, SiH is performed by plasma CVD.₄And H₂Was used to deposit an amorphous silicon thin film at 75 nm. As deposition conditions, SiH₄Flow rate 150sccm, H₂Flow rate 400sccm, pressure 100Pa, discharge power 0.1W / cm²The deposition was performed for 8 minutes under the condition of the substrate temperature of 320 ° C. This amorphous silicon thin film was subjected to dehydrogenation annealing at a heat treatment temperature of 400 ° C. for a heat treatment time of 2 hours, and then a polysilicon thin film was formed by a laser annealing method of irradiating KrF excimer laser light having a wavelength of 248 nm. As laser irradiation conditions, an energy density of 380 mJ / cm²The beam was scanned and irradiated under the condition of a beam overlap rate of 90%. The polysilicon thin film was formed into an island by dry etching after patterning by a normal photoresist process.
[0047]
Next, SiH is formed on the islanded polysilicon film by ECR-plasma CVD.₄And O₂Thus, a silicon dioxide thin film to be a gate insulating film was deposited to 40 nm. As deposition conditions, SiH₄Flow rate 10sccm, O₂Flow rate 200sccm, pressure 100Pa, discharge power density 0.23W / cm²The deposition was performed for 4 minutes under the condition of the substrate temperature of 270 ° C.
[0048]
Next, SiH is performed by plasma CVD.₄And PH₃(H₂Dilution 0.5%) and H₂Was used as a source gas, and a microcrystalline silicon thin film serving as a lower gate electrode was deposited to a thickness of 70 nm. As deposition conditions, SiH₄Flow rate 10sccm, PH₃Flow rate 40sccm, H₂Flow rate 1000sccm, pressure 100Pa, discharge power density 0.5W / cm²The substrate was deposited for 23 minutes at a substrate temperature of 300 ° C. Subsequently, a tungsten silicide thin film serving as an upper gate electrode was deposited to a thickness of 100 nm by sputtering as in the first embodiment.
[0049]
As in the first embodiment, the gate electrode is formed by patterning and dry etching, but at this time, the etching time is increased from the normal condition to produce a 1 μm side-etched region. The etching time was 2 minutes and 9 minutes for the upper layer and the lower layer, respectively.
[0050]
Next, impurities were introduced by ion doping in the same manner as in the first example while holding the resist on the gate electrode. Next, the resist on the gate electrode is removed, and PH is obtained by ion doping.₃(H₂Dilution 0.1%) and H₂As a source gas, a low concentration impurity was introduced into the side etch region to form an LDD region. The doping conditions are an acceleration voltage of 40 keV and a dose amount of 7 × 10.¹²cm^-2The pressure was 0.02 Pa. By having the LDD region, the resulting TFT leakage current was reduced to about 1/50.
[0051]
After the activation process, the LDD-TFT is completed by the same process as in the first embodiment. The completed LDD-TFT has a lower process temperature than a conventional LDD-TFT, is manufactured with high throughput and low cost, and the reliability of the gate electrode is high.
[0052]
Next, the result of manufacturing a thin film transistor by the method of the third embodiment of the present invention will be described. In the same manner as in the first example, a polysilicon thin film was formed on a glass substrate to form an island, and a gate insulating film, a microcrystal silicon thin film, and a tungsten silicide thin film were deposited.
[0053]
In the same manner as in the first example, the gate electrode was formed by patterning and dry etching, and the etching time at this time was 2 minutes for the upper layer and 6 minutes for the lower layer. As a result, the upper layer was narrower by 1 μm on the left and right than the lower layer.
[0054]
Next, as in the first example, impurities were introduced by ion doping. In the portion where the gate electrode does not exist, impurities are introduced into the polysilicon thin film only through the gate insulating film, and the dose amount is 3 × 10 4 as in the first embodiment.¹⁵cm^-2Met. On the other hand, in the polysilicon region that is directly below the portion where the upper gate electrode is side-etched and the lower gate electrode is exposed, the dose is 2 × 10¹²cm^-2Met.
[0055]
As shown in FIG. 5, the P concentration decreased by about three orders of magnitude due to the influence of the lower gate electrode having a film thickness of 70 nm. By having the LDD region, the resulting TFT leakage current was reduced to about 1/20.
[0056]
After the activation process, the process is the same as that of the first example, thereby completing the LDD-TFT. The completed LDD-TFT has a process temperature lower than that of the conventional LDD-TFT, the number of impurity introductions is less, it is manufactured with high throughput and low cost, and the reliability of the gate electrode is high.
[0057]
Needless to say, the present invention is not limited to the above embodiments. For example, in the above embodiment, amorphous silicon is used as an initial material for laser annealing, but the same effect can be obtained by using another silicon film such as polysilicon or microcrystal silicon as the initial material. It was. Further, the same effect can be obtained by using other insulating films such as a silicon nitride film and a silicon oxynitride film instead of the silicon oxide film as the gate insulating film. The same effect was obtained when other metal such as aluminum, chromium, molybdenum, molybdenum silicide or tungsten molybdenum alloy was used as the upper gate electrode instead of tungsten silicide.
[0058]
【The invention's effect】
As described above, according to the method for manufacturing a top gate type thin film transistor according to the present invention, by using a two-layer gate electrode composed of a microcrystalline silicon thin film and a metal thin film as a gate electrode, low resistance and high reliability are achieved. TFT having a conductive gate electrode can be manufactured with high throughput and low cost. Further, by side-etching only the upper gate electrode, an LDD-TFT having a gate electrode with low resistance and high reliability can be manufactured at low cost.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the structure of a thin film transistor manufactured by a first embodiment method of the present invention.
FIG. 2 is a cross-sectional view showing the structure of a thin film transistor manufactured by a second embodiment method of the present invention.
FIG. 3 is a cross-sectional view showing the structure of a thin film transistor manufactured by a third embodiment method of the present invention.
FIG. 4 is a graph showing the relationship between the film thickness and resistivity of a microcrystalline silicon thin film.
FIG. 5 is a graph showing a P concentration profile in silicon.
FIG. 6 is a cross-sectional view showing the structure of a conventional thin film transistor.
FIG. 7 is a cross-sectional view showing the structure of a conventional LDD thin film transistor.
FIG. 8 is a cross-sectional view showing another conventional LDD-TFT structure.
[Explanation of symbols]
1: Low temperature glass substrate
2: Underlying oxide film
3: Polysilicon thin film
4: Gate insulating film
5: Microcrystal silicon gate electrode
6: Metal gate electrode
7: Source / drain region
8: LDD region
9: Interlayer insulation film
10: Metal wiring
11: Polysilicon gate electrode

Claims (5)

A step of forming a polysilicon thin film on an insulating substrate, a step of forming a gate insulating film on the polysilicon thin film, and a crystal component in the film as a lower gate electrode on the gate insulating film from bottom to top A step of forming a microcrystalline silicon thin film, which is growing at a temperature of 350 ° C. or less by a plasma CVD method, a step of forming a metal thin film serving as an upper gate electrode on the microcrystalline silicon thin film by a sputtering method, and the metal thin film A step of selectively forming a photoresist on the upper surface, and dry etching, the upper metal thin film and the lower microcrystalline silicon thin film are continuously etched using the same mask as a mask to form a two-layer structure. forming a gate electrode, only the side surface of the metal thin film Saidoe' And a step of introducing an impurity into the polysilicon thin film through the gate insulating film, and a high concentration impurity introduction region into which the impurity is introduced through the gate insulating film, and the gate insulation A low-concentration impurity introduction region into which impurities are introduced is formed simultaneously through the film and the lower gate electrode, and the structure of the polysilicon thin film in the low-concentration impurity introduction region and the high-concentration impurity introduction region is amorphous in the upper part A method of manufacturing a thin film transistor, wherein a polysilicon layer remains in a lower portion. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the impurity is introduced so that a concentration of the impurity on a substrate-side surface of the polysilicon thin film is less than 3 × 10 ¹⁹ cm ⁻³ . 3. The method of manufacturing a thin film transistor according to claim 1, wherein the concentration of the impurity in the polysilicon film is high above the film and low below the film. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the impurity is introduced after forming an insulating film on the polysilicon thin film. 5. The method of manufacturing a thin film transistor according to claim 1, wherein the impurity introduction method is an ion doping method.

Images