KR100254924B1 - Method of fabricating image display device - Google Patents
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- KR100254924B1 KR100254924B1 KR1019920018902A KR920018902A KR100254924B1 KR 100254924 B1 KR100254924 B1 KR 100254924B1 KR 1019920018902 A KR1019920018902 A KR 1019920018902A KR 920018902 A KR920018902 A KR 920018902A KR 100254924 B1 KR100254924 B1 KR 100254924B1
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- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
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Abstract
Description
제1(a)도 내지 제1(e)도는 종래 화상표시장치의 제조 공정을 보인 단면도.1 (a) to 1 (e) are sectional views showing the manufacturing process of a conventional image display apparatus.
제2(a)도 내지 제2(e)도는 본 발명의 화상표시장치의 제조 공정을 보인 단면도.2 (a) to 2 (e) are sectional views showing the manufacturing process of the image display device of the present invention.
제3도는 본 발명 다른 실시예의 화상표시장치 단면도.3 is a cross-sectional view of an image display device according to another embodiment of the present invention.
제4도는 본 발명의 화상표시장치를 포함하는 액정표시 화소평면도.4 is a liquid crystal display pixel plane view including the image display device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 절연기판 2 : 활성층1 Insulation substrate 2 Active layer
3 : 게이트절연막 3′: 층간절연막3: gate insulating film 3 ': interlayer insulating film
4 : 게이트전극 5 : 소스/드레인 영역4 gate electrode 5 source / drain region
6 : 소스/드레인 전극 7 : 보호막6: source / drain electrode 7: protective film
8 : 저농도 불순물 도핑층8: low concentration impurity doping layer
본 발명은 액정표시소자용 화상표시장치의 제조방법에 관한 것으로, 특히 소스/드레인 영역형성시 이온 주입 공정에 의한 불순물 주입 공정을 제외하고 불순물로 도핑된 폴리 실리콘층으로 형성하여 화상표시장치의 시트저항(Sheet Registance)과 접촉저항(Contact Registance)을 감소시켜 소자의 특성을 개선하고 이온주입 공정을 제외하여 공정의 단순화에 적당하도록한 화상표시장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an image display device for a liquid crystal display device. In particular, a sheet of an image display device is formed by forming a polysilicon layer doped with impurities except for an impurity implantation process by an ion implantation process when forming a source / drain region. The present invention relates to a method of manufacturing an image display device which reduces the resistance (Sheet Registance) and contact resistance (Contact Registance) to improve the characteristics of the device and is suitable for the simplification of the process excluding the ion implantation process.
제1(a)도 내지 제1(e)도는 종래 화상표시장치의 제조 공정을 보인 단면도로서 이를 참조하여 종래 화상표시장치의 제조공정과 문제점을 설명하면 다음과 같다.1 (a) to 1 (e) are cross-sectional views illustrating a manufacturing process of a conventional image display apparatus, and the manufacturing process and problems of the conventional image display apparatus will be described with reference to the following.
기판준비 공정을 통해 청결하고 잘건조된 석영, 유리등의 절연기판(1)위에 화학기상증착법(Chemical Vapor Deposition: CVD)에 의해 비정질 실리콘을 일정두께로 증착한 다음 재결정화 방법을 사용하여 다결정 실리콘으로 만든 후, 사진 식각공정(Photo etching)을 통해 선택적 식각하여 패턴구조의 활성층(2)을 형성하여 제1(a)도와 동일하게 제조한 다음 그 활성층(2)위와 상기 식각공정을 통해 노출된 절연기판(1)위에 게이트 절연막(3)을 형성한후 그 게이트 절연막(3)위에 불순물이 도핑된 다결정 실리콘이나 메탈 실리사이드(silicide) 등을 상기와 동일한 화학 기상 증착법으로 증착한 후 자외선(UV)과 마스크(mask)를 이용한 사진식각 공정을 통한 선택적 식각으로 패턴형성한 게이트 전극(4)을 형성한 다음 그 게이트 전극(4)을 마스크로 이용한 이온주입공정(Implantation)을 통해 상기 활성층(2)일부에 불순물을 도핑시켜 소스/드레인 영역(5)을 형성하여 제1(b)도와 동일한 구조를 제조한 다음 상기 게이트 전극(4)위에 층간절연막(3′)을 적층한후 사진식각 공정을 통한 선택적 식각으로 상기 소스/드레인영역(5) 상부의 층간절연막(3′)과 게이트 절연막(3)을 식각하여 그 소스/드레인영역(5)을 노출시켜 제1(c)도와 동일한 구조로 제조한다.After depositing amorphous silicon to a certain thickness by chemical vapor deposition (CVD) on an insulating substrate (1) of clean, well-dried quartz, glass, etc., through the substrate preparation process, polycrystalline silicon After etching, the active layer 2 of the pattern structure is formed by selective etching through photo etching to prepare the same as the first (a), and then exposed on the active layer 2 and the etching process. After the gate insulating film 3 is formed on the insulating substrate 1, polycrystalline silicon or metal silicide doped with impurities is deposited on the gate insulating film 3 by the same chemical vapor deposition method as described above. And patterned gate electrode 4 is formed by selective etching through a photolithography process using a mask and then an ion implantation process using the gate electrode 4 as a mask is performed. The source / drain region 5 is formed by doping an impurity in a portion of the active layer 2 to form the same structure as in FIG. 1 (b), and then an interlayer insulating film 3 'is stacked on the gate electrode 4. Afterwards, the interlayer insulating film 3 ′ and the gate insulating film 3 on the source / drain region 5 are etched by selective etching through a photolithography process to expose the source / drain region 5 to expose the first / c region. Manufactured in the same structure as tiles.
이후 상기의 과정을 통해 노출된 소스/드레인영역(5)위에 알루미늄(Al), 크롬(Cr), 텅스텐(W)등의 금속을 증착한후 상기와 동일한 사진식각공정을 통해 선택적 식각으로 패턴을 형성하여 소스/드레인전극(6)을 제1(d)도와 동일하게 제조한 다음 표면전면에 산화 실리콘막(SiO2) 또는 질화실리콘(SiOx)의 절연막으로 보호막(7)을 형성하여 제1(e)도와 동일하게 절연기판(1)위에 소스/드레인영역(5)이 양측에 형성된 활성층(2)이 형성되고, 그 활성층(2)위에 게이트 절연막(3)이 형성되며 그 게이트 절연막(3)위에 게이트 전극(4)과 층간절연막(3′)이 형성되고, 상기 소스/드레인영역(5)위에 소스/드레인 전극(6)이 형성되며 그 소스/드레인 전극(6)위와 노출된 각 부위에 보호막(7)이 구비된 구조로 제조된다.Thereafter, a metal such as aluminum (Al), chromium (Cr), tungsten (W), etc. is deposited on the exposed source / drain region 5 through the above process, and then the pattern is selectively etched through the same photolithography process as described above. The source / drain electrodes 6 are formed in the same manner as the first (d), and then the protective film 7 is formed on the front surface of the silicon oxide film (SiO 2 ) or the silicon nitride (SiOx). In the same manner as in e), an active layer 2 having source / drain regions 5 formed on both sides of the insulating substrate 1 is formed, a gate insulating film 3 is formed on the active layer 2, and the gate insulating film 3 is formed. A gate electrode 4 and an interlayer insulating film 3 'are formed thereon, a source / drain electrode 6 is formed on the source / drain region 5, and the source / drain electrode 6 is formed on each of the exposed portions. It is manufactured in the structure provided with the protective film 7.
상기의 과정을 통해 제조된 종래 화상표시장치는 게이트 전극패턴후 소스/드레인 영역활성을 위해 이온주입 공정을 통해 불순물을 주입하므로 별도의 주입공정이 필요하여 공정이 복잡하고 이온주입 공정시 정확한 불순물량제어가 어려우며 접촉저항과 시트 저항이 증가하여 소자의 성능을 저하시키는 문제점과 아울러 데이터신호선이 단층구조의 금속이므로 단선이 일어날 확률이 많은 문제점이 있었다.The conventional image display device manufactured through the above process injects impurities through the ion implantation process for source / drain region activation after the gate electrode pattern, so a separate implantation process is required, and the process is complicated and the amount of impurities is correct during the ion implantation process. Difficult to control and increase the contact resistance and the sheet resistance, thereby lowering the performance of the device, as well as the problem that the disconnection is likely to occur because the data signal line is a metal of a single layer structure.
본 발명은 상기와 같은 종래의 문제점을 감안하여 소스/드레인 형성시 이온주입 공정을 제거하기 위해 접촉홀 형성이후 불순물이 도핑된 반도체층을 형성하고 소스/드레인금속을 증착하여 시트저항 및 접촉저항을 감소시켜 소자의 특성을 개선하고 데이터신호선을 불순물이 도핑된 다결정실리콘과 전도성금속의 2층구조로 형성하여 데이터신호선의 단선을 방지할 수 있으며, 이온주입 공정제거로 공정의 단순화를 이루고자 한다.In view of the above-mentioned problems, the present invention forms a semiconductor layer doped with impurities after the formation of contact holes and removes source / drain metals to form ion resistance and contact resistance in order to remove ion implantation processes during source / drain formation. By reducing the characteristics of the device and improving the data signal line to form a two-layer structure of polycrystalline silicon and conductive metal doped with impurities, it is possible to prevent the disconnection of the data signal line, and to simplify the process by removing the ion implantation process.
제2(a)도 내지 제2(e)도는 본 발명의 박막트랜지스터 제조공정을 보인 단면도로서, 이와 본 발명의 화상표시장치를 포함하는 액정표시소자 화소 평면도인 제5도를 참조하여 화상표시장치의 제조공정과 작용 효과를 상세히 설명하면 다음과 같다.2 (a) to 2 (e) are cross-sectional views showing the manufacturing process of the thin film transistor of the present invention, with reference to FIG. 5 which is a plan view of the pixel of the liquid crystal display device including the image display device of the present invention. Referring to the manufacturing process and the effect of the operation in detail as follows.
기판준비 공정을 통해 잘건조된 유리, 석영등의 절연기판(1)위에 폴리실리콘(Poly-Si)을 화학기상증착법(Chemical Vapor Deposition: CVD)과 재결정화방법을 이용하여 일정두께로 증착한후 포토레지스트(Photo Resist)를 도포한 마스크(Mask)를 통해 자외선(UV)을 투사시키는 사진식각공정(Photo Etching)을 사용하여 패턴의 활성층(2)을 제2(a)도와 동일하게 제조한후 그 활성층(2)과 선택적식각 공정에 의해 노출된 절연기판(1)일부에 게이트 절연막(3)을 형성하고 그 게이트 절연막(3)위에 불순물이 도핑된 다결정실리콘이나 메탈실리사이드 등을 상기와 동일한 화학기상증착법을 통해 증착후 선택적식각으로 패턴구조의 게이트 전극(4)을 형성하여 제2(b)도와 동일한 구조로 제조한다.After depositing polysilicon (Poly-Si) on a well-dried glass, quartz, etc. insulating substrate (1) by chemical vapor deposition (CVD) and recrystallization, After manufacturing the active layer 2 of the pattern in the same manner as in the second (a) using a photo etching process of projecting ultraviolet (UV) light through a mask coated with a photo resist The gate insulating film 3 is formed on a portion of the insulating substrate 1 exposed by the active layer 2 and the selective etching process, and polycrystalline silicon, metal silicide, etc. doped with impurities on the gate insulating film 3 are subjected to the same chemistry as described above. After vapor deposition, a gate electrode 4 having a pattern structure is formed by selective etching after deposition, thereby fabricating a structure having the same structure as that of FIG. 2 (b).
이후 상기의 과정을 통해 형성된 게이트 전극(4)위에 층간절연막(3′)을 형성한다음 상기의 사진식각공정과 동일한 방법으로 층간절연막(3′)과 게이트 절연막(3)을 선택적식각으로 상기 활성층(2)경계까지 식각하여 상기 게이트 전극(4)이 존재하지 않은 부분의 활성층(2)을 노출시켜 제2(c)도와 같이 콘택홀(Contact hole)을 형성한 후 불순물로 도핑된 폴리실리콘을 상기의 과정으로 노출된 활성층(2)위에 증착하여 소스/드레인영역(5)을 형성한 다음 열처리공정을 통해 열처리한후 알루미늄(Al), 크롬(Cr), 몰리브덴(Mo), 탄탄(Ta) 및 텅스텐(W)등의 금속을 연속증착한 후 사진식각공정을 통해 선택적식각하여 제2(d)도와 동일하게 소스/드레인전극(6)을 형성한다.Thereafter, the interlayer insulating film 3 'is formed on the gate electrode 4 formed through the above process, and then the interlayer insulating film 3' and the gate insulating film 3 are selectively etched in the same manner as the photolithography process. (2) by etching to the boundary to expose the active layer (2) where the gate electrode (4) does not exist to form a contact hole (2) as shown in (c) and then doped with polysilicon doped with impurities The source / drain region 5 is formed by depositing on the active layer 2 exposed by the above process, and then heat-treated by heat treatment, followed by aluminum (Al), chromium (Cr), molybdenum (Mo), and tantan (Ta). And continuously depositing a metal such as tungsten (W), and selectively etching through a photolithography process to form a source / drain electrode 6 as shown in FIG.
이후 상기 과정으로 형성된 화상표시장치를 보호하기 위해 산화실리콘(SiO2), 질화실리콘(SiNx)등의 절연막을 상기 소스/드레인전극(6)과 표면으로 노출된 각부분에 제2(e)도와 동일하게 보호막(7)을 형성하여 화상표시장치의 제조를 완료하여 액정표시소자에 이용하여 제4도와 동일한 액정표시소자 화소평면도를 갖는다.Afterwards, an insulating film such as silicon oxide (SiO 2 ) or silicon nitride (SiNx) may be formed on the portions exposed to the source / drain electrode 6 and the surface to protect the image display device formed by the process. Similarly, the protective film 7 is formed to complete the manufacture of the image display device and used in the liquid crystal display device to have the same liquid crystal display device pixel plan view as in FIG.
한편 본 발명의 다른 실시예로 제3도에 도시한 바와같이 게이트 전극(4)을 게이트절연막(3)위에 형성한 후 그 게이트 전극(4)을 마스크로 이용하여 상기 활성층(2) 일부를 노출시킨 다음 그 활성층(2) 일부에 이온주입공정(Ion Implantation)을 통해 불순물량이 5x1013atom/㎠ 이하로 되게 이온주입하여 저농도불순물도핑층(8)을 형성한 후 그 불순물 도핑층(8)위에 고농도불순물로 도핑된 폴리실리콘을 증착하여 소스/드레인영역(5)을 형성한 다음 그 소스/드레인영역(5)위에 전도성 금속을 증착하여 소스/드레인전극(6)을 형성후 선택적식각으로 패턴을 형성한 다음 표면전체에 산화실리콘(SiO2), 질화실리콘(SiNx)등의 증착으로 보호막(7)을 형성하여 화상표시장치의 제조를 완료한다.In another embodiment of the present invention, as shown in FIG. 3, a gate electrode 4 is formed on the gate insulating film 3, and then a portion of the active layer 2 is exposed using the gate electrode 4 as a mask. After ion implantation into a portion of the active layer 2 to form a low concentration impurity doping layer 8 with an impurity of 5x10 13 atoms / cm 2 or less, and then on the impurity doping layer 8 The source / drain region 5 is formed by depositing polysilicon doped with a high concentration impurity, and then a conductive metal is deposited on the source / drain region 5 to form the source / drain electrode 6, and then the pattern is selectively formed. After the formation, a protective film 7 is formed on the entire surface by deposition of silicon oxide (SiO 2 ), silicon nitride (SiNx), or the like to complete the manufacture of the image display apparatus.
이상에서 상세히 설명한 바와같이 소스/드레인 형성을 위한 이온주입공정을 제거해 소스/드레인영역의 시트저항(Sheet Regist)을 줄이는 동시에 소스/드레인 전극과의 접촉저항(Contact Regist)을 감소시키며 데이터신호의 단선을 방지할 수 있어 소자의 특성을 개선하며 이온주입 공정의 제거로 공정을 단순화하는 효과가 있다.As described in detail above, the ion implantation process for source / drain formation is eliminated to reduce sheet resistivity of the source / drain regions, and to reduce contact resistance with the source / drain electrodes and to disconnect the data signal. It is possible to prevent the improvement of the characteristics of the device and the effect of simplifying the process by removing the ion implantation process.
Claims (5)
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KR1019920018902A KR100254924B1 (en) | 1992-10-14 | 1992-10-14 | Method of fabricating image display device |
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KR1019920018902A KR100254924B1 (en) | 1992-10-14 | 1992-10-14 | Method of fabricating image display device |
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KR940010306A KR940010306A (en) | 1994-05-24 |
KR100254924B1 true KR100254924B1 (en) | 2000-05-01 |
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KR1019920018902A KR100254924B1 (en) | 1992-10-14 | 1992-10-14 | Method of fabricating image display device |
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KR100359795B1 (en) * | 1995-08-22 | 2003-01-14 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display and method for fabricating the same |
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