KR940010306A - Method of manufacturing thin film transistor - Google Patents

Method of manufacturing thin film transistor Download PDF

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Publication number
KR940010306A
KR940010306A KR1019920018902A KR920018902A KR940010306A KR 940010306 A KR940010306 A KR 940010306A KR 1019920018902 A KR1019920018902 A KR 1019920018902A KR 920018902 A KR920018902 A KR 920018902A KR 940010306 A KR940010306 A KR 940010306A
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KR
South Korea
Prior art keywords
forming
active layer
thin film
film transistor
layer
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Application number
KR1019920018902A
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Korean (ko)
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KR100254924B1 (en
Inventor
양명수
Original Assignee
이헌조
주식회사 금성사
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Priority to KR1019920018902A priority Critical patent/KR100254924B1/en
Publication of KR940010306A publication Critical patent/KR940010306A/en
Application granted granted Critical
Publication of KR100254924B1 publication Critical patent/KR100254924B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 박막트랜지스터 제조방법에 관한 것으로, 종래에는 소스 드레인형성을 위해 게이트 전극 패턴형성후 게이트 절연막을 선택적식각하여 활성층에 이온주입 공정으로 불순물을 주입하여 제조하므로 이온주입 공정에의해 소스 드레인의 시트 저항과 접촉저항이 증가하여 소자의 특성을 저하시키고 제조시 공정이 복잡한 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor. In the related art, a sheet of a source drain is formed by an ion implantation process because an impurity is implanted into the active layer by an ion implantation process by selectively etching a gate insulating layer after forming a gate electrode pattern to form a source drain. Increasing resistance and contact resistance deteriorated the characteristics of the device and there was a complicated process in manufacturing.

본 발명은 상기와 같은 종래의 문제점을 감안하여 소스 드레인형성시 게이트 전극 패턴 형성후 게이트 절연막을 선택적식각한 다음 도핑된 실리콘을 활성층에 증착하여 제조하므로 이온주입 공정을 제거하여 공정을 단순화하고 소스 드레인의 접촉저항과 시트 저항을 줄일 수 있어 소자의 특성을 개선하는 효과가 있다.In view of the above-described conventional problems, the present invention manufactures a gate insulating film after forming a gate electrode pattern and then deposits doped silicon in an active layer to form a source electrode, thereby simplifying the process by eliminating an ion implantation process. It is possible to reduce the contact resistance and sheet resistance of the, thereby improving the characteristics of the device.

Description

박막트랜지스터 제조방법Method of manufacturing thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가) 내지 (마)는 본 발명의 박막트랜지스터 제조 공정을 보인 단면도,(A) to (E) of Figure 2 is a cross-sectional view showing a manufacturing process of the thin film transistor of the present invention,

제3도는 본 발명 다른 실시예의 박막트랜지스터 단면도,3 is a cross-sectional view of a thin film transistor of another embodiment of the present invention;

제4도는 본 발명의 박막트랜지스터를 포함하는 액정표시소 화소평면도.4 is a pixel plan view of a liquid crystal display including the thin film transistor of the present invention.

Claims (5)

절연기판(1)상에 활성층(2)을 형성하는 단계와, 그 활성층(2)위에 게이트 절연막(3)과 게이트 전극(4)을 형성하는 단계와, 그 게이트전극(4)위에 절연막(3′)을 형성후 상기 게이트 절연막(3)을 선택적식각으로 상기 활성층(2) 일부를 노출시키는 단계와, 상기 활성층(2)에 도핑된 폴리실리콘을 증착하여 소스 드레인(6)과 보호막(7)을 형성하는 단계로 제조하는 박막트랜지스터의 제조방법.Forming an active layer 2 on the insulating substrate 1, forming a gate insulating film 3 and a gate electrode 4 on the active layer 2, and forming an insulating film 3 on the gate electrode 4. And forming a portion of the active layer 2 by selectively etching the gate insulating layer 3 and depositing polysilicon doped in the active layer 2 to form the source drain 6 and the protective layer 7. Method of manufacturing a thin film transistor to form a step of forming a. 제1항에 있어서, 상기 활성층(2)은 불순물도핑층(8)을 포함하여 제조하는 박막트랜지스터 제조방법.The method of claim 1, wherein the active layer (2) comprises an impurity doped layer (8). 제2항에 있어서, 상기 불순물 도핑층(8)은 불순물을 5×1013aton/㎠ 이하로 제조하는 박막트랜지스터 제조방법.The method of claim 2, wherein the impurity doping layer (8) manufactures impurities at 5 × 10 13 aton / cm 2 or less. 제1항에 있어서, 상기 소스 드레인 전극(6)은 Al. W. Ta. Cr. Mo중 하나로 제조하는 박막트랜지스터 제조방법.The method of claim 1, wherein the source drain electrode (6) is Al. W. Ta. Cr. Method for manufacturing a thin film transistor manufactured by one of Mo. 제1항에 있어서, 상기 소스 드레인(5)은 도핑된 폴리실리콘증착후 열처리로 제조하는 박막트랜지스터 제조방법.The method of claim 1, wherein the source drain (5) is manufactured by heat treatment after doping polysilicon deposition. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920018902A 1992-10-14 1992-10-14 Method of fabricating image display device KR100254924B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920018902A KR100254924B1 (en) 1992-10-14 1992-10-14 Method of fabricating image display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920018902A KR100254924B1 (en) 1992-10-14 1992-10-14 Method of fabricating image display device

Publications (2)

Publication Number Publication Date
KR940010306A true KR940010306A (en) 1994-05-24
KR100254924B1 KR100254924B1 (en) 2000-05-01

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Application Number Title Priority Date Filing Date
KR1019920018902A KR100254924B1 (en) 1992-10-14 1992-10-14 Method of fabricating image display device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359795B1 (en) * 1995-08-22 2003-01-14 엘지.필립스 엘시디 주식회사 Liquid crystal display and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359795B1 (en) * 1995-08-22 2003-01-14 엘지.필립스 엘시디 주식회사 Liquid crystal display and method for fabricating the same

Also Published As

Publication number Publication date
KR100254924B1 (en) 2000-05-01

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