JP3147365B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention particularly relates to a thin film transistor applied to an active matrix type liquid crystal display, an image sensor, a three-dimensional integrated circuit, or the like.

[Conventional technology]

An example of the structure of a conventional thin film transistor will be described with reference to a structure sectional view in the channel direction shown in FIG. A source region 202 and a drain region 203 made of a polycrystalline silicon film to which an impurity serving as a donor or an acceptor is added are formed on an insulating substrate 201 such as glass or quartz. A channel region 204 made of a polycrystalline silicon thin film is provided in contact with the upper side of the source region and the upper end of the drain region so as to connect the two. The whole is covered with a gate oxide film 205 formed by thermal oxidation, on which a gate electrode made of metal such as chromium, aluminum, etc.
206 are provided. Further, the whole is covered with an interlayer insulating film 207 made of an insulating film such as a CVD silicon oxide film. A source electrode 208 made of a metal, a transparent conductive film, or the like made of ITO and aluminum is formed in the source region 202 through the contact hole 210, and a drain electrode 209 is formed in the drain region 203.
It is connected to the.

[Problems to be solved by the invention]

However, the above-mentioned prior art has the following problems.

First, when considering the realization of a large liquid crystal display, the process, due to the problem of the glass used for the substrate,
In particular, the formation of a gate oxide film, which has been conventionally performed at a temperature of about 1000 ° C., must be lowered. As a countermeasure, a method has been considered in which a silicon oxide film is deposited by a CVD method and this is used as a gate oxide film.

Second, if you want to realize a liquid crystal display with a built-in driver, you need to increase the speed of the transistors. For this purpose, first, it is necessary to adopt a polycrystalline silicon thin film transistor (POLY-SiTFT) in which the channel portion is composed of a polycrystalline silicon film and to reduce the parasitic capacitance between the gate electrode and the source / drain. is there. As a method of reducing the parasitic capacitance, it is effective to perform a self-alignment process widely used for MOS transistors. That is, after forming the gate electrode,
Using it as a mask, selectively add impurities,
The source and the drain are formed. The condition for adopting the self-alignment process is that the gate electrode material can serve as a mask when adding impurities, and it is necessary to change from conventional metals such as chromium and aluminum to silicon films to which impurities are added. is there.

However, trying to do the above two at the same time creates a new problem. That is, when the gate oxide film is changed from a thermal oxide film to a CVD oxide film, 350 ° C.
When the above heat is applied, transistor characteristics are significantly deteriorated.

FIG. 3 shows the characteristics of a transistor in which a gate oxide film is formed using a CVD oxide film, annealing is performed at each temperature, and then a chromium gate electrode is formed. Here, the temperature for depositing chromium is 350 ° C. or less. According to this graph, in the case of a gate oxide film made of a CVD oxide film, after forming the gate oxide film,
It can be seen that when heat of 350 ° C. or more is applied, the transistor characteristics are significantly deteriorated.

When changing the gate electrode material from a conventional metal such as chromium or aluminum to a silicon film to which impurities are added, it is common to form a silicon film by the LPCVD method, but the temperature of this special LPCVD furnace is 400 ° C. That's all. As a result, the transistor characteristics deteriorated.

SUMMARY OF THE INVENTION The present invention solves this problem, and an object of the present invention is to provide a polycrystalline silicon thin film transistor which can be formed at a low temperature and has a high speed in order to realize a large liquid crystal display with a built-in driver. It is in the thing.

[Means for solving the problem]

The present invention relates to a method for manufacturing a thin film transistor having a source / drain region, a channel region disposed between the source / drain regions, and a gate electrode disposed opposite to the channel region via a gate insulating film. The gate insulating film is formed by a CVD method,
The method of forming the gate electrode includes a step of forming an amorphous silicon thin film to which impurities are added by plasma CVD at a temperature of 350 ° C. or less, and then exposing the amorphous silicon thin film to an atmosphere of 350 ° C. or less to activate the impurities in the amorphous silicon thin film. It is characterized by including.

The present invention is further characterized in that, in the step of activating the impurities in the amorphous silicon thin film, the activation of the impurities in the silicon thin film in the source / drain regions is performed simultaneously.

[Action]

Conventionally, when performing a self-alignment process, a step of depositing a polycrystalline silicon film as a gate electrode material and a step of activating an impurity for forming a source / drain are performed at a temperature of 350 ° C. or higher after forming a gate insulating film. was there.
According to the present invention, an amorphous silicon film formed by plasma CVD is used for a gate electrode material, and impurity activation of a source / drain region and a gate electrode portion is performed by plasma irradiation, so that each step can be performed. The temperature can be reduced to 350 ° C or less. This is because C
This shows that the self-alignment process can be used without deteriorating the transistor characteristics even if the silicon oxide film formed by the VD method is used.

From the above, the gate electrode can be formed at a low temperature and
A small-capacity thin-film transistor with a low operating speed and low source-drain parasitic capacitance has been realized, enabling a large liquid crystal display with a built-in driver.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 is an example of a sectional structural view showing a thin film transistor according to the present invention (see FIG. 1 (c)) and a process sectional view showing steps for realizing the same. On an insulating substrate 101 made of glass, quartz, sapphire or the like, patterns 102 and 103 made of a silicon thin film such as polycrystalline silicon or amorphous silicon are formed. A pattern 104 made of a polycrystalline silicon film is provided so as to be in contact with the upper side and to connect the two. Next, the entire structure is covered with a gate insulating film 105 made of an insulating film such as a silicon oxide film formed by a CVD method, and an impurity-added amorphous silicon layer formed at 350 ° C. or less by a plasma CVD method thereon. The gate electrode 106 is formed. (See FIG. 1A.) Subsequently, using the gate electrode 106 as a mask, an impurity serving as a donor or an acceptor is added by an ion implantation method, an ion doping method, or the like, and the source region 107 and the drain region are self-aligned. Form 108. Thereafter, impurities in the gate electrode 106, the source region 107, and the drain region 108 are activated by, for example, exposure to a hydrogen plasma atmosphere. (Refer to FIG. 1 (b).) Thereafter, deposition of an interlayer insulating film 109, opening of a contact hole 110, a source electrode 111 made of a metal, a transparent conductive film, etc. Then, the thin film transistor according to the present invention is completed by connecting to the drain region 108. (See FIG. 1 (c)) (Another Embodiment 2 of the Invention) FIG. 4 is a cross-sectional structural view showing a thin film transistor according to the present invention (see FIG. 4 (c)) and steps for realizing it. It is another Example of a process sectional view. On an insulating substrate 401 made of glass, quartz, sapphire or the like, patterns 402 and 403 made of a silicon thin film such as polycrystalline silicon or amorphous silicon doped with impurities are formed. A pattern 40 made of a polycrystalline silicon film formed by laser annealing a non-crystalline silicon film so as to be in contact with the upper side and to connect the two.
4 is provided. Next, these are entirely covered with a gate insulating film 405 made of an insulating film such as a silicon oxide film formed by a CVD method, and an amorphous silicon layer doped with impurities formed thereon at a temperature of 350 ° C. or less by a plasma CVD method. The gate electrode 406 is formed. (See FIG. 4A.) Subsequently, using the gate electrode 406 as a mask, an impurity serving as a donor or an acceptor is added by an ion implantation method, an ion doping method, or the like, and the source region 407 and the drain region are self-aligned. Form 408. Thereafter, the impurities in the gate electrode 406, the source region 407, and the drain region 408 are activated, for example, by exposing them to a hydrogen plasma atmosphere. (Refer to FIG. 4 (b).) Thereafter, an interlayer insulating film 409 is deposited, a contact hole 410 is opened, a source electrode 411 made of metal, a transparent conductive film, and the like, and a drain electrode 412 is similarly formed in the source region 407 according to a normal process. Then, the thin film transistor according to the present invention is completed by connecting to the drain region 408. (See FIG. 4 (c)) (Other Embodiment 3 of the Invention) FIG. 5 is a cross-sectional structural view showing a thin film transistor according to the present invention (see FIG. 5 (c)) and steps for realizing it. It is another Example of a process sectional view.

A pattern 502 made of a polycrystalline silicon thin film is formed on an insulating substrate 501 made of glass, quartz, sapphire, or the like. Next, the entire structure is covered with a gate insulating film 503 made of an insulating film such as a silicon oxide film formed by a CVD method, and an amorphous silicon layer doped with impurities formed at a temperature of 350 ° C. or less by a plasma CVD method. Gate electrode 504
To form (See FIG. 5A.) Subsequently, using the gate electrode 504 as a mask, an impurity serving as a donor or an acceptor is added by an ion implantation method, an ion doping method, or the like, and the source region 505 and the drain region are self-aligned. Form 506. Thereafter, the impurities in the gate electrode 504, the source region 505, and the drain region 506 are activated, for example, by exposing them to a hydrogen plasma atmosphere. (Refer to FIG. 5 (b).) After that, according to a normal process, deposition of an interlayer insulating film 507, opening of a contact hole 508, a source electrode 509 made of a metal, a transparent conductive film, etc. And the drain region 506 to complete the thin film transistor according to the present invention. (Refer to FIG. 5 (c).) In the embodiment for realizing the present invention, an amorphous silicon layer doped with impurities and formed at 350 ° C. or less by a plasma CVD method as a gate electrode material is used. After depositing an amorphous silicon layer with no impurity added, formed at 350 ° C or lower by CVD,
The donor region does not depart from the gist of the present invention even if an impurity serving as an acceptor is added by an ion implantation method, an ion doping method, or the like.

In the above description, the activation of the impurity in the gate electrode and the activation of the impurity in the source region and the drain region are performed at the same time. However, performing these separately does not depart from the gist of the present invention.

In addition, in the above description, the gate insulating film covers the source region, the drain region, and the drain region,
Even after the gate electrode is formed, the gate insulating film is selectively etched using the gate electrode as a mask to expose the source region and the drain region and then activate the impurities without departing from the spirit of the present invention.

Further, in the above description, the activation of the impurities in the gate electrode, the source region, and the drain region is performed in a hydrogen plasma atmosphere. However, even if the activation is performed in an argon plasma atmosphere, for example, the gist of the present invention is not deviated.

〔The invention's effect〕

As described above, according to the present invention, it is possible to form a gate oxide film by a CVD method, which has not been possible conventionally, and to form a thin film transistor employing a self-alignment process.

As a result, a thin film transistor which can be formed at a low temperature, has a small parasitic capacitance between the gate electrode and the source / drain, has a high operating speed, and can realize a large liquid crystal display with a built-in driver. Further, the present invention is not limited to this, and can be applied to all fields using thin film transistors such as image sensors.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a cross-sectional structure of a thin film transistor according to the present invention. FIG. 2 is a diagram showing an example of a cross-sectional structure of a conventional thin film transistor. FIG. 3 is a graph showing that when a gate oxide film is formed by a CVD method, the characteristics of the thin film transistor are degraded by a subsequent heat process. 4 and 5 are process sectional views showing an embodiment for realizing the thin film transistor according to the present invention. In the figure, 101, 201, 401, 501 ... substrate 102, 103, 104, 402, 403, 404, 502 ... silicon pattern 105, 205, 405, 503 ... gate insulating film 106, 206, 406, 504 ... gate electrode 107, 202, 407, 505 ... source region 108, 203, 408, 506 ... drain region 204 ... channel region 109, 207, 409, 507 ... interlayer insulating film 110, 210 ... 410 111,208,411,509 …… Source electrode 112,209,412,510 …… Drain electrode

Claims (2)

(57) [Claims] 1. A method of manufacturing a thin film transistor, comprising: a source / drain region; a channel region disposed between the source / drain regions; and a gate electrode disposed opposite the channel region with a gate insulating film interposed therebetween. The gate insulating film is formed by a CVD method. The method of forming the gate electrode is to form an amorphous silicon thin film doped with impurities at a temperature of 350 ° C. or less by plasma CVD, and then expose the amorphous silicon thin film to a plasma atmosphere of 350 ° C. or less. Activating the impurities in the amorphous silicon thin film. 2. The method according to claim 1, wherein in the step of activating the impurities in the amorphous silicon thin film, the impurities in the silicon thin film in the source / drain regions are simultaneously activated. Method.