JP2621619B2 - Method for manufacturing thin film transistor - Google Patents

Method for manufacturing thin film transistor

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Publication number
JP2621619B2
JP2621619B2 JP24355490A JP24355490A JP2621619B2 JP 2621619 B2 JP2621619 B2 JP 2621619B2 JP 24355490 A JP24355490 A JP 24355490A JP 24355490 A JP24355490 A JP 24355490A JP 2621619 B2 JP2621619 B2 JP 2621619B2
Authority
JP
Japan
Prior art keywords
film
thin film
semiconductor
film transistor
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24355490A
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Japanese (ja)
Other versions
JPH04122072A (en
Inventor
和弘 小林
昌宏 羽山
博之 村井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP24355490A priority Critical patent/JP2621619B2/en
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  • Thin Film Transistor (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、例えばアクティブマトリックス液晶表示
装置のスィチング素子として用いる薄膜トランジスタの
特性改善、特にオフ電流の低減に関するものである。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in characteristics of a thin film transistor used as a switching element of, for example, an active matrix liquid crystal display device, and particularly to a reduction in off current.

[従来の技術] 第5図(a)〜(e)は、従来の薄膜トランジスタの
製造方法を工程順に示す断面図である。図において、
(1)はガラス等の絶縁性物質を用いた絶縁性基板、
(2)はCr等の金属を用い基板(1)上に形成されたゲ
ート電極、(3)はゲート電極(2)を覆うように形成
された窒化Siなどからなるゲート絶縁膜、(4)はゲー
ト絶縁膜(3)の上部に接するように形成されたノンド
ープSi膜等の半導体を用いた半導体膜、(5)は半導体
膜(4)上、薄膜トランジスタのチャネル部上を覆う窒
化Si膜等で形成された保護膜、(6)は保護膜(5)上
に保護膜(5)をパターニングすることによって形成し
たコンタクトホールを介して半導体膜(4)に接続して
形成され、かつその膜の一部である能動態領域の上部を
エッチング等で取り除いた、P等の不純物をSi等の半導
体膜にドープし形成したコンタクト膜、(7)はコンタ
クト膜(6)上部に形成された金属よりなるソース・ド
レイン電極、(8)は薄膜トランジスタ全体を保護する
ための窒化Si等で形成された第2保護膜である。
[Prior Art] FIGS. 5A to 5E are cross-sectional views showing a conventional method for manufacturing a thin film transistor in the order of steps. In the figure,
(1) is an insulating substrate using an insulating material such as glass,
(2) is a gate electrode formed on a substrate (1) using a metal such as Cr, (3) is a gate insulating film made of Si nitride or the like formed to cover the gate electrode (2), (4) Is a semiconductor film using a semiconductor such as a non-doped Si film formed so as to be in contact with the upper part of the gate insulating film (3); (5) is a Si nitride film covering the semiconductor film (4) and the channel portion of the thin film transistor; The protective film (6) is formed by connecting the semiconductor film (4) through a contact hole formed by patterning the protective film (5) on the protective film (5), and the film is formed. A contact film formed by doping impurities such as P into a semiconductor film such as Si by removing an upper portion of an active region which is a part of the active region by etching or the like; (7) is a contact film formed from a metal formed on the contact film (6); Source / drain electrodes, (8) This is a second protective film formed of silicon nitride or the like for protecting the entire thin film transistor.

まず、Cr等の金属膜を絶縁性基板(1)上に形成し、
写真製版法でゲート電極(2)パターンを形成する(第
5図a)。次いで、ゲート絶縁膜(3)、半導体膜
(4)、保護膜(5)を連続で成膜し写真製版法でパタ
ーニングを行いSiをアイランド化する(第5図b)。次
いで、写真製版法でパターニングを行い、コンタクト膜
(6)と、半導体膜(4)を接続するためのコンタクト
ホールを開ける(第5図c)。その後、コンタクト膜
(6)及びソースドレイン電極(7)を成膜し、さらに
写真製版法でパターン形成をする(第5図d)。最後に
第2保護膜(8)を形成する(第5図e)。
First, a metal film such as Cr is formed on the insulating substrate (1),
A gate electrode (2) pattern is formed by photolithography (FIG. 5a). Next, a gate insulating film (3), a semiconductor film (4), and a protective film (5) are successively formed and patterned by photolithography to form Si islands (FIG. 5b). Next, patterning is performed by photolithography to open a contact hole for connecting the contact film (6) and the semiconductor film (4) (FIG. 5c). Thereafter, a contact film (6) and a source / drain electrode (7) are formed, and a pattern is formed by photolithography (FIG. 5d). Finally, a second protective film (8) is formed (FIG. 5e).

次に薄膜トランジスタの動作について説明する。ソー
ス・ドレイン電極(7)間に例えば10〜20V程度の電圧
を印加し、ゲート電極(2)に印加する電圧を、例えば
−5V〜20Vの間で変化させることでソース・ドレイン電
極間に流れる電流を制御しスィッチング動作を行なう。
例えば、nチャンネルの薄膜トランジストの場合、ゲー
ト電極を負にした時に、トランジスタのスイッチング状
態は、オフとなり、ゲート電圧を正にしたときにスイッ
チ状態はオンとなる。
Next, the operation of the thin film transistor will be described. A voltage of, for example, about 10 to 20 V is applied between the source and drain electrodes (7), and the voltage applied to the gate electrode (2) is changed, for example, between −5 V and 20 V, to flow between the source and drain electrodes. The switching operation is performed by controlling the current.
For example, in the case of an n-channel thin film transistor, when the gate electrode is made negative, the switching state of the transistor is turned off, and when the gate voltage is made positive, the switching state is turned on.

[発明が解決しようとする課題] 良好なスィッチング動作を得るためには、例えば、n
チャンネルの薄膜トランジスタの場合、ゲート電極を正
に印加した場合にソース・ドレイン電極間に流れるドレ
イン電流(以下オン電流と記す)が大きく、ゲート電極
を負に印加した場合にソース・ドレイン間に流れるドレ
イン電流(以下オフ電流と記す)が小さい事が大切であ
る。ところが、従来の薄膜トランジスタは、マトリック
スアドレス指定方式の液晶ディスプレイ等のスィッチン
グ素子として用いる場合には、オフ電流が十分に低くな
く、その使用マージンは必ずしも大きくなかった。
[Problem to be Solved by the Invention] In order to obtain a good switching operation, for example, n
In the case of a channel thin film transistor, the drain current (hereinafter referred to as on-current) flowing between the source and drain electrodes when the gate electrode is applied positively is large, and the drain current flowing between the source and drain when the gate electrode is negatively applied. It is important that the current (hereinafter referred to as off-state current) be small. However, when a conventional thin film transistor is used as a switching element of a matrix addressing type liquid crystal display or the like, the off current is not sufficiently low, and the use margin is not always large.

この発明は、上記のような問題点を解決するためにな
されたもので、薄膜トランジスタのバックチャネルを不
活性化し、その結果として、例えば液晶ディスプレイ等
のスィッチング素子として充分に適用し得るオフ電流が
十分低い薄膜トランジスタを作製することを目的として
いる。
The present invention has been made to solve the above problems, and inactivates a back channel of a thin film transistor. As a result, for example, an off current that can be sufficiently applied as a switching element such as a liquid crystal display is sufficiently reduced. It is intended to manufacture a thin film transistor.

[課題を解決するための手段] この発明の薄膜トランジスタの製造方法は、薄膜トラ
ンジスタの保護膜形成前に半導体・保護膜界面側の半導
体膜の膜表面を、H2ガスを導入し形成したプラズマ中に
曝し、半導体膜・保護膜界面の界面準位を上げるように
したものである。
[Means for Solving the Problems] According to a method of manufacturing a thin film transistor of the present invention, a film surface of a semiconductor film on a semiconductor / protective film interface side is formed in a plasma formed by introducing an H 2 gas before a protective film of the thin film transistor is formed. Exposure increases the interface state at the interface between the semiconductor film and the protective film.

[作用] この発明においては、半導体膜を上記プラズマ中に曝
し、半導体膜・保護膜界面の界面準位を上げるようにし
たので、薄膜トランジスタのバックチャネルを不活性化
し、薄膜トランジスタのオフ動作時にバックチャネルに
流れる漏れ電流を減少させ、その結果として薄膜トラン
ジスタのオフ電流を低減させることができる。
[Operation] In the present invention, the semiconductor film is exposed to the plasma to raise the interface state at the interface between the semiconductor film and the protective film. Therefore, the back channel of the thin film transistor is inactivated, and the back channel is turned off when the thin film transistor is turned off. Of the thin film transistor, and as a result, the off current of the thin film transistor can be reduced.

[実施例] 以下この発明の実施例を図について説明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.

第1図(a)〜(g)の工程順に示す断面図に基づ
き、この発明の一実施例の薄膜トランジスタの製造方法
を説明する。
A method for manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to the cross-sectional views shown in the order of steps of FIGS.

まず、Cr等の金属膜を絶縁性基板(1)上に形成し、
写真製版法でゲート電極パターン(2)を形成する(第
1図a)。次いで、ゲート絶縁膜(3)、半導体膜
(4)を成膜後(第1図b)、半導体膜(4)の表面を
H2ガスを導入し形成したプラズマ中に曝す(第1図
c)。次いで、保護膜(5)を成膜し、写真製版法でパ
ターニングを行いSiをアイランド化する(第1図d)。
その後、写真製版法でパターニングを行い、コンタクト
膜(6)と半導体膜(4)を接続するためのコンタクト
ホールを開ける(第1図e)。次いで、コンタクト膜
(6)、及びソースドレイン電極(7)を成膜し、その
後写真製版法でパターン形成をする(第1図f)。最後
に第2保護膜(8)を形成する(第1図g)。
First, a metal film such as Cr is formed on the insulating substrate (1),
A gate electrode pattern (2) is formed by photolithography (FIG. 1a). Next, after forming a gate insulating film (3) and a semiconductor film (4) (FIG. 1b), the surface of the semiconductor film (4) is removed.
The H 2 gas is introduced and exposed to the formed plasma (FIG. 1c). Next, a protective film (5) is formed and patterned by photolithography to form Si islands (FIG. 1d).
Thereafter, patterning is performed by photolithography to open a contact hole for connecting the contact film (6) and the semiconductor film (4) (FIG. 1e). Next, a contact film (6) and a source / drain electrode (7) are formed, and then a pattern is formed by photolithography (FIG. 1f). Finally, a second protective film (8) is formed (FIG. 1g).

次に薄膜トランジスタの動作について説明する。 Next, the operation of the thin film transistor will be described.

ソース・ドレイン電極(7)間に例えば10〜20V程度の
電圧を印加し、ゲート電極(2)に印加する電圧を、例
えば−5V〜20Vの間で変化させることでソース・ドレイ
ン電極間に流れる電流を制御しスィッチング動作を行な
う。例えば、nチャンネルの薄膜トランジストの場合、
ゲート電極を負にしたときにトランジスタのスイッチン
グ状態は、オフとなり、ゲート電圧を正にしたときにス
イッチ状態はオンとなる。
A voltage of, for example, about 10 to 20 V is applied between the source and drain electrodes (7), and the voltage applied to the gate electrode (2) is changed, for example, between −5 V and 20 V, to flow between the source and drain electrodes. The switching operation is performed by controlling the current. For example, for an n-channel thin film transistor,
When the gate electrode is made negative, the switching state of the transistor is turned off, and when the gate voltage is made positive, the switching state is turned on.

この発明においては、薄膜トランジスタの保護膜形成
前に半導体・保護膜界面側の半導体層の膜表縁をH2ガス
を導入し形成したプラズマ中に曝し、半導体膜・保護膜
界面の界面準位を増加させることで、薄膜トランジスタ
のバックチャネルを不活性化し、薄膜トランジスタのオ
フ動作時にバックチャネルに流れる漏れ電流を減少さ
せ、その結果として薄膜トランジスタのオフ電流を低減
させている。
In the present invention, before forming the protective film of the thin film transistor, the film surface of the semiconductor layer on the semiconductor / protective film interface side is exposed to a plasma formed by introducing H 2 gas to reduce the interface state at the semiconductor film / protective film interface. By increasing the thickness, the back channel of the thin film transistor is inactivated, the leakage current flowing through the back channel during the off operation of the thin film transistor is reduced, and as a result, the off current of the thin film transistor is reduced.

ゲート絶縁膜(3)として窒化Si膜、半導体膜(4)
として非晶質Si、保護膜(5)として窒化Si膜、コンタ
クト膜(6)として隣を不純物としてドープした非晶質
Siを用い、表に示す条件のH2プラズマに曝し、この発明
の一実施例による薄膜トランジスタ作製した。この実施
例のオフ電流の温度依存性をドレイン電圧20V、ゲート
電圧−5V、トランジスタのチャンネル幅とチャンネル長
の比:W/L=40/5の測定条件で測定した。その結果を第2
図の特性図に従来法によるH2プラズマ中に曝していない
比較例とともに示す。縦軸はオフ電流、横軸は絶対温度
の逆数で、特性曲数Aがこの実施例の水素プラズマ照射
有りの、Bが比較例の水素プラズマ照射無しのオフ電流
の温度依存性を表わす。図からわかるように薄膜トラン
ジスタの半導体・保護膜界面側の半導体膜(4)の膜表
面をH2プラズマに曝すことによりオフ電流が低下すると
ともに、水素プラズマ照射無しの時0.46eVであった、オ
フ電流の活性化エネルギーがプラズマ照射することによ
り0.65eVと増加している。
Silicon nitride film, semiconductor film (4) as gate insulating film (3)
Amorphous silicon, a protective film (5) as a silicon nitride film, and a contact film (6) as an adjacent doped impurity.
Using Si, the thin film transistor according to one embodiment of the present invention was exposed to H 2 plasma under the conditions shown in the table. The temperature dependence of the off-state current in this example was measured under the measurement conditions of a drain voltage of 20 V, a gate voltage of −5 V, and a ratio of channel width to channel length of the transistor: W / L = 40/5. The result is
By the conventional method in the characteristic diagram of Fig together with comparative examples not exposed in H 2 plasma. The vertical axis represents the off-current, and the horizontal axis represents the reciprocal of the absolute temperature. The characteristic number A represents the temperature dependence of the off-state current without hydrogen plasma irradiation of the comparative example, and B represents the hydrogen plasma irradiation of this embodiment. As can be seen from the figure, when the film surface of the semiconductor film (4) on the semiconductor / protective film interface side of the thin film transistor is exposed to H 2 plasma, the off-state current is reduced, and the off-state current was 0.46 eV without hydrogen plasma irradiation. The activation energy of the current increased to 0.65 eV by plasma irradiation.

また、保護膜(5)上にバックゲート電極を形成して
バックゲート電極とソース電極(7)間の容量−電圧特
性を測定した。その結果を第3図の特性図に示す。縦軸
が容量(pF)、横軸が電圧(V)で、特性曲線Cがこの
実施例の水素プラズマ照射有りの、Dが比較例の水素プ
ラズマ照射無しの容量−電圧特性を表わす。薄膜トラン
ジスタの半導体・保護膜界面側の半導体膜(4)の膜表
面をH2プラズマに曝していない比較例の場合は、容量−
電圧特性がバックゲート電圧を正に印加することで増加
するが、薄膜トランジスタの半導体・保護膜界面側の半
導体膜(4)の膜表面を、H2プラズマに曝したこの実施
例の場合は、バックゲート電圧を正に印加しても、容量
−電圧特性の変化は見られない。これより、H2プラズマ
に曝すことにより半導体・保護膜界面の界面準位が増加
し不活性化していると考えられる。
Further, a back gate electrode was formed on the protective film (5), and the capacitance-voltage characteristics between the back gate electrode and the source electrode (7) were measured. The results are shown in the characteristic diagram of FIG. The vertical axis indicates the capacitance (pF), the horizontal axis indicates the voltage (V), and the characteristic curve C indicates the capacity-voltage characteristics of the present example with hydrogen plasma irradiation, and the characteristic curve C indicates the comparative example without hydrogen plasma irradiation. If the film surface of the thin film transistor of the semiconductor-protective film interface side of the semiconductor film (4) of Comparative Example not exposed in H 2 plasma, capacity -
Although the voltage characteristics increase when the back gate voltage is applied positively, in the case of this embodiment in which the film surface of the semiconductor film (4) on the semiconductor / protective film interface side of the thin film transistor is exposed to H 2 plasma, Even if the gate voltage is applied positively, no change in the capacitance-voltage characteristics is observed. From this, believed interface state of the semiconductor-protective film interface by exposing in H 2 plasma is increased inactivated.

以上の結果から、保護膜形成前に半導体膜・保護膜界
面側の半導体膜(4)の膜表面をH2ガスを導入し形成し
たプラズマ中に曝すことにより、薄膜トランジスタの半
導体・保護膜界面の界面準位が増加し不活性化し、その
結果として、半導体・保護膜界面のエネルギーバンドが
第4図(b)の説明図の様になり、オフ時に薄膜トラン
ジスタの半導体・保護膜界面を通じてリーク電流として
流れるバックチャネル電流が低下し、その結果としてオ
フ電流が減少したと考えられる。第4図(a)は従来例
による薄膜トランジスタの半導体・保護膜界面のエネル
ギーバンドを示す説明図である。
From the above results, before the formation of the protective film, the film surface of the semiconductor film (4) on the semiconductor film / protective film interface side is exposed to the plasma formed by introducing H 2 gas, whereby the semiconductor / protective film interface of the thin film transistor is formed. The interface level increases and becomes inactive. As a result, the energy band at the interface between the semiconductor and the protective film becomes as illustrated in FIG. 4 (b). It is considered that the flowing back channel current decreased, and as a result, the off current decreased. FIG. 4 (a) is an explanatory diagram showing an energy band at an interface between a semiconductor and a protective film of a conventional thin film transistor.

なお、上記実施例では、半導体膜(4)として非晶質
Si膜を用いた場合について説明したが、半導体膜(4)
として多結晶Si膜を用いても同様な効果を有する。
In the above embodiment, the semiconductor film (4) is amorphous.
The case where the Si film is used has been described, but the semiconductor film (4)
The same effect can be obtained even if a polycrystalline Si film is used.

なお、上記実施例では、薄膜トランジスタは、nチャ
ンネルのものについて説明したが、pチャンネルのもの
を用いても同様な効果を有する。
In the above embodiment, the n-channel thin film transistor has been described. However, a similar effect can be obtained by using a p-channel thin film transistor.

[発明の効果] 以上のようにこの発明によれば、薄膜トランジスタを
製造する際、保護膜形成前に半導体膜・保護膜界面側の
半導体膜の膜表面をH2ガスを導入し形成したプラズマ中
に曝し、半導体膜・保護膜界面の界面準位をプラズマ照
射前と比べ増加させることにより、半導体膜・保護膜界
面の半導体膜の導電率・移動度を減少させ不活性化し、
薄膜トランジスタのオフ電流を低減できる効果がある。
[Effects of the Invention] As described above, according to the present invention, when manufacturing a thin film transistor, the film surface of the semiconductor film on the interface side of the semiconductor film and the protective film is formed by introducing H 2 gas into the plasma before forming the protective film. Exposure to increase the interface state at the interface between the semiconductor film and the protective film compared to that before plasma irradiation, thereby decreasing the conductivity and mobility of the semiconductor film at the interface between the semiconductor film and the protective film, and inactivating the semiconductor film.
The off-current of the thin film transistor can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(g)はこの発明の一実施例の薄膜トラ
ンジスタの製造方法を工程順に示す断面図、第2図はこ
の発明の一実施例による薄膜トランジスタのオフ電流の
温度依存性を比較例とともに示す特性図、第3図は同、
ソース電極とバックゲート電極間で測定した容量−電圧
特性を比較例とともに示す特性図、第4図(a)はこの
一実施例のバックチャネル側の半導体膜・保護膜界面の
定性的なエネルギーバンド図を示す説明図、同図(b)
は同比較例の説明図、第5図(a)〜(e)は従来の薄
膜トランジスタの製造方法を工程順に示す断面図であ
る。 (1)は絶縁性基板、(2)はゲート電極、(3)はゲ
ート絶縁膜、(5)は保護膜、(4)は半導体膜、
(6)はコンタクト膜、(7)はソース・ドレイン電極
である。 なお、図中、同一符号は同一又は相当部分を示す。
1A to 1G are cross-sectional views showing a method of manufacturing a thin film transistor according to an embodiment of the present invention in the order of steps, and FIG. 2 compares the temperature dependence of off current of the thin film transistor according to an embodiment of the present invention. The characteristic diagram shown with the example, FIG.
FIG. 4 (a) is a characteristic diagram showing capacitance-voltage characteristics measured between a source electrode and a back gate electrode together with a comparative example. FIG. Explanatory drawing showing the figure, FIG.
5A to 5E are explanatory views of the comparative example, and FIGS. 5A to 5E are cross-sectional views showing a conventional method of manufacturing a thin film transistor in the order of steps. (1) is an insulating substrate, (2) is a gate electrode, (3) is a gate insulating film, (5) is a protective film, (4) is a semiconductor film,
(6) is a contact film, and (7) is a source / drain electrode. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁性基板と、ゲート電極と、ゲート絶縁
膜と、半導体膜と、この半導体膜に形成される保護膜
と、コンタクト膜と、ソース電極と、ドレイン電極とを
有する薄膜トランジスタを製造する方法において、上記
保護膜形成前に上記半導体膜・保護膜界面の半導体膜の
膜表面をH2ガスを導入し形成したプラズマ中に曝し、上
記半導体膜・保護膜界面の界面準位を上げるようにした
ことを特徴とする薄膜トランジスタの製造方法。
A thin film transistor having an insulating substrate, a gate electrode, a gate insulating film, a semiconductor film, a protective film formed on the semiconductor film, a contact film, a source electrode, and a drain electrode is manufactured. In the method, before forming the protective film, the film surface of the semiconductor film at the interface between the semiconductor film and the protective film is exposed to plasma formed by introducing H 2 gas to raise the interface state at the interface between the semiconductor film and the protective film. A method for manufacturing a thin film transistor, characterized in that:
JP24355490A 1990-09-12 1990-09-12 Method for manufacturing thin film transistor Expired - Lifetime JP2621619B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24355490A JP2621619B2 (en) 1990-09-12 1990-09-12 Method for manufacturing thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24355490A JP2621619B2 (en) 1990-09-12 1990-09-12 Method for manufacturing thin film transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP30210596A Division JP2671898B2 (en) 1996-11-13 1996-11-13 Method for manufacturing thin film transistor

Publications (2)

Publication Number Publication Date
JPH04122072A JPH04122072A (en) 1992-04-22
JP2621619B2 true JP2621619B2 (en) 1997-06-18

Family

ID=17105587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24355490A Expired - Lifetime JP2621619B2 (en) 1990-09-12 1990-09-12 Method for manufacturing thin film transistor

Country Status (1)

Country Link
JP (1) JP2621619B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759283B2 (en) 2001-05-16 2004-07-06 Nec Lcd Technologies, Ltd. Thin film transistor and method of fabricating the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01316488A (en) * 1988-06-13 1989-12-21 Yoshiharu Matsuda Iron-terbium binary alloy plating solution
JP2639356B2 (en) * 1994-09-01 1997-08-13 日本電気株式会社 Method for manufacturing thin film transistor
JP2780673B2 (en) * 1995-06-13 1998-07-30 日本電気株式会社 Active matrix type liquid crystal display device and manufacturing method thereof
JP3404562B2 (en) * 1996-11-18 2003-05-12 株式会社日立製作所 Active matrix type liquid crystal display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759283B2 (en) 2001-05-16 2004-07-06 Nec Lcd Technologies, Ltd. Thin film transistor and method of fabricating the same

Also Published As

Publication number Publication date
JPH04122072A (en) 1992-04-22

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