JP3210196B2 - Thin film transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a liquid crystal display (TFT: Thin Film Transistor) using the thin film transistor.
The present invention relates to a structure of a semiconductor device applied to an er-LCD (Liquid Crystal Display) and a method of manufacturing the same.

[0002]

2. Description of the Related Art A known document describing a conventional thin film transistor is disclosed in, for example, JP-A-63-16805.
No. 2 publication is available. This publication discloses a self-aligned thin film transistor which can be manufactured stably without a lift-off step in the manufacture of an amorphous silicon thin film transistor in order to reduce parasitic capacitance and realize high performance of a device, and to manufacture the same. It provides a method. That is, a method of manufacturing a completely self-aligned thin film transistor using the ion doping method is disclosed. U.S. Pat. No. 5,241,192 also discloses a thin film transistor structure for reducing edge leakage.

FIG. 5 is a configuration diagram of a conventional thin film transistor, in which 201 is an insulating substrate, 202 is a gate electrode,
203 is a gate insulating film, 204 is an amorphous silicon thin film,
205 is a channel protective film, 206 is an n + type amorphous silicon thin film, 207 is a source / drain electrode, and 208 is a picture element electrode.

In this case, the channel protective film is formed in a self-aligned manner by back surface exposure using the gate electrode as a mask.
The type amorphous silicon thin film 206 is formed by using a patterned channel protective film as a mask, discharging and decomposing gas containing impurities such as phosphine diluted with hydrogen, and accelerating and implanting generated ions. Then the source
Completely self-aligned TFT by forming a drain metal electrode and a pixel electrode having electrical connection with the drain electrode
Is completed.

[0005]

As described above, in the conventional thin film transistor, the formation of the n + layer is achieved by implanting impurity ions by the ion doping method using the channel protective film 205 as a mask. At the time of this ion doping, the edge of the channel protective film 205 serving as a mask for ion doping is formed as shown in FIG.
Due to its processing characteristics, it has a certain taper angle, and in the region below the taper of the channel protective layer 205, at least some implanted impurity ions are present. 209 are formed (FIG. 7). If the conductive layer 209 is not completely removed, a leak current occurs between the source and drain electrodes of the transistor due to the conductive layer formed on the edge of the channel protective film 205, and good transistor characteristics cannot be obtained.

The present invention has been made in view of such circumstances, and in a thin film transistor in which an n + layer is formed by an ion doping method, a conductive layer at an edge portion of a channel protective film is surely cut, and a source / drain is formed. It is an object of the present invention to provide a thin film transistor and a method of manufacturing the same, in which the problem of the leak current between the electrodes is solved and the n + conductive layer region generated at the ion implantation mask edge is reliably removed to improve the thin film transistor characteristics. And

[0007]

According to the present invention, in order to solve the above-mentioned problems, (1) a gate electrode 103 formed on a transparent insulating substrate 101 and a gate electrode 103 formed so as to cover the gate electrode 103 are provided. 1 insulating film 105 and the first insulating film 1
The second insulating film 107 formed on the semiconductor layer 106 is self-aligned with the gate electrode 103 using the amorphous semiconductor layer or microcrystalline semiconductor layer 106 formed on The semiconductor layer 106 is doped with impurities using the second insulating film 107 or the resist pattern of the second insulating film 107 as a mask, and an n + layer 108 is formed. And the second insulating film 1
In the region where the impurity is ion-implanted into the semiconductor layer 106 below the region 07, the conductive region below the edge of the channel protective film is removed.
(2) the amorphous or microcrystalline or polycrystalline semiconductor layer 123 formed on the transparent insulating substrate 121 is completely removed and the portion connected between the source and the drain is cut; A first insulating film formed to cover the semiconductor layer 123;
A gate electrode 125 formed thereon and the gate electrode 12
5 or using the resist pattern of the gate electrode 125 as a mask, doping impurities into the semiconductor layer 123,
A positive staggered or top-gate thin film transistor forming the n + layer 122, in which a conductive region below an edge portion of a channel protective film is completely removed from a region in which impurities are ion-implanted into the semiconductor layer 123 below the gate electrode 125.
The part connected between the source and the drain is cut off, and (3) a gate electrode 103 formed on the transparent insulating substrate 101 in the thin film transistor having an inverted staggered structure; A first insulating film 105 formed so as to cover 103, a step of forming an amorphous semiconductor layer or a microcrystalline semiconductor layer 106 and a second insulating film 107 over the first insulating film 105, Using the gate electrode 103 as a mask, patterning the second insulating film 107 formed on the semiconductor layer 106 in a self-aligned manner with the gate electrode 103;
07 or using the resist pattern of the second insulating film 107 as a mask, the semiconductor layer 106 is doped with an impurity to form an n + layer 108, and the semiconductor layer 106 under the second insulating film 107 is doped with an impurity. Conductive region under the edge of the channel protective film in the ion-implanted region
Completely removing and disconnecting a portion connected between the source and the drain, or (4) in a positive staggered or top-gate thin film transistor, an amorphous layer formed on the transparent insulating substrate 121. Or forming a microcrystalline or polycrystalline semiconductor layer 123;
Forming a first insulating film 124 formed so as to cover the semiconductor layer 123, forming a gate electrode 125 on the first insulating film 124,
Or a step of forming an n + layer 122 by doping impurities on the semiconductor layer 123 using a resist pattern on the gate electrode 125 as a mask;
The method includes a step of cutting a portion connected between the source and the drain in a region in which impurities are ion-implanted into the semiconductor layer 123 below the semiconductor layer 123.

[0008]

According to the thin film transistor and the method of manufacturing the same of the present invention, after the ion doping step in the thin film transistor manufacturing step, the edge portion of the channel protective film and the semiconductor layer formed below the edge portion are separately removed by etching. A process is added to prevent leakage current of the transistor.

(1) In the first aspect of the present invention, the gate electrode is formed on a transparent insulating substrate, and the first insulating film is formed so as to cover the gate electrode. An amorphous semiconductor layer or a microcrystalline semiconductor layer is formed over the first insulating film, and a second insulating film is formed over the semiconductor using the gate electrode as a mask. Patterning the second insulating film in a self-aligned manner with the gate electrode;
The semiconductor layer is formed by doping impurities using the resist pattern of the insulating film or the second insulating film as a mask. A region under the edge of the channel protective film , in a region in which impurities are ion-implanted into the semiconductor layer under the second insulating film;
Since the conductive region is completely removed and the portion connected between the source and the drain is cut off, the leakage current of the transistor can be prevented.

(2) In the invention described in claim 2, the amorphous, microcrystalline or polycrystalline semiconductor layer is formed on a transparent insulating substrate, and the first insulating film is formed so as to cover the semiconductor layer. . A gate electrode is formed on the first insulating film, and an n + layer is formed by doping impurities on the semiconductor layer using the gate electrode or a resist pattern of the gate electrode as a mask. Among impurities are ion-implanted regions in the semiconductor layer under the gate electrode, the channel coercive
Since the conductive region under the edge portion of the protective film is completely removed, and the portion connected between the source and the drain is cut off, the leakage current of the transistor can be prevented.

(3) In the invention described in claim 3, the gate electrode formed on the transparent insulating substrate, the first insulating film formed so as to cover the gate electrode, and the gate electrode formed on the transparent insulating substrate. An amorphous semiconductor layer or a microcrystalline semiconductor layer and a second insulating film, and using the gate electrode as a mask, patterning the second insulating film formed on the semiconductor layer in a self-aligned manner with the gate electrode. Using the second insulating film or the resist pattern of the second insulating film as a mask, doping an impurity into the semiconductor layer to form an n + layer, and ion-implanting the impurity into the semiconductor layer below the second insulating film; Of the implanted region, the conductive region under the edge of the channel protective film is completely
Since removal is performed and a portion connected between the source and the drain is cut, a leakage current generated between the source and the drain can be prevented, and good transistor characteristics with excellent leakage characteristics can be realized.

(4) In the invention according to claim 4, an amorphous or microcrystalline or polycrystalline semiconductor layer is formed on a transparent insulating substrate, and the first semiconductor layer is formed so as to cover the semiconductor layer. Forming an insulating film, forming a gate electrode on the first insulating film, doping impurities on the semiconductor using the gate electrode or a resist pattern on the gate electrode as a mask, forming an n + layer, Of the regions where impurities are ion-implanted into the semiconductor layer below the gate electrode,
Since the portion connected between the drains is cut, leakage current generated between the source and the drain can be prevented, and good transistor characteristics with excellent leak characteristics can be realized.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 and 2A and 2B are configuration diagrams for explaining an embodiment of a thin film transistor according to the present invention. The TFT (Thin Film Transistor) -LCD (Liquid Crystal Display)
1 is a cross-sectional view of a TFT matrix type substrate for a liquid crystal display (quid crystal display). In the figure, 101 is an insulating substrate, 102 is a base coat insulating film, 103 is a tantalum thin film, 104 is an anodized film, 105 is a Si ₃ N ₄ film, 106 is a semiconductor film, 107
Is an Si ₃ N ₄ film, 108 is an n + silicon layer, 109 is a conductive layer region, 110 is a source / drain electrode, and 111 is a picture element electrode (indium oxide transparent conductive film: ITO).

In this embodiment, a glass substrate is used as the insulating substrate 101. Next, a base coat insulating film 102 made of Ta ₂ O _{5 is} formed on one surface of the substrate to a thickness of 3000 °. On top of this, a film thickness of 300 is formed on the base coat insulating film by a sputtering apparatus.
The tantalum thin film 103 is formed so as to be 0 °. Thereafter, the tantalum thin film 103 is patterned into a predetermined shape by a photolithography process to form the lower gate electrode 103.
To form After that, the tantalum thin film 103 is subjected to an anodic oxidation treatment to form an anodic oxide film 104. Next, PC
A VD (Chemical Vapor Deposition) method is used to form a Si ₃ N ₄ film 105 as a gate insulating film at 3000Å,
The amorphous silicon (a-Si) semiconductor film 106 is
{Circle around (3)}, a three-layer continuous film formation of the Si ₃ N ₄ film 2000 is performed.

Next, using the gate electrode 103 as a mask, back surface exposure is performed from the transparent insulating substrate 101 side, and the Si ₃ N ₄ film 107 is patterned into a predetermined shape by a photolithography process to form a channel protective film 107. . Next, using the channel protective film 107 as a mask, the a-Si semiconductor film 106 is doped with an acceleration voltage of 10 ke as a doping condition.
v, doping with impurity ions at a dose of 5 × 10 ¹⁵ / cm ² , then annealing at 250 ° C. for 1 hour to obtain n +
A silicon layer 108 is formed.

Thereafter, patterning is performed by a photolithography process so that the conductive layer region 109 which causes a leak current between the source and drain electrodes can be cut by patterning, and is etched and removed together with the upper-layer channel protective film 107. Next, the semiconductor layer is patterned into an island shape, and a Ti film 3000 # is formed. The source / drain electrodes 110 are formed by patterning into a predetermined shape by a photolithography process. The removal of the conductive layer region 109 is sufficient if the source side and the drain side are not connected, and the shape is arbitrary. In addition, the conductive layer region 109
And the step of patterning the semiconductor film into an island shape may be combined into one step. Thereafter, an ITO transparent conductive film 111 is formed to a thickness of 1000 ° by sputtering. Then, the pixel electrode 111 is formed by patterning into a predetermined shape by a photolithography process. As a result, a TFT can be realized.

As described above, the gate electrode 103 is formed on the transparent insulating substrate 101, and the first insulating film 105 is formed so as to cover the gate electrode 103. The amorphous semiconductor layer or the microcrystalline semiconductor layer 106 is formed on the first insulating film 10.
The second insulating film 107 is formed on the semiconductor 106 using the gate electrode 103 as a mask. The second insulating film 107 is patterned in a self-aligned manner with the gate electrode 103, and the n + layer 108 is formed by using the second insulating film 107 or the resist pattern of the second insulating film 107 as a mask. Is formed by doping impurities. Of the region where impurities are ion-implanted into the semiconductor layer 106 under the second insulating film 107,
Since the portion connected between the source and the drain is disconnected, leakage current of the transistor can be prevented.

An amorphous or microcrystalline or polycrystalline semiconductor layer 106 is formed on the transparent insulating substrate 101, and a first insulating film 105 is formed so as to cover the semiconductor layer 106. The gate electrode is formed on the first insulating film 105, and the n + layer 108 is formed by using the gate electrode or a resist pattern of the gate electrode as a mask,
6 is formed by doping impurities. In the region where the impurity is ion-implanted into the semiconductor layer 106 below the gate electrode, a portion connected between the source and the drain is cut, so that leakage current of the transistor can be prevented.

Further, a gate electrode 103 formed on a transparent insulating substrate 101, a first insulating film 105 formed so as to cover the gate electrode 103, and a first insulating film 10
Forming an amorphous semiconductor layer or a microcrystalline semiconductor layer 106 and a second insulating film 107 on the gate electrode 5 and using the gate electrode 103 as a mask to form the second insulating film 107 on the semiconductor layer 106. A step of patterning in a self-aligned manner with the gate electrode 103, and doping impurities into the semiconductor layer 106 using the second insulating film 107 or a resist pattern of the second insulating film 107 as a mask to form an n + layer 108 And a step of cutting a portion connected between the source and the drain in a region in which the impurity is ion-implanted into the semiconductor layer 106 below the second insulating film 107. It is possible to prevent the generated leakage current and realize good transistor characteristics having excellent leakage characteristics.

A step of forming an amorphous, microcrystalline, or polycrystalline semiconductor layer formed on the transparent insulating substrate 101; and a step of forming an eleventh insulating film formed to cover the semiconductor layer. Forming a gate electrode on the first insulating film; doping impurities on the semiconductor using the gate electrode or a resist pattern on the gate electrode as a mask to form an n + layer 108; Cutting a portion connected between the source and the drain in a region in which impurities are ion-implanted into the semiconductor layer below the gate electrode, so that a leak current generated between the source and the drain can be prevented. Good transistor characteristics with excellent characteristics can be realized.

When the semiconductor layer is doped with impurities, a step of forming a doping cap layer, a step of separately forming a mask for determining a doping region on the cap layer, and thereafter, an impurity is ion-implanted. A step of cutting a portion of the region that is connected between the source and the drain, so that a leak current generated between the source and the drain can be prevented, and good transistor characteristics with excellent leak characteristics can be realized.

In the above description, the channel protection film 107 is formed, and the semiconductor film 106 is doped with impurity ions using the mask as a mask. However, instead of the channel protection film 107, a photoresist or other material having a similar shape is used. It is also possible to form a mask pattern and use the mask as a mask to dope the semiconductor layer with impurity ions. Although the embodiment in which a-Si is used as the semiconductor layer has been described, it is needless to say that microcrystalline silicon may be used.

FIG. 3 is a structural diagram for explaining another embodiment of the thin film transistor according to the present invention. In the drawing, 121 is an insulating substrate, 122 is an n + semiconductor layer, 123 is a semiconductor layer,
124 is a first insulating film, and 125 is a gate electrode. The semiconductor layer 123 is an amorphous, microcrystalline, or polycrystalline semiconductor layer formed over the insulating substrate 121. The first insulating film 124 is formed so as to cover the semiconductor layer 123. The gate electrode 125 is formed of the first insulator film 1
24. Using the gate electrode 125 or the resist pattern of the gate electrode 125 as a mask, the semiconductor layer 123 is doped with impurities to form the n + layer 12.
2 is a positive staggered or top-gate thin film transistor, and a portion connected between a source and a drain in a region where impurities are ion-implanted into the semiconductor layer 123 below the gate electrode 125 is cut off.

In a positive staggered or top gate type thin film transistor, the amorphous or microcrystalline or polycrystalline semiconductor layer 12 formed on the transparent insulating substrate 121 is formed.
3, a step of forming a first insulating film 124 formed so as to cover the semiconductor layer 123, and a step of forming the first insulating film 124.
Forming a gate electrode 125 on the insulating film 124, and forming an n + layer 122 by doping impurities on the semiconductor layer 123 using the gate electrode 125 or a resist pattern on the gate electrode 125 as a mask. And a step of cutting a portion connected between the source and the drain in a region in which impurities are ion-implanted into the semiconductor layer 123 below the gate electrode 125.

FIG. 4 is a block diagram for explaining still another embodiment of the thin film transistor according to the present invention.
Numeral 6 denotes an n + layer (gap layer), and other portions having the same functions as those in FIG. 3 are denoted by the same reference numerals. Semiconductor layer 123
At the time of impurity doping, a doping cap layer is used. That is, the n + layer 126 is formed as a gap layer on the semiconductor layer 123. In addition, the semiconductor layer 12
A step of forming a doping cap layer 126 during the doping of impurities into the layer 3, and a step of separately forming a mask for determining a doping region on the cap layer 126;
Then, a step of cutting a portion connected between the source and the drain in the region into which the impurities are ion-implanted.

[0026]

As apparent from the above description, the present invention has the following effects. (1) Effects corresponding to the first to fourth aspects: in a thin film transistor in which impurity ions are implanted into a semiconductor layer to form an n-type contact layer, a conductive region below an edge portion of a channel protective film caused by ion doping is completely removed. And
The feature is to solve the problem of the leak current generated between the source and the drain. As a result, good transistor characteristics having better leakage characteristics than the conventional manufacturing method are realized. (2) Effects corresponding to claim 1: a gate electrode formed on a transparent insulating substrate, a first insulating film formed to cover the gate electrode, and a gate electrode formed on the first insulating film. Using the amorphous semiconductor layer or the microcrystalline semiconductor layer and the gate electrode as a mask, patterning a second insulating film formed on the semiconductor in a self-aligned manner with the gate electrode;
The semiconductor layer is doped with impurities using the resist pattern of the insulating film or the resist pattern of the second insulating film as a mask to form an n + layer. An edge of the channel protective film in a region where impurities are ion-implanted into the semiconductor layer below the second insulating film;
Since the conductive region in the lower layer is completely removed and the portion connected between the source and the drain is cut, leakage current of the transistor can be prevented. (3) An effect corresponding to claim 2: an amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate;
A first insulating film formed so as to cover the semiconductor layer, a gate electrode formed over the first insulating film, and a gate electrode or a resist pattern of the gate electrode as a mask; To form an n + layer. A region under the edge portion of the channel protective film in a region where impurities are ion-implanted into the semiconductor layer under the gate electrode;
Since the conductive region is completely removed and the portion connected between the source and the drain is cut off, the leakage current of the transistor can be prevented. (4) An effect corresponding to the third aspect: a gate electrode formed on a transparent insulating substrate, a first insulating film formed so as to cover the gate electrode, and an amorphous film formed on the first insulating film. Forming a crystalline semiconductor layer or a microcrystalline semiconductor layer and a second insulating film, and patterning the second insulating film formed on the semiconductor layer in a self-aligned manner with the gate electrode using the gate electrode as a mask Using the second insulating film or a resist pattern of the second insulating film as a mask, doping impurities into the semiconductor layer to form an n + layer, and forming a n + layer on the semiconductor layer below the second insulating film. The conductive region under the edge portion of the channel protective film in the region into which the impurities are ion-implanted.
A step of completely removing the substrate and cutting a portion connected between the source and the drain, thereby preventing a leakage current generated between the source and the drain and realizing excellent transistor characteristics having excellent leakage characteristics. (5) An effect corresponding to claim 4: a step of forming an amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate, and a first step formed to cover the semiconductor layer.
Forming an insulating film, forming a gate electrode on the first insulating film, using the gate electrode or a resist pattern on the gate electrode as a mask, doping impurities into the semiconductor, and n + A step of forming a layer and a step of cutting a portion connected between the source and the drain in a region in which impurities are ion-implanted into the semiconductor layer below the gate electrode, so that a leak generated between the source and the drain is formed. Current can be prevented, and good transistor characteristics with excellent leakage characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a thin film transistor according to the present invention.

FIG. 2 is a plan view of FIG.

FIG. 3 is a configuration diagram for explaining another embodiment of a thin film transistor according to the present invention.

FIG. 4 is a configuration diagram for explaining still another embodiment of the thin film transistor according to the present invention.

FIG. 5 is a configuration diagram of a conventional thin film transistor.

FIG. 6 is a diagram showing an edge portion of a conventional channel protective film.

FIG. 7 is a plan view of FIG. 5;

[Explanation of symbols]

101: insulating substrate, 102: base coat insulating film, 10
3: Tantalum thin film, 104: anodized film, 105: Si
₃ N ₄ film, 106: semiconductor film, 107: Si ₃ N ₄ film, 10
8 n + silicon layer, 109 conductive layer region, 110 source / drain electrode, 111 pixel electrode (indium oxide transparent conductive film: ITO), 121 insulating substrate, 122
n + semiconductor layer, 123 ... semiconductor layer, 124 ... first insulating film, 125 ... gate electrode, 126 ... n + layer (gap layer).

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-62-54471 (JP, A) JP-A-6-196701 (JP, A) JP-A-1-253965 (JP, A) JP-A-4- 350943 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (4)

(57) [Claims] A gate electrode formed on a transparent insulating substrate; a first insulating film formed to cover the gate electrode; and an amorphous semiconductor layer formed on the first insulating film. Alternatively, using the microcrystalline semiconductor layer and the gate electrode as a mask, the second insulating film formed over the semiconductor layer is patterned in a self-aligned manner with the gate electrode, and the second insulating film or the second insulating film is formed. A thin film transistor having an inverted staggered structure in which an impurity is doped into the semiconductor layer using a resist pattern of the film as a mask to form an n + layer;
Of the regions where impurities are ion-implanted into the semiconductor layer below the insulating film, the conductive region below the edge of the channel protective film is completely completed.
A thin film transistor which is completely removed and a portion connected between a source and a drain is cut. 2. An amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate, a first insulating film formed so as to cover the semiconductor layer, and a first insulating film formed on the first insulating film. A positive staggered or top-gate thin film transistor, wherein an n + layer is formed by doping impurities on the semiconductor layer using the gate electrode or the resist pattern of the gate electrode as a mask, Of the regions in which impurities are ion-implanted into the semiconductor layer under the electrode, the conductive region under the edge of the channel protective film is completed.
A thin film transistor which is completely removed and a portion connected between a source and a drain is cut. 3. A thin film transistor having an inverted staggered structure, comprising: a gate electrode formed on a transparent insulating substrate;
A first insulating film formed so as to cover the gate electrode;
Forming an amorphous semiconductor layer or a microcrystalline semiconductor layer and a second insulating film over the first insulating film; and forming a second insulating film over the semiconductor layer using the gate electrode as a mask. Patterning in a self-aligned manner with the gate electrode;
Doping an impurity into the semiconductor layer using the second insulating film or a resist pattern of the second insulating film as a mask,
forming an n + layer; and holding a channel in a region in which impurities are ion-implanted into the semiconductor layer below the second insulating film.
Completely removing the conductive region under the edge portion of the protective film and cutting a portion connected between the source and the drain. 4. A step of forming an amorphous or microcrystalline or polycrystalline semiconductor layer formed on a transparent insulating substrate in a positive staggered or top gate thin film transistor, and a step of forming a semiconductor layer covering the semiconductor layer. Forming a first insulating film, forming a gate electrode on the first insulating film, and doping impurities on the semiconductor layer using the gate electrode or a resist pattern on the gate electrode as a mask. , An n + layer, and a step of cutting a portion connected between a source and a drain in a region in which impurities are ion-implanted into the semiconductor layer below the gate electrode. Production method.