JP2716035B2 - Thin film field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film field effect transistor.

[0002]

2. Description of the Related Art Conventionally, a thin film field effect transistor (hereinafter, referred to as a TFT) described in Japanese Patent Application Laid-Open No. Hei 3-4566, "Thin Film Field Effect Transistor and Manufacturing Method Thereof" is known. FIG. 2 is a sectional view showing the TFT and a method for manufacturing the TFT. In the figure, 1 is a transparent insulating film such as glass, 2 is a gate electrode, 3 is a gate insulating film, 4 is an i-type amorphous silicon layer (i
5c is a protective insulating film having a low hydrofluoric acid resistance, 5d is a protective insulating film having a high hydrofluoric acid resistance, and 6 is a metal silicide layer (source / source).
A part of the drain electrode), 7 is a source / drain electrode, 8
Is an n-layer or a p-layer.

This TFT has a gate electrode 2 made of a conductive material such as a metal or a silicide thereof on a transparent insulating substrate 1 made of glass or the like as shown in FIG. A gate insulating film 3 made of an insulator and an i-type amorphous silicon film (i-layer) 4;
Further, a protective insulating film 5d is formed on the i-layer 4 immediately above the gate electrode 2 in a self-aligned pattern with respect to the gate electrode 2 by a back surface exposure process using the gate electrode 2 as a photomask. Phosphorus ions (P) may be implanted (mass separation type impurity ion addition method) or ion doping method (non-mass separation type impurity ion addition method).
⁺ ) And an impurity semiconductor layer of an n-type or p-type amorphous silicon layer (n-layer or p-layer) 8 formed by adding impurity ions such as boron ions (B ⁺ ) and metal. Alternatively, it has a structure having a source / drain electrode 7 made of a conductive material such as silicide.

In a TFT having such a structure, an n-layer or a p-layer 8 is formed by ion implantation or ion doping, followed by formation of a metal silicide layer 6, and a source / electrode having the metal silicide layer 6 as a part of an electrode. Since the formation of the drain electrode 7 can be performed using the protective insulating film 5d formed in a self-aligned manner with respect to the gate electrode 2 by the back exposure process using the gate electrode 2 as a photomask, the source / drain electrode 7 and the gate electrode 2 are formed. The parasitic point between them can be extremely reduced. Therefore, this TFT
Is an active matrix type liquid crystal display (AM
When used as a pixel switching element of an LCD, a low parasitic capacitance stabilizes the pixel potential, suppresses burn-in and luminance unevenness due to field-through, and achieves good image display.

[0005]

However, in the conventional method for manufacturing a TFT, when the metal silicide layer 6 is formed on the n-layer or the p-layer 8 formed by the ion implantation method or the ion doping method, a TFT array substrate is not provided. (Hereinafter referred to as a sample) was once taken out of the ion implantation apparatus or ion doping apparatus into the atmosphere, and then the sample was introduced into a sputtering apparatus to form a metal film. After ion implantation or ion doping, the surface of the n-layer or p-layer 8 is in a state where a large amount of defects (dangling bonds) are generated due to incident ions and easily bonded to oxygen in the atmosphere. When taken out, a natural oxide film is quickly formed on the surface of the n-layer or the p-layer 8. When this natural oxide film is present, the alloy reaction at the interface between the n-layer or p-layer 8 and the metal film, which proceeds simultaneously with the formation of the metal film, does not progress at all, and the impurity semiconductor layer /
There is a problem that the metal silicide layer 6 cannot be formed at the metal film interface. For this reason, the natural oxide film is removed with hydrofluoric acid, and the surface of the n-layer or p-layer 8 in which a large amount of defects are generated by incident ions is stabilized with hydrogen atoms, and then a metal film is formed thereon immediately. It is necessary to form the metal silicide layer 6 at the interface between the impurity semiconductor layer and the metal film by an alloy reaction between the amorphous silicon and the metal.

In the conventional manufacturing method, the protective insulating film is etched by the hydrofluoric acid during the step of removing the natural oxide film by the hydrofluoric acid, and the pattern is reduced. The metal silicide layer 6 is located inside the gate electrode 2 more than the p layer 8.
Is formed, whereby the metal silicide layer 6 and the amorphous silicon layer 4 other than the n-layer or the p-layer 8 come into contact with each other. There has been a problem that a hole current flows in a region other than the p layer 8 and an OFF current of the TFT increases.

In order to solve this problem, the protective insulating film 5c, which has been used as a mask for incident ions at the time of ion implantation or ion doping, is once removed,
It is necessary to form a new protective insulating film 5d having a high resistance to hydrofluoric acid again, resulting in a problem that the number of manufacturing steps is increased.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems, to realize a simplified TFT manufacturing process, and to improve the throughput and cost of products using the TFT.
An object of the present invention is to provide an FT structure.

[0009]

The thin film field effect transistor of the present invention has a gate electrode made of a conductive material on a transparent insulating substrate, and a first electrode on the gate electrode and the transparent insulating substrate.
An insulating film, a semiconductor film over the first insulating film,
A second insulating film on the body film and on the gate electrode;
And located on the semiconductor film and away from the end of the second insulating film.
A metal silicide layer on the
Away from the end of the metal silicide layer on the second insulating film side
A source / drain electrode made of a conductive material at a position,
The source in the semiconductor film, from the end of the second insulating film
/ The second insulating film is formed in a region up to the end of the drain electrode.
N-type implanted using the source / drain electrodes as a mask
Alternatively, the semiconductor device includes a p-type impurity semiconductor layer .

After a protective insulating film 5a is formed in a self-aligned manner with respect to the gate electrode by a back surface exposure step, a source / drain region located on both sides of the protective insulating film 5a has a metal silicide layer as a part of the electrode. / Drain electrode is formed in self-alignment with the protective insulating film 5a. Thereafter, the pattern width of the protective insulating film 5a is slightly reduced to the inside of the gate electrode with a hydrofluoric acid solution, and then n is ion-implanted or ion-doped using the protective insulating film 5a as a mask.
By forming the layer or the p-layer slightly inside the gate electrode than the metal silicide electrode, the number of manufacturing steps can be reduced as compared with the conventional TFT manufacturing step, and as a result, high throughput and low cost of the manufacturing step can be realized. . Further, since the n layer or the p layer can be constantly formed inside the gate electrode rather than the metal silicide electrode portion,
The metal silicide electrode portion does not come into contact with the i-layer portion other than the n-layer or the p-layer, thereby preventing an increase in the OFF current of the TFT. Further, since the formation of the metal silicide layer can be performed on the surface of the i-layer which is very stable, the formation of a good metal silicide layer can be constantly performed. Therefore, it is not necessary to form the protective insulating films 5c and 5d twice by the conventional two back exposure steps, and as a result, the number of manufacturing steps can be reduced as compared with the conventional case. Moreover, a good metal silicide layer can be formed with good reproducibility.

Further, as a secondary effect, an n-layer or a p-layer is formed by ion implantation or ion doping after forming a metal silicide layer on the surface of the i-layer. Due to the effect, promotion of reduction in resistance of the metal silicide layer can be expected, and formation of a good metal silicide layer having lower resistance can be expected.

By the above operation, it is possible to achieve a higher throughput and lower cost of the process than the conventional TFT manufacturing process, and to obtain a TFT having good switching characteristics.

[0013]

FIG. 1 shows an embodiment of the present invention. The TFT shown in FIG. 1 is manufactured through the following steps.

First, chromium (Cr) is placed on a glass substrate 1.
The gate electrode 2 is patterned with a thickness of 50 nm. A gate insulating film 3 made of a silicon nitride film, an i-type amorphous silicon film (i layer) 4, and a protective insulating film 5a made of a silicon nitride film are formed thereon at 300 nm and 1 nm, respectively.
Films are formed to a thickness of 00 nm and 200 nm (FIG. 1)
(A)).

Next, a protective insulating film 5a used as a mask for incident ions at the time of forming the n-layer 8 by ion implantation on the i-layer 4 immediately above the gate electrode 2 is formed by a back exposure process using the gate electrode 2 as a photomask. The electrode 2 is patterned in a self-aligned manner. 0.005 for patterning
This is performed by wet etching using a hydrofluoric acid solution having a concentration of 10% (FIG. 1B). The thickness of the protective insulating film 5a is determined by the type of impurity ions to be added and the acceleration energy conditions. Here, when an ion doping method is used instead of an ion implantation method in which a hydride doping gas is plasma-decomposed and used as an ion source instead of an ion implantation method, the impurity ions that can be controlled at the same time as the target valence electron controllable impurity ions are used. Hydrogen ions added (H ⁺ )
Since the ion implantation range is large, the thickness of the protective insulating film 5a must be set in consideration of the range of H ⁺ . However, here, in order to avoid complicated description, only the ion implantation method will be described as an example of a method of adding impurity ions.

The sample manufactured up to the above-mentioned state is thereafter introduced into a sputtering apparatus, and a metal film is formed with a thickness of 50 nm. At this time, since the protective insulating film 5a on the surface of the i-layer 4 has been patterned by the hydrofluoric acid solution, it is in a very stable state, and there is no need to perform another natural oxide film removal treatment with hydrofluoric acid. Although a good metal silicide layer 6 can be formed in this state, a lower resistance metal silicide layer can be formed by performing a surface treatment with a hydrofluoric acid solution. A metal film is formed by sputtering, and a metal silicide layer 6 is formed at the interface between the metal film and the amorphous silicon layer by an alloying reaction at the interface between the metal film and the amorphous silicon layer. A source / drain electrode 7 is formed as a part (FIG. 1C).

Next, the pattern of the protective insulating film 5a is reduced by about 100 nm on both sides with a 0.005% hydrofluoric acid solution (FIG. 1 (d)), and the protective insulating film 5a is used as a mask for incident ions. Add impurity ions to
An n-layer 8 is formed in the source / drain region (FIG. 1)
(E)). The ion implantation conditions at this time are shown below. ◎ Ion implantation conditions Ion species: phosphorus ions (P ⁺ ) Acceleration energy: 30 keV Dose: 3 × 10 ¹⁵ dose / cm ² or more The metal silicide source / drain electrodes formed in a self-aligned manner with respect to the protective insulating film 5a. The i-layer 4 below 6 is converted into an n-layer. At this time, the pattern width of the protective insulating film 5a used as a mask for incident ions during ion implantation is smaller than when the metal silicide electrode 6 is formed. As a result, the n-layer 8 is larger than the metal silicide electrode 6 part. It is formed on the i-layer 4 inside the gate electrode 2 by about 100 nm. Therefore, the metal silicide electrode 6 and the i-layer 4 other than the n-layer 8 do not come into contact with each other, and the O
An increase in FF current can be prevented, and a TFT having good switching characteristics can be obtained.

In the conventional method, since the metal silicide layer 6 is formed after the ion implantation, a large number of defects occur and the surface of the n-layer 8 on which the natural oxide film is formed is stabilized with hydrogen atoms by hydrofluoric acid treatment. Had to be done. But,
According to the method of the present invention, after the protective insulating film 5a is patterned with hydrofluoric acid, the metal silicide layer 6 is formed first, so that a good metal silicide layer 6 is formed on the surface of the i-layer 4 in a stabilized state. It can be carried out. Further, since the patterning of the protective insulating film 5a which is first patterned is reduced by using hydrofluoric acid, the protective insulating film 5a, which has been conventionally divided into two steps, can be formed only once and the number of manufacturing steps can be greatly reduced. . Moreover, the metal silicide electrode 6 and the n-layer 8
Contact with the i-layer 4 other than the
Can be prevented from increasing, and a TFT having good switching characteristics can be obtained.

Finally, a final insulating protective film 5b for protecting the entire sample is formed with a thickness of 200 nm,
A contact hole is formed in the drain electrode 7 (FIG. 1F).

By the above manufacturing steps, the number of manufacturing steps can be significantly reduced as compared with the conventional manufacturing method, and high throughput and low cost of the manufacturing steps can be realized.

[0021]

According to the present invention, the step of forming the protective insulating film (including the step of forming the protective insulating film and the step of exposing the back surface associated therewith) can be performed only once, so that the number of TFT manufacturing steps can be greatly reduced. High throughput and low cost can be realized. Further, since the formation of the metal silicide layer is always performed on the amorphous silicon layer in a stabilized state, it is possible to constantly form a good metal silicide layer. In addition, since the source / drain regions can be formed steadily inside the gate electrode rather than the metal silicide electrode portion, the hole blocking characteristics are good, that is, OFF.
A TFT having a small leakage current and good switching characteristics can be supplied over a large area with good uniformity and constantly.

As a secondary effect, the impurity semiconductor layer is formed by ion implantation or ion doping after forming the metal silicide layer on the surface of the i-layer. Promotion of lowering the resistance of the silicide layer can be expected, and formation of a good metal silicide layer having lower resistance can be expected.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a conventional thin film field effect transistor and a method for manufacturing the same.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 gate electrode 3 gate insulating film 4 i-type amorphous silicon layer (i layer) 5a protective insulating film 5b final protective insulating film 5c protective insulating film with low hydrofluoric acid resistance 5d protective insulating film with high hydrofluoric acid resistance 6 Metal silicide layer (part of source / drain electrode) 7 Source / drain electrode 8 N-type amorphous silicon layer (N layer)

Claims (1)

(57) [Claims] 1. A has a gate electrode made of conductive material on a transparent insulating substrate, the gate electrode and the transparent insulating substrate
A first insulating film, and a semiconductor film on the first insulating film;
And on the semiconductor film and on the gate electrode
A second insulating film on the semiconductor film and the second insulating film;
Metal silicide layer at a position distant from the insulating film edge
And the second insulating film on the metal silicide layer and
Conductive material at a position away from the end of the metal silicide layer
A semiconductor film having source / drain electrodes made of
The source / drain from the end of the second insulating film.
The second insulating film and the source are formed in the region up to the end of the rain electrode.
N-type implanted with source / drain electrodes as masks
Or a p-type impurity semiconductor layer .