JP2630195B2 - Thin film field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a thin film field effect transistor (hereinafter, referred to as a TFT) described in Japanese Patent Application Laid-Open No. Hei 3-4566, "Thin Film Field Effect Transistor and Manufacturing Method Thereof" is known. FIG. 6 is a cross-sectional view showing the TFT and a method for manufacturing the TFT. In the figure, 1 is a transparent insulating film such as glass, 2 is a gate electrode, 3 is a gate insulating film, 4 is an i-type amorphous silicon layer (i
5c is a protective insulating film having a low hydrofluoric acid resistance, 5d is a protective insulating film having a high hydrofluoric acid resistance, and 6 is a metal silicide layer (source / source).
A part of the drain electrode), 7 is a source / drain electrode, 8
Is an n-layer or a p-layer.

This TFT has a gate electrode 2 made of a conductive material such as a metal or a silicide thereof on a transparent insulating substrate 1 made of glass or the like as shown in FIG. A gate insulating film 3 made of an insulator and an i-type amorphous silicon film (i-layer) 4;
Further, a protective insulating film 5d is formed on the i-layer 4 immediately above the gate electrode 2 in a self-aligned pattern with respect to the gate electrode 2 by a back surface exposure process using the gate electrode 2 as a photomask. Phosphorus ions (P) may be implanted (mass separation type impurity ion addition method) or ion doping method (non-mass separation type impurity ion addition method).
⁺ ) And an impurity semiconductor layer of an n-type or p-type amorphous silicon layer (n-layer or p-layer) 8 formed by adding impurity ions such as boron ions (B ⁺ ) and metal. Alternatively, it has a structure having a source / drain electrode 7 made of a conductive material such as silicide.

In a TFT having such a structure, an n-layer or a p-layer 8 is formed by ion implantation or ion doping, followed by formation of a metal silicide layer 6, and a source / electrode having the metal silicide layer 6 as a part of an electrode. Since the formation of the drain electrode 7 can be performed using the protective insulating film 5d formed in a self-aligned manner with respect to the gate electrode 2 by the back exposure process using the gate electrode 2 as a photomask, the source / drain electrode 7 and the gate electrode 2 are formed. The parasitic point between them can be extremely reduced. Therefore, this TFT
Is an active matrix type liquid crystal display (AM
When used as a pixel switching element of an LCD, a low parasitic capacitance stabilizes the pixel potential, suppresses burn-in and luminance unevenness due to field-through, and achieves good image display.

[0005]

However, in the conventional method for manufacturing a TFT, when the metal silicide layer 6 is formed on the n-layer or the p-layer 8 formed by the ion implantation method or the ion doping method, a TFT array substrate is not provided. (Hereinafter referred to as a sample) was once taken out of the ion implantation apparatus or ion doping apparatus into the atmosphere, and then the sample was introduced into a sputtering apparatus to form a metal film. After ion implantation or ion doping, the surface of the n-layer or p-layer 8 is in a state where a large amount of defects (dangling bonds) are generated due to incident ions and easily bonded to oxygen in the atmosphere. When taken out, a natural oxide film is quickly formed on the surface of the n-layer or the p-layer 8. When this natural oxide film is present, the alloy reaction at the interface between the n-layer or p-layer 8 and the metal film, which proceeds simultaneously with the formation of the metal film, does not progress at all, and the impurity semiconductor layer /
There is a problem that the metal silicide layer 6 cannot be formed at the metal film interface. For this reason, the natural oxide film is removed with hydrofluoric acid, and the surface of the n-layer or p-layer 8 in which a large amount of defects are generated by incident ions is stabilized with hydrogen atoms, and then a metal film is formed thereon immediately. It is necessary to form the metal silicide layer 6 at the interface between the impurity semiconductor layer and the metal film by an alloy reaction between the amorphous silicon and the metal.

In the conventional manufacturing method, the protective insulating film is etched by the hydrofluoric acid during the step of removing the natural oxide film by the hydrofluoric acid, and the pattern is reduced. The metal silicide layer 6 is located inside the gate electrode 2 more than the p layer 8.
Is formed, whereby the metal silicide layer 6 and the amorphous silicon layer 4 other than the n-layer or the p-layer 8 come into contact with each other. There has been a problem that a hole current flows in a region other than the p layer 8 and an OFF current of the TFT increases.

In order to solve this problem, the protective insulating film 5c, which has been used as a mask for incident ions at the time of ion implantation or ion doping, is once removed,
It is necessary to form a new protective insulating film 5d having a high resistance to hydrofluoric acid again, resulting in a problem that the number of manufacturing steps is increased.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems, to realize a simplified TFT manufacturing process, and to improve the throughput and cost of products using the TFT.
An object of the present invention is to provide an FT structure and a manufacturing method thereof.

[0009]

According to the method of manufacturing a thin film field effect transistor of the present invention, a step of patterning a gate electrode made of a conductive material on a transparent insulating substrate is performed, and thereafter, a step of forming an insulating film, a semiconductor film, and an insulating film. Forming a layer, then patterning the uppermost insulating film in a self-aligned manner with respect to the gate electrode by a backside exposure step using the gate electrode as a photomask, and then forming a metal film Patterning a source / drain electrode in a source / drain region; thereafter, reducing the pattern of the uppermost insulating film slightly inside the gate electrode with hydrofluoric acid; Is used as a mask for incident ions, and impurity ions are added to a semiconductor sample to form an n-type or p-type impurity semiconductor layer. Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in a self-aligning manner with the uppermost insulating film in which the pattern is reduced by adding impurity ions into the semiconductor film below the source / drain electrodes; And a step of performing

According to the method of manufacturing a thin film field effect transistor of the present invention, a step of patterning a gate electrode made of a conductive material on a transparent insulating substrate is followed by an insulating film, a semiconductor film, an insulating film having low hydrofluoric acid resistance, A step of forming four layers of a highly acidic film, and thereafter, an uppermost film obtained by combining the two layers of the insulating film with low hydrofluoric acid resistance and the film with high hydrofluoric acid resistance, using the gate electrode as a photomask. A step of patterning the gate electrode in a self-aligned manner by a backside exposure step, a step of forming a metal film and then patterning the source / drain electrodes in source / drain regions, and thereafter, the step of lowering the resistance to hydrofluoric acid A step of reducing the pattern of the insulating film slightly inside the gate electrode with hydrofluoric acid, and thereafter, using the uppermost insulating film as a mask for incident ions, Is added to a semiconductor sample to form an n-type or p-type impurity semiconductor layer, and impurity ions are added to the semiconductor film below the source / drain electrodes to reduce the pattern. Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in a self-aligned manner with the film. The film having a high resistance to hydrofluoric acid may be a nitride film, an oxide film, or an organic polymer film.

According to the method of manufacturing a thin film field effect transistor of the present invention, a step of patterning a gate electrode made of a conductive material on a transparent insulating substrate, a step of forming two layers of an insulating film and a semiconductor film, and Patterning the organic polymer film on the semiconductor film in a self-aligned manner with respect to the gate electrode by a back surface exposure process using the gate electrode as a photomask; Forming a film and patterning the source / drain electrodes in the source / drain regions; and thereafter, removing the organic polymer film and renewing the organic polymer film on the semiconductor film by the back exposure step. A step of patterning the pattern by reducing the pattern slightly inside the gate electrode than the second organic polymer film, and thereafter, the second organic polymer film Used as a mask for incident ions,
A second organic method in which the pattern is reduced by adding impurity ions to the semiconductor film below the source / drain electrodes by adding impurity ions to the semiconductor sample to form an n-type or p-type impurity semiconductor layer. Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in self-alignment with the polymer film.

According to the method of manufacturing a thin film field effect transistor of the present invention, a step of patterning a gate electrode made of a conductive material on a transparent insulating substrate, a step of forming two layers of an insulating film and a semiconductor film, and Patterning the organic polymer film on the semiconductor film in a self-aligned manner with respect to the gate electrode by a back exposure process using the gate electrode as a photomask, and thereafter exposing the organic polymer film without exposing the organic polymer film to light. Depositing a metal film while leaving it, patterning source / drain electrodes in source / drain regions, and thereafter reducing the pattern slightly inside the gate electrode without exposing the organic polymer film to light. Then, using the organic polymer film obtained by reducing the pattern as a mask for incident ions, impurity ions are applied to the semiconductor sample. The second organic polymer film, in which the pattern is reduced by adding impurity ions into the semiconductor film below the source / drain electrodes by a method of forming an n-type or p-type impurity semiconductor layer, is used. Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in a consistent manner.

In the thin film field effect transistor of the present invention, a gate electrode made of a conductive material is formed on a transparent insulating substrate.
A first insulating film and a semiconductor film above the gate electrode;
Are sequentially formed, and the half corresponding to the gate electrode position is formed.
A second insulating film is formed on the conductive film, and the second insulating film is formed on the conductive film;
A metal silicide layer on the semiconductor film located on both sides of
Source / drain made of electrically connected conductive material
An electrode is formed, and n is formed below the source / drain electrode.
Thin film on which a p-type or p-type impurity semiconductor layer is formed
In the field effect transistor, the second insulating film is resistant to
A layer having a low hydrofluoric acid resistance is provided below, and a layer having a high hydrofluoric acid resistance is provided as described above.
A two-layer structure provided only above the low-acid layer, and
The width of the layer having low hydrofluoric acid resistance is smaller than the width of the gate electrode.
And the end of the metal silicide layer is resistant to the hydrofluoric acid.
Away from the edge of the lower layer and the impurity semiconductor layer is
In the semiconductor film including the lower part of the edge of the layer having low resistance to hydrofluoric acid,
Characterized in that it is formed.

[0014]

[0015]

After forming a source / drain electrode having a metal silicide layer as a part of the electrode in the source / drain region of the TFT in a self-aligned manner with respect to the gate electrode, an n layer or a p layer is formed by ion implantation or ion doping. Is formed slightly inside the gate electrode than the metal silicide electrode, the number of manufacturing steps can be reduced as compared with the conventional TFT manufacturing process, and as a result, the throughput of the manufacturing process can be increased.
Cost reduction can be realized. Further, since the n-layer or the p-layer can be formed constantly on the inner side of the gate electrode than the metal silicide electrode portion, the contact between the metal silicide electrode portion and the i-layer portion other than the n-layer or the p-layer can be prevented. As a result, an increase in the OFF current of the TFT can be prevented.
Further, since the formation of the metal silicide layer can be performed on the surface of the i-layer which is very stable, the formation of a good metal silicide layer can be constantly performed. Therefore, a metal silicide layer is not formed on a rough surface after ion implantation or ion doping (a surface on which a large number of defects are generated and a natural oxide film is formed), and a stable state is maintained. Since a metal silicide layer can be formed by forming a metal film on the surface of the i-layer, there is no need to perform another natural oxide film removal treatment by hydrofluoric acid treatment, and the number of manufacturing steps can be reduced as compared with the conventional case. Moreover, a good metal silicide layer can be formed with good reproducibility.

Further, as a secondary effect, an n-layer or a p-layer is formed by ion implantation or ion doping after forming a metal silicide layer on the surface of the i-layer. Due to the effect, promotion of reduction in resistance of the metal silicide layer can be expected, and formation of a good metal silicide layer having lower resistance can be expected.

By the above-described operation, it is possible to achieve a higher throughput and lower cost in the process than in the conventional TFT manufacturing process, and to obtain a TFT having good switching characteristics.

[0018]

FIG. 1 shows an embodiment of the present invention. The TFT shown in FIG. 1 is manufactured through the following steps.

First, chromium (Cr) is placed on a glass substrate 1.
The gate electrode 2 is patterned with a thickness of 50 nm. A gate insulating film 3 made of a silicon nitride film, an i-type amorphous silicon film (i layer) 4, and a protective insulating film 5a made of a silicon nitride film are formed thereon at 300 nm and 1 nm, respectively.
Films are formed to a thickness of 00 nm and 200 nm (FIG. 1)
(A)).

Next, a protective insulating film 5a used as a mask for incident ions when the n-layer 8 is formed by ion implantation on the i-layer 4 immediately above the gate electrode 2 is gated by a back exposure process using the gate electrode 2 as a photomask. The electrode 2 is patterned in a self-aligned manner. 0.005 for patterning
This is performed by wet etching using a hydrofluoric acid solution having a concentration of 10% (FIG. 1B). The thickness of the protective insulating film 5a is determined by the type of impurity ions to be added and the acceleration energy conditions. Here, when an ion doping method is used instead of an ion implantation method in which a hydride doping gas is plasma-decomposed and used as an ion source instead of an ion implantation method, the impurity ions that can be controlled at the same time as the target valence electron controllable impurity ions are used. Hydrogen ions added (H ⁺ )
Since the ion implantation range is large, the thickness of the protective insulating film 5a must be set in consideration of the range of H ⁺ . However, here, in order to avoid complicated description, only the ion implantation method will be described as an example of a method of adding impurity ions.

The sample manufactured up to the above-described state is thereafter introduced into a sputtering apparatus, and a metal film is formed with a thickness of 50 nm. At this time, since the protective insulating film 5a on the surface of the i-layer 4 has been patterned by the hydrofluoric acid solution, it is in a very stable state, and there is no need to perform another natural oxide film removal treatment with hydrofluoric acid. In this state, a good metal silicide layer 6 can be formed. A metal film is formed by sputtering, and a metal silicide layer 6 is formed at the interface between the metal film and the amorphous silicon layer by an alloying reaction at the interface between the metal film and the amorphous silicon layer. A source / drain electrode 7 is formed as a part (FIG. 1C).

Next, the pattern of the protective insulating film 5a is reduced by about 100 nm on both sides with a 0.005% hydrofluoric acid solution (FIG. 1 (d)), and the protective insulating film 5a is used as a mask for incident ions. Add impurity ions to
An n-layer 8 is formed in the source / drain region (FIG. 1)
(E)). The ion implantation conditions at this time are shown below. ◎ Ion implantation conditions Ion species: phosphorus ions (P ⁺ ) Acceleration energy: 30 keV Dose: 3 × 10 ¹⁵ dose / cm ² or more The metal silicide source / drain electrodes formed in a self-aligned manner with respect to the protective insulating film 5a. The i-layer 4 below 6 is converted into an n-layer. At this time, the pattern width of the protective insulating film 5a used as a mask for incident ions during ion implantation is smaller than when the metal silicide electrode 6 is formed. As a result, the n-layer 8 is larger than the metal silicide electrode 6 part. It is formed on the i-layer 4 inside the gate electrode 2 by about 100 nm. Therefore, the metal silicide electrode 6 and the i-layer 4 other than the n-layer 8 do not come into contact with each other, and the O
An increase in FF current can be prevented, and a TFT having good switching characteristics can be obtained.

In the conventional method, since the metal silicide layer 6 is formed after the ion implantation, a large number of defects are generated, and the surface of the n-layer 8 on which the natural oxide film is formed is stabilized with hydrogen atoms by hydrofluoric acid treatment. Had to be done. But,
According to the method of the present invention, after the protective insulating film 5a is patterned with hydrofluoric acid, the metal silicide layer 6 is formed first, so that a good metal silicide layer 6 is formed on the surface of the i-layer 4 in a stabilized state. It can be carried out. Further, since the patterning of the protective insulating film 5a which is first patterned is reduced by using hydrofluoric acid, the protective insulating film 5a, which has been conventionally divided into two steps, can be formed only once and the number of manufacturing steps can be greatly reduced. . Moreover, the metal silicide electrode 6 and the n-layer 8
Contact with the i-layer 4 other than the
Can be prevented from increasing, and a TFT having good switching characteristics can be obtained.

Finally, a final insulating protective film 5b for protecting the entire sample is formed with a thickness of 200 nm,
A contact hole is formed in the drain electrode 7 (FIG. 1F).

By the above manufacturing steps, the number of manufacturing steps can be greatly reduced as compared with the conventional manufacturing method, and high throughput and low cost of the manufacturing steps can be realized.

FIG. 2 shows another embodiment of the present invention. The TFT shown in FIG. 2 is manufactured through the following steps.

The steps up to the formation of the i-layer 4 are the same as in the embodiment of FIG. The conditions for adding impurity ions are the same, and the protective insulating film is formed of a silicon nitride film. i layer 4
After the film formation, the protective insulating film 5c having a low hydrofluoric acid resistance
After forming the protective insulating film 5d having a high hydrofluoric acid resistance,
A 0 nm film is formed (FIG. 2A).

Then, a lower hydrofluoric acid-resistant protective insulating film 5c and a higher hydrofluoric acid-resistant protective insulating film 5d are formed in a self-aligned manner with respect to the gate electrode 2 by a backside exposure process similar to the embodiment of FIG. The thus formed protective insulating film having a two-layer structure is patterned (FIG. 2B). Subsequent steps are the same as those in the embodiment of FIG. 1, and similar effects can be obtained. In the embodiment of FIG. 1, when the pattern of the protective insulating film 5a is reduced by hydrofluoric acid, the protective insulating film 5a is also etched in the film thickness direction due to isotropic etching peculiar to wet etching, and the protective insulating film 5a becomes thin. That is inevitable. If the thickness of the protective insulating film 5a is too thin, there is a concern that incident ions cannot be sufficiently prevented during ion implantation. In order to avoid this concern, measures such as increasing the thickness of the protective insulating film 5a by an amount corresponding to the etching amount may be taken in advance, but this requires an increase in the film forming time. However, as shown in the embodiment of FIG. 2, the structure of the protective insulating film 5 has a low-fluoric acid-resistant lower structure and a high hydrofluoric acid-resistant structure has a two-layer structure.
The d acts to suppress the isotropic etching of the lower protective insulating film 5c, thereby making it possible to prevent the protective insulating film 5c from becoming thinner as a whole. Therefore, the above-mentioned concern can be avoided without the necessity of making the protective insulating film thicker than necessary.

FIG. 3 shows another embodiment of the present invention. The TFT shown in FIG. 3 is manufactured through the following steps.

The steps up to the formation of the i-layer 4 are the same as in the embodiment of FIG. The conditions for adding impurity ions are the same, and the protective insulating film is formed of a silicon nitride film. i layer 4
After the film formation, a silicon nitride film used as the protective insulating film 5a is formed to a thickness of 200 nm (FIG. 3A). Thereafter, the protective insulating film 5a is patterned in a self-aligned manner with respect to the gate electrode 2 by a back surface exposure process similar to the embodiment of FIG. Conventionally, the resist film 9a used for patterning the protective insulating film 5a was peeled off after the patterning of the protective insulating film 5a, but in the present invention, it is used without being removed. The thickness of the resist is about 1.5 μm (FIG. 3B).

The sample manufactured up to the above-mentioned state is thereafter
A metal film is formed on the protective insulating film 5a with the resist film 9a left. Then, the metal film is patterned to form a source / drain electrode 7 using the metal silicide layer 6 as a part of the electrode (FIG. 3C).

Next, with the resist film 9a left on the protective insulating film 5a, the pattern of the protective insulating film 5a is reduced by about 100 nm on both sides with a 0.005% hydrofluoric acid solution (FIG. 3 (d)). )), The protective insulating film 5a and the resist film 9a are used as masks for incident ions during ion implantation, and impurity ions are added to the sample to form the n-layer 8 (FIG. 3E). Thereafter, the resist film 9a on the protective insulating film 5a is peeled off. At this time, since the resist film 9a is hardly peeled off due to the influence of incident ions, it is necessary to appropriately perform an oxygen (O ₂ ) ashing process or the like as needed. Subsequent steps are the same as in the embodiment of FIG.

In the embodiment of FIG. 2, problems such as thinning of the protective insulating films 5c and 5d could be prevented.
Since impurity ions are also implanted into the protective insulating films 5c and 5d, there is a concern about a problem of electrical instability such as the presence of a current via a level due to the impurities. However, by diverting the resist film 9a used for patterning the protective insulating film 5a, it is possible not only to prevent the protective insulating film 5a from being thinned but also to prevent impurity ions from being implanted into the protective insulating film 5a. Thus, the concern of electrical instability due to the implantation of impurity ions into the protective insulating film 5a can be eliminated.

FIG. 4 shows another embodiment of the present invention. The TFT shown in FIG. 4 is manufactured through the following steps.

The steps up to the formation of the i-layer 4 are the same as in the embodiment of FIG. The conditions for adding impurity ions are the same, and the protective insulating film is formed of a silicon nitride film. i layer 4
After the formation, a resist film 9a having a thickness of about 1.5 μm is spin-coated on the surface of the i-layer 4 (FIG. 4A). Then, the resist film 9a is patterned in a self-aligning manner by a back exposure process using the gate electrode 2 as a photomask (FIG. 4).
(B)). Thereafter, a metal film is formed by sputtering, a metal silicide layer 6 is formed at the interface between the metal film and the amorphous silicon layer, and then the metal film is patterned to use the metal silicide layer 6 as a part of an electrode. / Drain electrode 7 is formed (FIG. 4C). At this time, as described above, the surface of the i-layer 4 is sufficiently stable without performing hydrofluoric acid treatment,
A good metal silicide layer 6 can be formed.

Next, after the resist film 9a is peeled off once, the resist film 9b is spin-coated again with a thickness of 1.5 μm (FIG. 4D). Then, the resist film 9b is again patterned in a self-aligned manner with respect to the gate electrode by the back surface exposure step. When patterning (developing) the resist film 9b, the developing time is set to be slightly longer and the resist film 9b is formed.
Is formed on the inside of the gate electrode 2 by reducing the pattern by about 100 nm from the resist film 9a formed the first time (FIG. 4E). Using the resist film 9b as a mask for incident ions at the time of ion implantation, P ⁺ is added to the sample, and the lower portion of the metal silicide source / drain electrode 6 is patterned in a self-aligned manner with respect to the first formed resist film 9a. The i-layer 4 is turned into an n-layer (FIG. 4F). At this time, the pattern width of the second resist film 9b used as a mask for ion implantation is smaller than that at the time of forming the metal silicide electrode 6, and as a result, the n-layer 8 is about 100 nm thicker than the metal silicide electrode 6 part. Inside i
Formed on layer 4. Therefore, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

After the formation of the source / drain regions, the resist film 9b used as a mask for ion implantation is hardened as in the embodiment shown in FIG. Therefore, it is preferable to appropriately perform O ₂ ashing to make the resist film 9b easily peelable.

Finally, the resist film 9b is removed, and then a final protective insulating film 5b is formed. Then, a contact hole is formed in the source / drain electrode 7 (FIG. 4).
(H)).

By the above manufacturing steps, the formation of the protective insulating film becomes only the final protective insulating film 5b, so that the film forming steps of each layer can be largely reduced, thereby realizing high throughput and low cost of the TFT manufacturing process. it can. In the manufacturing method of this embodiment, the back surface exposure step for patterning the resist film is increased by one time compared to the above-described three embodiments, but the film formation step has a higher throughput than any vacuum process. High, and the frequency of use of film forming equipment is reduced,
The time required for maintenance of the apparatus, which has been one of the causes of the decrease in the throughput, can be saved, and there are many advantages in the process. Therefore, the TFT manufacturing process can be significantly reduced.

FIG. 5 shows another embodiment of the present invention. The TFT shown in FIG. 5 is manufactured through the following steps.

The steps up to the formation of the i-layer 4 are the same as in the embodiment of FIG. The conditions for adding impurity ions are the same, and the protective insulating film is formed of a silicon nitride film. i layer 4
After the formation, a resist film 9a having a thickness of about 1.5 μm is spin-coated on the surface of the i-layer 4 (FIG. 5A). Then, the resist film 9a is patterned in a self-aligned manner by a back surface exposure process using the gate electrode 2 as a photomask (FIG. 5).
(B)). Thereafter, a metal film is formed by an evaporation method in an environment where the resist film 9a is not exposed to light. As a method of forming the metal film, a sputtering method may be used,
Since the resist film 9a may be exposed to light from a rare gas element (mainly argon: Ar) generated when the target is sputtered, it is safer to use a vapor deposition method for forming the metal film. Seem. However,
If a resist material with low photosensitivity is used, the resist film 9a
It seems that it is possible to reduce the degree of photosensitivity.

After the metal silicide layer 6 is formed at the interface between the metal film and the amorphous silicon layer by an alloying reaction, the metal film is patterned and the source / drain having the metal silicide layer 6 as a part of the electrode is formed. The electrode 7 is formed (FIG. 5
(C)). At this time, as described above, the surface of the i-layer 4 is sufficiently stable without performing the hydrofluoric acid treatment, and a good metal silicide layer 6 can be formed. Until the ion implantation step is completed, all the steps must be performed in an environment where the resist film 9a is not exposed.

Next, the pattern of the resist film 9a is reduced to about 100 nm inside the gate electrode 2 by a developing solution (FIG. 5D). Using this resist film 9a as a mask for incident ions at the time of ion implantation, P ⁺ is added to the sample, and i under the metal silicide source / drain electrode 6 patterned in a self-aligned manner with respect to the resist film 9a formed first. The layer 4 is converted into an n-layer (FIG. 5E). At this time, the pattern width of the resist film 9a used as a mask for ion implantation is naturally smaller than that when the metal silicide electrode 6 is formed. As a result, the n-layer 8 is about 100 nm thicker than the metal silicide electrode 6 part. It is formed on the inner i-layer 4. Therefore, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

After the formation of the source / drain regions, the resist film 9a used as a mask for ion implantation is hardened similarly to the embodiment shown in FIGS. Therefore, it is preferable to appropriately perform O ₂ ashing to make the resist film 9a easily peelable.

Finally, the resist film 9a is removed, and thereafter, a final protective insulating film 5b is formed. Then, a contact hole is formed in the source / drain electrode 7 part. (FIG. 5 (f)).

According to the above manufacturing steps, the protective insulating film is formed not only in the final protective insulating film 5b but also in the backside exposure step only once, so that the number of manufacturing steps can be greatly reduced. Higher throughput and lower cost of the TFT manufacturing process can be realized as compared with the embodiment.

[0047]

According to the present invention, the step of forming the protective insulating film including the final protective insulating film (including the step of forming the protective insulating film and the step of exposing the back surface thereof) can be performed twice or once. The number of manufacturing steps can be greatly reduced, and therefore, high throughput and low cost of the manufacturing steps can be realized. Further, since the formation of the metal silicide layer is always performed on the amorphous silicon layer in a stabilized state, it is possible to constantly form a good metal silicide layer. In addition, since the source / drain regions can be formed steadily inside the gate electrode rather than the metal silicide electrode portion, a TFT having a good hole blocking characteristic, that is, a small OFF leak current, and a good switching characteristic can be formed on a large area. It can be supplied uniformly and constantly.

As a secondary effect, since the impurity semiconductor layer is formed by ion implantation or ion doping after forming the metal silicide layer on the surface of the i-layer, the effect of thermal energy given to the film by incident ions causes Promotion of lowering the resistance of the silicide layer can be expected, and formation of a good metal silicide layer having lower resistance can be expected.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing another embodiment of the present invention.

FIG. 3 is a sectional view showing another embodiment of the present invention.

FIG. 4 is a sectional view showing another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing another embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a conventional thin film field effect transistor and a method for manufacturing the same.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate electrode 3 Gate insulating film 4 i-type amorphous silicon layer (i layer) 5a Protective insulating film 5b Final protective insulating film 5c Protective insulating film with low hydrofluoric acid resistance 5d Protective insulating film with high hydrofluoric acid resistance 6 Metal silicide layer (part of source / drain electrode) 7 Source / drain electrode 8 N-type amorphous silicon layer (N layer) 9a First resist film 9b Second resist film

Claims (5)

(57) [Claims] A step of patterning a gate electrode made of a conductive material on a transparent insulating substrate, a step of forming three layers of an insulating film, a semiconductor film, and an insulating film; and a step of forming the uppermost insulating film. A step of patterning the gate electrode in a self-aligned manner by a backside exposure step using the gate electrode as a photomask, and a step of thereafter forming a metal film and patterning the source / drain electrodes in source / drain regions; Thereafter, a step of reducing the pattern of the uppermost insulating film slightly inside the gate electrode with hydrofluoric acid, and thereafter, adding the impurity ions to the semiconductor sample by using the uppermost insulating film as a mask of incident ions. impurity ions are added to the semiconductor film below the source / drain electrodes by a method of forming an n-type or p-type impurity semiconductor layer; Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in a self-aligned manner with respect to the uppermost insulating film in which the pattern is reduced. Method. 2. A step of patterning a gate electrode made of a conductive material on a transparent insulating substrate, and thereafter forming four layers of an insulating film, a semiconductor film, an insulating film having low resistance to hydrofluoric acid, and a film having high resistance to hydrofluoric acid. And a back exposure step using the gate electrode as a photomask to form an uppermost film obtained by combining the two layers of the low hydrofluoric acid resistant insulating film and the high hydrofluoric acid resistant film with respect to the gate electrode. A step of patterning in a self-aligned manner, and then a step of forming a metal film and patterning source / drain electrodes in source / drain regions;
After that, a step of reducing the pattern of the insulating film having low hydrofluoric acid resistance slightly inside the gate electrode with hydrofluoric acid, and thereafter, using the uppermost insulating film as a mask for incident ions, removing impurity ions from the semiconductor sample To form an n-type or p-type impurity semiconductor layer by adding impurity ions into the semiconductor film below the source / drain electrodes to reduce the pattern, thereby reducing the pattern resistance of the insulating film with low hydrofluoric acid resistance. Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in a self-aligned manner. 3. A step of patterning a gate electrode made of a conductive material on a transparent insulating substrate, a step of forming two layers of an insulating film and a semiconductor film, and thereafter, an organic polymer film on the semiconductor film Patterning the gate electrode in a self-aligned manner by a backside exposure step using the gate electrode as a photomask, and then forming a metal film while leaving the organic polymer film on the source / drain regions. Patterning the source / drain electrodes, and then removing the organic polymer film and re-exposing a new organic polymer film on the semiconductor film again by the back exposure step to be slightly more than the first organic polymer film. Patterning the pattern by reducing the pattern inside the gate electrode, and then using the second organic polymer film as a mask for incident ions, A second organic polymer in which the pattern is reduced by adding impurity ions into the semiconductor film below the source / drain electrodes by a method of forming an n-type or a p-type impurity semiconductor layer by adding GaN to a semiconductor sample. N-type or p-type
Forming a thin-film impurity semiconductor layer. 4. A step of patterning a gate electrode made of a conductive material on a transparent insulating substrate, a step of forming two layers of an insulating film and a semiconductor film, and thereafter, an organic polymer film on the semiconductor film Patterning the gate electrode in a self-aligned manner by a backside exposure step using the gate electrode as a photomask, and then forming a metal film while leaving the organic polymer film on the source / drain regions. Patterning the source / drain electrodes, thereafter reducing the pattern slightly inside the gate electrode without exposing the organic polymer film, and then reducing the pattern by the organic polymer film Is used as a mask for incident ions, and impurity ions are added to a semiconductor sample to form an n-type or p-type impurity semiconductor layer. Forming an n-type or p-type impurity semiconductor layer in the semiconductor film in a self-alignment manner with the organic polymer film reduced in size by adding impurity ions into the semiconductor film below the source / drain electrode; A method of manufacturing a thin-film field-effect transistor. 5. A gate electrode made of a conductive material is formed on a transparent insulating substrate, a first insulating film and a semiconductor film are sequentially formed above the gate electrode, and a first insulating film and a semiconductor film are sequentially formed on the semiconductor film corresponding to the position of the gate electrode. A source / drain electrode made of a conductive material electrically connected to a metal silicide layer is formed on the semiconductor film located on both sides of the second insulating film; In the thin-film field-effect transistor in which an n-type or p-type impurity semiconductor layer is formed below the / drain electrode, the second insulating film has a lower hydrofluoric acid-resistant layer below and a higher hydrofluoric acid-resistant layer. A two-layer structure provided only above the low hydrofluoric acid resistant layer, wherein the width of the low hydrofluoric acid resistant layer is smaller than the width of the gate electrode, and the end of the metal silicide layer is Low acid layer A thin film field effect transistor, wherein the impurity semiconductor layer is formed in the semiconductor film including a portion below an end of the low hydrofluoric acid resistant layer.