JP3358284B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) used as an active element of an active matrix liquid crystal display (AM-LCD).

[0002]

2. Description of the Related Art Generally, a thin film transistor is used as an active element of an active matrix liquid crystal display element or an active element forming a driving circuit. This kind of thin film transistor is generally manufactured by the following manufacturing method.

[0003] First, as shown in FIG.
A gate electrode 102, a gate insulating layer 103 made of silicon nitride, a semiconductor layer 104 made of amorphous silicon, and a blocking layer 105 are sequentially formed on the gate electrode. FIG.
As shown in FIG. 2, a positive photoresist layer 106 is formed on the blocking layer 105 and is exposed from the glass substrate 101 side (back side). At this time, the gate electrode 102 serves as a mask, and only the portion of the photoresist layer 106 corresponding to the gate electrode 102 is not exposed.

The exposed photoresist layer 106 is developed to leave only a portion of the photoresist layer 106 corresponding to the gate electrode 102, as shown in FIG. The remaining photoresist layer 106 is used as a mask and the blocking layer 105 is etched using BHF as an etchant. As shown in FIG. 14, only the portion of the blocking layer 105 corresponding to the gate electrode 102 is etched. Is patterned so as to remain.

As shown in FIG. 14, using the remaining blocking layer 105 as a mask, an impurity is implanted into the semiconductor layer 104 using an ion doping (ion implantation) apparatus to form an n ⁺ region. . After that, the blocking layer 105 is removed by etching.

As shown in FIG. 15, the semiconductor layer 104 is irradiated with an excimer laser to anneal the semiconductor layer 104,
Amorphous silicon is converted to polysilicon and the implanted impurities are activated to form a source region and a drain region. The semiconductor layer 104 is patterned into an element shape, and a device area is processed as shown in FIG. Thereafter, as shown in FIG.
Is formed, and further, the source and drain electrodes 108 are formed to complete the thin film transistor.

[0007]

According to the above manufacturing method, when patterning the blocking layer 105 using BHF, BHF penetrates the gate insulating layer 103 and etches silicon nitride. For this reason, the defect density of the gate insulating layer 103 of the manufactured thin film transistor becomes extremely large, and there are problems such as a decrease in yield and a decrease in breakdown voltage characteristics of the manufactured thin film transistor.

In order to eliminate such a defect, it is conceivable to pattern the blocking layer 105 by dry etching. However, there is a problem that dry etching cannot be used because the selectivity between the semiconductor layer 104 and the gate insulating layer 103 is small.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a thin film transistor having a high yield rate.
Another object of the present invention is to provide a method for manufacturing a thin film transistor capable of manufacturing a thin film transistor having excellent characteristics.

[0010]

In order to achieve the above object, a method of manufacturing a thin film transistor according to a first aspect of the present invention comprises a method for manufacturing a thin film transistor on a substrate, comprising: a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer; A step of sequentially forming a second insulating layer having a different material from the first insulating layer; and patterning the second insulating layer into a predetermined shape by dry etching while protecting the semiconductor layer with the first insulating layer. A dry etching step, a diffusion step of diffusing impurities in the semiconductor layer using the patterned second insulating layer as a mask, a step of patterning the semiconductor layer into a predetermined element shape, and the step of Forming an insulating protective layer on the semiconductor layer; forming a contact hole in the protective layer; and forming a source of the semiconductor layer through the contact hole. Characterized in that it comprises a step of forming a source electrode and a drain electrode connected to the band and the drain region.

For example, the gate insulating layer is formed of silicon nitride, the first insulating layer is formed of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is formed of a thickness of 100 to 200 nm.
nm, formed from silicon nitride and the dry etching process is performed using CF ₄ + O ₂ as a reactive gas.

By forming the second insulating layer in a self-aligned manner with respect to the gate electrode using backside exposure, the channel region of the semiconductor layer can be formed in a self-aligned manner with respect to the gate electrode. The first insulating layer is patterned into, for example, the same shape on the semiconductor layer and remains until completion. Impurities are injected into the semiconductor layer through the first insulating layer. The semiconductor layer after the impurity implantation may be annealed.

Further, according to a method of manufacturing a thin film transistor according to a second aspect of the present invention, a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer, and a material different from the first insulating layer are formed on a substrate. Forming an insulating layer and a photoresist layer, and exposing and developing the photoresist layer from the substrate side to form a photoresist pattern formed in a self-aligned manner with respect to the gate electrode. And using the photoresist pattern as a mask,
By dry-etching the second insulating layer using a reaction gas having a different etching rate for the first and second insulating layers, an insulating layer pattern formed in a self-aligned manner with respect to the gate electrode is formed. Forming, using the insulating layer pattern as a mask, injecting an impurity into the semiconductor layer, patterning the first insulating layer and the semiconductor layer into a device shape, A step of forming an interlayer insulating layer on the insulating layer; and a step of forming an electrode connected to the semiconductor layer via the interlayer insulating layer.

For example, the gate insulating layer is formed from silicon nitride, the semiconductor layer is formed from amorphous silicon, the first insulating layer is formed from silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is formed from silicon oxide. It is formed of silicon nitride having a thickness of 100 to 200 nm. The dry etching process uses CF ₄ + O ₂ as a reaction gas, and the impurity is implanted into the semiconductor layer through the first insulating layer. The semiconductor layer into which the impurities have been implanted may be laser-annealed via the first insulating layer to be poly-crystalline.

[0015]

According to the above structure, according to the method of manufacturing a thin film transistor according to the first and second aspects of the present invention, when patterning the second insulating layer, the semiconductor layer is formed with the second insulating layer. Since the semiconductor layers are protected by the first insulating layers having different etching rates, the semiconductor layers are not damaged. In addition, since the second insulating layer is etched by dry etching, the characteristics of the manufactured thin film transistor are kept good and the yield is increased without damaging the gate insulating layer.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a thin film transistor according to one embodiment of the present invention will be described below with reference to the drawings. The thin film transistor according to this embodiment constitutes a driving circuit of an active matrix type liquid crystal display element.

First, a conductive film made of a light-impermeable conductive material such as aluminum (Al), an aluminum alloy, or chromium is formed on a transparent substrate 1 made of glass, a flexible film, or the like by sputtering, vapor deposition, or the like. It is formed to a thickness of about 60 to 150 nm. Next, this is patterned by using a photolithographic process to form a gate electrode (and a gate wiring connected thereto) 2.

A gate insulating layer 3 made of a silicon nitride film (SiN) or the like is deposited on the entire surface of the transparent substrate 1 by a plasma CVD method or the like to a thickness of about 100 to 300 nm. A semiconductor layer 4 made of amorphous silicon is deposited on the entire surface of the transparent substrate 1 using a plasma CVD method or the like to a thickness of about 20 to 80 nm.

Next, a first blocking layer 11 made of a silicon oxide film (SiO) is deposited using a sputtering device and a plasma CVD device. As will be described later, the first blocking layer 11 has a function of protecting the semiconductor layer 4 when the second blocking layer 12 is dry-etched. On the other hand, in order to inject impurities into the semiconductor layer 4 (FIG. 4) and perform laser annealing (FIG. 5), it is desirable that the thickness be thin. In order to satisfy these contradictory conditions, it is desirable that the first blocking layer 11 be formed to a thickness of 10 to 30 nm, preferably 16 to 24 nm, particularly preferably about 19 to 21 nm.

Next, a second blocking layer 12 made of a silicon nitride film (SiN) is formed using a plasma CVD apparatus.
With a thickness of 50 to 250 nm, preferably a thickness of 100 to 180
nm, particularly preferably about 130 to 150 nm thick. Through the above steps, the structure shown in FIG. 1 is completed.

Next, as shown in FIG. 2, a photoresist layer 6 is formed on the second blocking layer 12, and is exposed from the transparent substrate 1 side (back side). At this time, only the portion of the photoresist layer 6 corresponding to (opposing) the gate electrode 2 is not exposed by using the gate electrode 2 as a mask.

By developing the photoresist layer 6 and leaving only the portion of the photoresist layer 6 corresponding to the gate electrode 2 as shown in FIG. 3, the photoresist layer 6 has the same shape as the gate electrode 2. Perform patterning. As a result, a resist pattern 6 formed on the gate electrode 2 in a self-aligned manner is formed.

Using the resist pattern 6 as a mask and CF ₄ + O ₂ as a reaction gas, the second blocking layer 12 is dry-etched as shown in FIG. When CF ₄ + O ₂ is used as a reaction gas, the selectivity between silicon nitride (SiN) and silicon oxide (SiO) is 10 or more, and the second blocking layer 12 is hardly etched on the first blocking layer 11. Can be patterned. As a result, an insulating layer pattern 12 formed on the gate electrode 2 in a self-aligned manner is formed.

As shown in FIG. 4, using the remaining insulating layer pattern 12 as a mask, the semiconductor layer 4 penetrates through the first blocking layer 11 using an ion doping (ion implantation) apparatus. A p-type impurity such as phosphorus is implanted. Since the first blocking layer 11 is a relatively thin film as described above, ion doping (ion implantation) with a low accelerating voltage of 40 keV or less is performed.
The device can also be doped. By this ion doping, a channel region (an intrinsic (i) semiconductor region into which impurities are not implanted) formed in a self-aligned manner with respect to the gate electrode 2 and n-type high-concentration source and drain regions are formed. Next, the blocking layer 12 is removed by dry etching using CF ₄ + O ₂ as a reaction gas in the same manner as described above.

Next, as shown in FIG. 5, the semiconductor layer 4 is irradiated with a laser beam such as an excimer laser while the first blocking layer 11 is left to anneal the semiconductor layer 4, thereby converting the amorphous silicon to polysilicon. The converted and implanted n-type impurities are activated. Then, the first blocking layer 1
1 is coated with a photoresist and is exposed from the upper side of the drawing (substrate surface side) using a predetermined mask pattern;
This is developed to leave the photoresist only on the element region. Next, using the remaining photoresist as a mask, as shown in FIG.
Then, the semiconductor layer 4 is patterned to process a device area.

Thereafter, as shown in FIG. 7, a protective layer (interlayer insulating layer) 1 made of a silicon oxide film or the like is formed on the entire surface of the transparent substrate 1.
5, a contact hole is formed, aluminum, an aluminum alloy, or the like is deposited and patterned to form a source and drain electrode 16, thereby completing a thin film transistor.

According to this embodiment, since the blocking layer has a multilayer structure of an oxide film and a nitride film, the blocking layer can be processed by dry etching. Accordingly, it is not necessary to use BHF when patterning the blocking layer, and the quality of the gate insulating layer 3 can be maintained. As a result, the characteristics of the manufactured thin film transistor are improved, and the yield is improved. Will be higher. During the manufacturing process, the semiconductor layer 4 is covered and protected by the oxide film (the first blocking layer 11).
Infiltration of impurities into the substrate is prevented, and the process is resistant to impurities.

An experiment was performed to confirm the effect of the present embodiment. In this experiment, as shown in FIG. 8, an aluminum electrode 22, a silicon nitride film 23,
Semiconductor layer (50 nm thick amorphous silicon layer) 2
4. In the configuration in which the upper aluminum electrode 25 is formed, a voltage is applied between the upper electrode 25 and the lower electrode 22;
The defect density (pieces / cm ² ) of the silicon nitride film 23 was measured from the current flowing during this time. The broken line graph in FIG. 9 shows the silicon nitride film 23 and the amorphous silicon layer 24.
Is formed, the structure is immersed in a 1: 6 BHF solution for 2 minutes, and then the characteristic when the upper electrode 25 is formed, and the solid line is the characteristic when the treatment with the BHF liquid is not performed.

As can be seen from FIG. 9, the defect density of the silicon nitride film 23 subjected to the BHF treatment is increased even though the amorphous silicon layer 24 having a thickness of 50 nm is disposed. 23 is much larger than the defect density. In this embodiment, since the BHF process is not performed, defects in the silicon nitride film 23 are extremely reduced.

In the above embodiment, a method of manufacturing a thin film transistor constituting a drive circuit section of an active matrix liquid crystal display has been described. The present invention is not limited to this. A thin film transistor (display thin film transistor) for a display pixel connected to the gate line, the data line, and the pixel electrode may be manufactured by a similar manufacturing method. In this case, for example, the first blocking layer 11 and the semiconductor layer 4
After patterning into a device shape, a portion of the first blocking layer 11 on the source region is partially etched.
Next, a transparent conductive film made of ITO (indium-tin oxide) or the like is formed on the entire surface of the transparent substrate 1 and is etched to form a pixel electrode (display electrode) connected to the source region as shown in FIG. ) 19 is formed. Then, the protective layer 1
5 (removed above the pixel electrode 19), and the drain electrode 16 is formed. When a display thin film transistor is formed, laser annealing is not performed and the semiconductor layer 4 is not used.
Is preferably left as amorphous silicon.
This is to reduce the leakage current at the time of OFF.

In the above embodiment, an example was shown in which a photoresist pattern was formed in a self-aligned manner with respect to the gate electrode 2 by exposing the photoresist layer 6 from the back side of the substrate.
The exposure may be performed from the substrate surface side using a predetermined exposure mask (in this case, the source / drain regions are not formed in a self-aligned manner with respect to the gate electrode). In the above embodiment, the first blocking layer 11 is left to the end, but may be removed together with or after the second blocking layer 12 is removed. In the above embodiment, the oxide film and the nitride film are used as the first and second blocking layers 11 and 12, respectively.
A nitride film may be used as 1 and an oxide film may be used as the second blocking layer 12.

[0032]

As described above, according to the present invention, a thin film transistor can be manufactured while maintaining a high quality gate insulating layer. As a result, a high performance thin film transistor can be manufactured at a high yield. it can.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a thin-film transistor manufacturing process according to a thin-film transistor manufacturing method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the thin film transistor, and is a cross-sectional view showing a step subsequent to the step shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing step of the thin-film transistor, and is a cross-sectional view showing a step subsequent to the step shown in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing step of the thin film transistor, and is a cross-sectional view showing a step subsequent to the step shown in FIG.

5 is a cross-sectional view showing a manufacturing step of the thin-film transistor, and is a cross-sectional view showing a step subsequent to the step shown in FIG.

6 is a cross-sectional view showing a manufacturing step of the thin-film transistor, and is a cross-sectional view showing a step subsequent to the step shown in FIG.

FIG. 7 is a cross-sectional view showing a structure of a thin film transistor manufactured by a method for manufacturing a thin film transistor according to one embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the structure of a device used for confirming the effect of the method for manufacturing a thin film transistor according to one embodiment of the present invention.

9 is a characteristic diagram when a defect density of a nitride film is measured using the structure shown in FIG. 8, where a broken line indicates a measurement result when BHF processing is performed, and a solid line indicates a case when BHF processing is not performed. Is the measurement result.

FIG. 10 is a cross-sectional view showing a structure of a display thin film transistor manufactured according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a conventional bottom-gate thin film transistor.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing a conventional bottom-gate thin film transistor.

FIG. 13 is a cross-sectional view illustrating a method of manufacturing a conventional bottom-gate thin film transistor.

FIG. 14 is a cross-sectional view illustrating a method of manufacturing a conventional bottom-gate thin film transistor.

FIG. 15 is a cross-sectional view illustrating a method of manufacturing a conventional bottom-gate thin film transistor.

FIG. 16 is a cross-sectional view illustrating a method of manufacturing a conventional bottom-gate thin film transistor.

FIG. 17 is a cross-sectional view for explaining a method of manufacturing a conventional bottom-gate thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transparent substrate, 2 ... Gate electrode, 3 ... Gate insulating layer (SiN), 4 ... Semiconductor layer (Si), 6 ... Photoresist layer, 11 ... First Blocking layer (SiO), 1
2 ... second blocking layer (SiN), 15 ... interlayer insulating layer, 16 ... source / drain electrode, 19 ... pixel electrode, 21 ... glass substrate, 22 ... lower electrode , 23 ... silicon nitride film, 24 ... amorphous silicon layer, 25
..Top electrode, 101 transparent substrate, 102 gate electrode, 103 gate insulating layer, 104 semiconductor layer, 10
5: blocking layer, 106: photoresist layer

Claims (9)

(57) [Claims] A step of sequentially forming a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer, and a second insulating layer made of a different material from the first insulating layer on a substrate; A dry etching step of patterning the second insulating layer into a predetermined shape by dry etching while protecting the semiconductor layer with an insulating layer; and using the patterned second insulating layer as a mask,
A step of diffusing impurities into the semiconductor layer; a step of patterning the semiconductor layer into a predetermined element shape; a step of forming an insulating protective layer on the patterned semiconductor layer; Forming a contact hole, and forming a source electrode and a drain electrode connected to the source region and the drain region of the semiconductor layer through the contact hole. 2. The semiconductor device according to claim 1, wherein said gate insulating layer is formed of silicon nitride, said semiconductor layer is formed of silicon,
_2. The thin film transistor according to claim 1, wherein said insulating layer is formed of silicon oxide, said second insulating layer is formed of silicon nitride, and said dry etching process uses CF ₄ + O ₂ as a reactive gas. Production method. 3. The gate insulating layer is formed of silicon nitride, the first insulating layer is formed of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is formed of silicon oxide having a thickness of 100 to 2 nm.
Is formed from silicon nitride of nm, the dry etching process method of manufacturing a thin film transistor according to claim 1, wherein the use of CF ₄ + O ₂ as the reaction gas. 4. The step of patterning the semiconductor layer,
A step of patterning the first insulating layer and the semiconductor layer into substantially the same shape using the same etching mask, wherein the step of forming the protective layer includes leaving the first insulating layer 4. The method according to claim 1, further comprising forming the protective layer on the first insulating layer. 5. 5. The step of diffusing is a step of implanting impurities into the semiconductor layer through the first insulating layer, and further comprising the step of implanting impurities through the first insulating layer. 5. The method according to claim 1, further comprising a step of annealing the semiconductor layer. 6. The semiconductor layer is formed of amorphous silicon, and the semiconductor layer into which the impurity has been implanted is irradiated with laser through the first insulating layer to convert the amorphous silicon into polysilicon. 6. The method of manufacturing a thin film transistor according to claim 1, comprising a step. 7. The method further comprising: forming a photoresist layer on the second insulating layer; and exposing the photoresist layer from the substrate side using the gate electrode as a mask. The dry etching step is a step of dry-etching the second insulating layer using the exposed photoresist layer as a mask to leave a second insulating layer self-aligned with the gate electrode. The method for manufacturing a thin film transistor according to any one of claims 1 to 6, wherein 8. forming a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer, a second insulating layer having a different material from the first insulating layer, and a photoresist layer on a substrate; Exposing and developing a photoresist layer from the substrate side to form a photoresist pattern formed in a self-aligned manner with respect to the gate electrode; and forming the first photoresist pattern using the photoresist pattern as a mask.
Forming a second self-aligned insulating layer pattern with respect to the gate electrode by dry-etching the second insulating layer with a reactive gas having a different etching rate for the second insulating layer. An impurity implanting step of implanting impurities into the semiconductor layer using the insulating layer pattern as a mask; a step of patterning the first insulating layer and the semiconductor layer into an element shape; Forming an electrode connected to the semiconductor layer via the interlayer insulating layer. 2. A method for manufacturing a semiconductor device, comprising: 9. The gate insulating layer is formed of silicon nitride, the semiconductor layer is formed of amorphous silicon, the first insulating layer is formed of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is formed of silicon oxide. Layers are 100-20 thick
The dry etching step uses CF ₄ + O ₂ as a reaction gas, and the impurity implanting step implants impurities into the semiconductor layer through the first insulating layer, 9. The method according to claim 8, further comprising a step of laser annealing the semiconductor layer via the first insulating layer.
A method for manufacturing the thin film transistor according to the above.