JPH07273342A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a thin film transistor of high yield which can provide a thin film transistor having good characteristics. CONSTITUTION:A gate electrode 2, a gate insulation layer 3 consisting of SiN, a semiconductor layer 4 consisting of amorphous silicon, a first insulation layer 11 consisting of Sin, a second insulation layer 12 consisting of SiN and a photoresist layer are formed on a substrate 1. A photoresist layer 6 is exposed and developed from the rear side of a substrate and a photoresist pattern 6 is formed. The second insulation layer 12 is dry-etched by employing the photoresist pattern 6 as a mask and using CF4+O2 and an insulation layer pattern is formed. Impurities are injected into the semiconductor layer 4 through the first insulation layer 11 using the insulation layer pattern as a mask. The first insulation layer 11 and the semiconductor layer 4 are patterned to an element shape, a protection layer is formed on the first insulation layer 11 and a source/drain electrode connected to the semiconductor layer 4 through the protection layer is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) used as an active element of an active matrix liquid crystal display (AM-LCD).

[0002]

A thin film transistor is generally used as an active element of an active matrix liquid crystal display element or an active element forming a drive circuit. This type of thin film transistor is generally manufactured by the following manufacturing method.

First, as shown in FIG. 11, a glass substrate 1
A gate electrode 102, a gate insulating layer 103 made of silicon nitride, a semiconductor layer 104 made of amorphous silicon, and a blocking layer 105 are sequentially formed on 01. Figure 1
As shown in FIG. 2, a positive photoresist layer 106 is formed on the blocking layer 105, and exposure is performed from the glass substrate 101 side (back side). At this time, only the portion of the photoresist layer 106 corresponding to the gate electrode 102 is not exposed by using the gate electrode 102 as a mask.

The exposed photoresist layer 106 is developed to leave only the portion of the photoresist layer 106 corresponding to the gate electrode 102, as shown in FIG. The remaining photoresist layer 106 is used as a mask and BHF is used as an etchant to etch the blocking layer 105. As shown in FIG. 14, only the portion of the blocking layer 105 corresponding to the gate electrode 102 is etched. Patterning is performed so as to remain.

As shown in FIG. 14, using the remaining blocking layer 105 as a mask, impurities are implanted into the semiconductor layer 104 by using an ion doping (ion implantation) device to form an n ⁺ region. . Then, the blocking layer 105 is removed by etching.

As shown in FIG. 15, the semiconductor layer 104 is irradiated with an excimer laser to anneal the semiconductor layer 104,
Amorphous silicon is converted into polysilicon, and the implanted impurities are activated to form a source region and a drain region. The semiconductor layer 104 is patterned into a device shape, and the device area is processed as shown in FIG. Thereafter, as shown in FIG. 17, the interlayer insulating layer 107
And the source and drain electrodes 108 are formed to complete the thin film transistor.

[0007]

According to the above manufacturing method, when the blocking layer 105 is patterned using BHF, BHF penetrates into the gate insulating layer 103 and etches silicon nitride. Therefore, there is a problem that the defect density of the gate insulating layer 103 of the manufactured thin film transistor becomes very large, the yield is lowered, and the withstand voltage characteristic of the manufactured thin film transistor is deteriorated.

In order to eliminate such a defect, it is possible to pattern the blocking layer 105 by dry etching. However, there is a problem that dry etching cannot be used because the selection ratio between the semiconductor layer 104 and the gate insulating layer 103 is small.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a thin film transistor having a high yield rate.
Moreover, this invention aims at providing the manufacturing method of the thin-film transistor which can manufacture the thin-film transistor which has the outstanding characteristic.

[0010]

In order to achieve the above object, a method of manufacturing a thin film transistor according to a first aspect of the present invention comprises a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer on a substrate, A step of sequentially forming a second insulating layer made of a material different from that of the first insulating layer, and patterning the second insulating layer into a predetermined shape by dry etching while protecting the semiconductor layer by the first insulating layer A dry etching step, a diffusion step of diffusing impurities into the semiconductor layer using the patterned second insulating layer as a mask, a step of patterning the semiconductor layer into a predetermined element shape, and a step of patterning the semiconductor layer. Forming an insulating protective layer on the semiconductor layer, forming a contact hole in the protective layer, and through the contact hole, the source of the semiconductor layer Characterized in that it comprises a step of forming a source electrode and a drain electrode connected to the band and the drain region.

For example, the gate insulating layer is formed of silicon nitride, the first insulating layer is formed of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is 100 to 200 in thickness.
formed of silicon nitride of nm, the dry etching process is performed using CF ₄ + O ₂ as a reaction gas.

By forming the second insulating layer in self alignment with the gate electrode by using backside exposure, the channel region of the semiconductor layer can be formed in self alignment with the gate electrode. The first insulating layer is, for example, patterned into the same shape as the semiconductor layer, and remains until completion. Impurities are implanted into the semiconductor layer through the first insulating layer. The semiconductor layer after the impurity implantation may be annealed.

According to a second aspect of the present invention, there is provided a method of manufacturing a thin film transistor, in which a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer, and a material different from those of the first insulating layer are formed on a substrate. Second step of forming an insulating layer and a photoresist layer, and a step of exposing the photoresist layer from the substrate side and developing it to form a photoresist pattern formed in a self-aligned manner with respect to the gate electrode. And using the photoresist pattern as a mask,
An insulating layer pattern formed in a self-aligned manner with respect to the gate electrode by dry-etching the second insulating layer using reaction gases having different etching rates for the first and second insulating layers. A step of forming, a step of implanting impurities into the semiconductor layer using the insulating layer pattern as a mask, a step of patterning the first insulating layer and the semiconductor layer into an element shape, and the first step. The method is characterized by including a step of forming an interlayer insulating layer on the insulating layer and a step of forming an electrode connected to the semiconductor layer via the interlayer insulating layer.

For example, the gate insulating layer is made of silicon nitride, the semiconductor layer is made of amorphous silicon, the first insulating layer is made of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is made of silicon oxide. It is formed of 100-200 nm silicon nitride, CF ₄ + O ₂ is used as a reaction gas in the dry etching process, and impurities are implanted into the semiconductor layer through the first insulating layer. The impurity-implanted semiconductor layer may be laser-annealed through the first insulating layer to be poly-doped.

[0015]

With the above structure, according to the method of manufacturing a thin film transistor according to the first and second aspects of the present invention, when the second insulating layer is patterned, the semiconductor layer becomes the second insulating layer. Since it is protected by the first insulating layer having a different etching rate, the semiconductor layer is not damaged. Further, since the second insulating layer is etched by dry etching, the characteristics of the manufactured thin film transistor can be maintained and the yield rate can be improved without damaging the gate insulating layer.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a thin film transistor according to an embodiment of the present invention will be described below with reference to the drawings. The thin film transistor according to this example constitutes a drive circuit of an active matrix type liquid crystal display element.

First, a conductive film made of a light-impermeable conductive material such as aluminum (Al), aluminum alloy, or chromium is formed on the transparent substrate 1 made of glass, a flexible film or the like by sputtering, vapor deposition or the like. It is formed to a thickness of about 60 to 150 nm. Next, this is patterned using a photolithography process to form a gate electrode (and a gate wiring connected thereto) 2.

A gate insulating layer 3 made of a silicon nitride film (SiN) or the like is deposited on the entire surface of the transparent substrate 1 by plasma CVD or the like to a thickness of about 100 to 300 nm. A semiconductor layer 4 made of amorphous silicon is deposited on the entire surface of the transparent substrate 1 by plasma CVD or the like to a thickness of about 20 to 80 nm.

Next, a first blocking layer 11 made of a silicon oxide film (SiO) is deposited by using a sputtering device and a plasma CVD device. As will be described later, the first blocking layer 11 has a function of protecting the semiconductor layer 4 when the second blocking layer 12 is dry-etched, and it is preferable that the first blocking layer 11 be thick from this viewpoint. On the other hand, in order to implant impurities into the semiconductor layer 4 (FIG. 4) and perform laser annealing (FIG. 5), it is desirable that the semiconductor layer 4 be thin. In order to satisfy these contradictory conditions, the first blocking layer 11 is preferably formed to have a thickness of 10 to 30 nm, preferably 16 to 24 nm, and particularly preferably 19 to 21 nm.

Next, the second blocking layer 12 made of a silicon nitride film (SiN) is formed by using a plasma CVD apparatus.
The thickness is 50-250 nm, preferably 100-180
nm, particularly preferably about 130 to 150 nm thick. Through the above steps, the structure shown in FIG. 1 is completed.

Next, as shown in FIG. 2, a photoresist layer 6 is formed on the second blocking layer 12 and exposed from the transparent substrate 1 side (back side). At this time, the gate electrode 2 serves as a mask, and only the portion of the photoresist layer 6 corresponding to (opposing) the gate electrode 2 is not exposed.

By developing the photoresist layer 6 and leaving only the portion of the photoresist layer 6 corresponding to the gate electrode 2 as shown in FIG. 3, the photoresist layer 6 is formed into the same shape as the gate electrode 2. Pattern. As a result, the resist pattern 6 formed in the gate electrode 2 in a self-aligned manner is formed.

Using the resist pattern 6 as a mask and CF ₄ + O ₂ as a reaction gas, the second blocking layer 12 is dry-etched as shown in FIG. When CF ₄ + O ₂ is used as the reaction gas, the selection ratio of silicon nitride (SiN) to silicon oxide (SiO) is 10 or more, and the second blocking layer 12 is hardly etched in the first blocking layer 11. Can be patterned. As a result, the insulating layer pattern 12 is formed on the gate electrode 2 in a self-aligned manner.

As shown in FIG. 4, the remaining insulating layer pattern 12 is used as a mask and an ion doping (ion implantation) apparatus is used to penetrate the first blocking layer 11 into the semiconductor layer 4. A p-type impurity such as phosphorus is implanted. Since the first blocking layer 11 is a relatively thin film as described above, ion doping (ion implantation) with a low acceleration voltage of 40 keV or less is performed.
It can also be doped in the device. By this ion doping, a channel region (intrinsic (i) semiconductor region in which impurities are not implanted) formed in a self-aligned manner with respect to the gate electrode 2 and n-type high-concentration source and drain regions are formed. Next, the blocking layer 12 is removed by dry etching using CF ₄ + O ₂ as a reaction gas as described above.

Next, as shown in FIG. 5, the semiconductor layer 4 is annealed by irradiating the semiconductor layer 4 with a laser beam such as an excimer laser while leaving the first blocking layer 11 left, and the amorphous silicon is converted into polysilicon. The converted and implanted n-type impurities are activated. Then the first blocking layer 1
1 is coated with a photoresist, which is exposed from the upper side of the drawing (substrate surface side) using a predetermined mask pattern,
This is developed so that the photoresist remains only on the element region. Next, using the remaining photoresist as a mask, the first blocking layer 11 is formed as shown in FIG.
Then, the semiconductor layer 4 is patterned to process the device area.

Thereafter, as shown in FIG. 7, a protective layer (interlayer insulating layer) 1 made of a silicon oxide film or the like is formed on the entire surface of the transparent substrate 1.
5, a contact hole is formed in this, aluminum, an aluminum alloy, etc. are vapor-deposited and patterned, the source and drain electrodes 16 are formed, and a thin film transistor is completed.

According to this embodiment, since the blocking layer has a multilayer structure of the oxide film and the nitride film, the blocking layer can be processed by dry etching. As a result, it is not necessary to use BHF when patterning the blocking layer, the gate insulating layer 3 can be maintained at high quality, and as a result, the characteristics of the manufactured thin film transistor are improved, and the yield rate is improved. Becomes higher. In addition, since the semiconductor layer 4 is covered and protected by the oxide film (first blocking layer 11) during the manufacturing process, the semiconductor layer 4 is protected.
Impurities are prevented from entering into the process, and the process is resistant to impurities.

An experiment was conducted to confirm the effect of this example. In this experiment, as shown in FIG. 8, the aluminum electrode 22, the silicon nitride film 23, the
Semiconductor layer (50 nm thick amorphous silicon layer) 2
4. In the structure in which the upper aluminum electrode 25 is formed, a voltage is applied between the upper electrode 25 and the lower electrode 22,
The defect density (pieces / cm ² ) of the silicon nitride film 23 was measured from the current flowing during this period. The broken line graph in FIG. 9 shows the silicon nitride film 23 and the amorphous silicon layer 24.
After the formation, the structure was immersed in a 1: 6 BHF solution for 2 minutes and then the upper electrode 25 was formed. The solid line shows the characteristics when the treatment with the BHF solution was not performed.

As is apparent from FIG. 9, although the amorphous silicon layer 24 having a thickness of 50 nm is arranged, the defect density of the silicon nitride film 23 subjected to the BHF treatment is the same as that of the silicon nitride film not subjected to the BHF treatment. It is much larger than the defect density of 23. In this embodiment, since the BHF process is not performed, the defects in the silicon nitride film 23 are extremely reduced.

In the above embodiment, the method of manufacturing the thin film transistor which constitutes the drive circuit portion of the active matrix liquid crystal display has been described. The present invention is not limited to this. A thin film transistor for display pixels (display thin film transistor) connected to the gate line, the data line, and the pixel electrode may be manufactured by the same manufacturing method. In this case, for example, the first blocking layer 11 and the semiconductor layer 4
After being patterned into a device shape, a part of the first blocking layer 11 on the source region is partially etched.
Next, a transparent conductive film made of ITO (indium-tin oxide) or the like is formed on the entire surface of the transparent substrate 1, and the transparent conductive film is etched to form a pixel electrode (display electrode) connected to the source region as shown in FIG. ) 19 is formed. Then the protective layer 1
5 is formed (the pixel electrode 19 is removed), and the drain electrode 16 is formed. When forming the display thin film transistor, laser annealing is not performed and the semiconductor layer 4 is not formed.
Is preferably left as amorphous silicon.
This is to reduce the leakage current at the time of off.

In the above embodiment, an example is shown in which the photoresist layer 6 is exposed from the back side of the substrate to form a resist pattern in a self-aligned manner with respect to the gate electrode 2.
The exposure may be performed from the substrate surface side using a predetermined exposure mask (in this case, the source / drain regions are not formed in self alignment with the gate electrode). In the above embodiment, the first blocking layer 11 is left to the end, but it may be removed together with the second blocking layer 12 or after removing it. In the above embodiment, the oxide film and the nitride film were used as the first and second blocking layers 11 and 12, respectively. However, for example, the first blocking layer 1
A nitride film may be used as 1 and an oxide film may be used as the second blocking layer 12.

[0032]

As described above, according to the present invention, a thin film transistor can be manufactured while maintaining a high quality gate insulating layer, and as a result, a high performance thin film transistor can be manufactured with a high yield rate. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a thin film transistor by a method of manufacturing a thin film transistor according to an embodiment of the present invention.

2 is a cross-sectional view showing the manufacturing process of the thin film transistor, which is a cross-sectional view showing the next process of the process shown in FIG. 1. FIG.

FIG. 3 is a cross-sectional view showing the manufacturing process of the thin film transistor, which is a cross-sectional view showing a step subsequent to the step shown in FIG. 2.

FIG. 4 is a cross-sectional view showing the manufacturing process of the thin-film transistor, which is a cross-sectional view showing the next process of the process shown in FIG.

5 is a cross-sectional view showing the manufacturing process of the thin film transistor, which is a cross-sectional view showing a step subsequent to the step shown in FIG. 4. FIG.

6 is a cross-sectional view showing the manufacturing process of the thin film transistor, which is a cross-sectional view showing a step subsequent to the step shown in FIG. 5. FIG.

FIG. 7 is a cross-sectional view showing a structure of a thin film transistor manufactured by a method of manufacturing a thin film transistor according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the structure of an apparatus used for confirming the effect of the method of manufacturing a thin film transistor according to an embodiment of the present invention.

9 is a characteristic diagram when the defect density of the nitride film is measured using the structure shown in FIG. 8, the broken line shows the measurement result when BHF treatment is performed, and the solid line shows when BHF treatment is not performed. Is the measurement result.

FIG. 10 is a sectional view showing a structure of a display thin film transistor manufactured according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating the method of manufacturing the conventional bottom-gate thin film transistor.

FIG. 12 is a cross-sectional view illustrating the method for manufacturing the conventional bottom-gate thin film transistor.

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the conventional bottom-gate thin film transistor.

FIG. 14 is a cross-sectional view illustrating the method for manufacturing the conventional bottom-gate thin film transistor.

FIG. 15 is a cross-sectional view illustrating the method for manufacturing the conventional bottom-gate thin film transistor.

FIG. 16 is a cross-sectional view illustrating the method for manufacturing the conventional bottom-gate thin film transistor.

FIG. 17 is a cross-sectional view illustrating the method for manufacturing the conventional bottom-gate thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transparent substrate, 2 ... Gate electrode, 3 ... Gate insulating layer (SiN), 4 ... Semiconductor layer (Si), 6 ... Photoresist layer, 11 ... 1st Blocking layer (SiO), 1
2 ... second blocking layer (SiN), 15 ... interlayer insulating layer, 16 ... source / drain electrode, 19 ... pixel electrode, 21 ... glass substrate, 22 ... lower electrode , 23 ... Silicon nitride film, 24 ... Amorphous silicon layer, 25 ...
..Upper electrode, 101 ... Transparent substrate, 102 ... Gate electrode, 103 ... Gate insulating layer, 104 ... Semiconductor layer, 10
5 ... Blocking layer, 106 ... Photoresist layer

Claims (9)

[Claims] 1. A step of sequentially forming a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer, and a second insulating layer made of a material different from that of the first insulating layer on a substrate, and the first insulating layer. A dry etching step of patterning the second insulating layer into a predetermined shape by dry etching while protecting the semiconductor layer with an insulating layer; and using the patterned second insulating layer as a mask,
A diffusion step of diffusing impurities into the semiconductor layer, a step of patterning the semiconductor layer into a predetermined element shape, a step of forming an insulating protective layer on the patterned semiconductor layer, and a step of forming a protective layer on the protective layer. Forming a contact hole and forming a source electrode and a drain electrode connected to the source region and the drain region of the semiconductor layer through the contact hole, respectively. 2. The gate insulating layer is formed of silicon nitride and the semiconductor layer is formed of silicon.
_2. The thin film transistor according to claim 1, wherein the insulating layer is formed of silicon oxide, the second insulating layer is formed of silicon nitride, and the dry etching process uses CF ₄ + O ₂ as a reaction gas. Production method. 3. The gate insulating layer is formed of silicon nitride, the first insulating layer is formed of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is formed of 100 to 2 in thickness.
The method of claim 1, wherein the thin film transistor is formed of 00 nm silicon nitride, and the dry etching process uses CF ₄ + O ₂ as a reaction gas. 4. The step of patterning the semiconductor layer comprises:
Including a step of patterning the first insulating layer and the semiconductor layer into substantially the same shape using the same etching mask, and the step of forming the protective layer, the first insulating layer is left as it is, 4. The method of manufacturing a thin film transistor according to claim 1, comprising forming the protective layer on the first insulating layer. 5. The diffusion step is a step of injecting an impurity into the semiconductor layer through the first insulating layer, and further, the impurity injected through the first insulating layer. The method for manufacturing a thin film transistor according to claim 1, comprising a step of annealing the semiconductor layer. 6. The semiconductor layer is formed of amorphous silicon, and the semiconductor layer in which the impurities are injected through the first insulating layer is irradiated with a laser to convert the amorphous silicon into polysilicon. The method for manufacturing a thin film transistor according to claim 1, further comprising a step. 7. The method further comprises: forming a photoresist layer on the second insulating layer; and exposing the photoresist layer from the side of the substrate using the gate electrode as a mask. The dry etching step is a step of dry-etching the second insulating layer using the exposed photoresist layer as a mask to leave the second insulating layer self-aligned with the gate electrode. 7. The method of manufacturing a thin film transistor according to claim 1, wherein there is. 8. A step of forming a gate electrode, a gate insulating layer, a semiconductor layer, a first insulating layer, a second insulating layer different in material from the first insulating layer, and a photoresist layer on a substrate, Exposing a photoresist layer from the side of the substrate and developing the photoresist layer to form a photoresist pattern formed in a self-aligned manner with the gate electrode;
And a step of forming an insulating layer pattern formed in a self-aligned manner with respect to the gate electrode by dry etching the second insulating layer using reaction gases having different etching rates for the second insulating layer. An impurity injection step of injecting impurities into the semiconductor layer using the insulating layer pattern as a mask; a step of patterning the first insulating layer and the semiconductor layer into an element shape; And a step of forming an electrode connected to the semiconductor layer via the interlayer insulating layer, and a method of manufacturing a semiconductor element. 9. The gate insulating layer is formed of silicon nitride, the semiconductor layer is formed of amorphous silicon, the first insulating layer is formed of silicon oxide having a thickness of 10 to 30 nm, and the second insulating layer is formed. Layers are 100 to 20 thick
Formed of 0 nm silicon nitride, the dry etching process uses CF ₄ + O ₂ as a reaction gas, the impurity implantation process penetrates the first insulating layer, and implants impurities into the semiconductor layer, 9. The method further comprises laser annealing the semiconductor layer via the first insulating layer.
A method for manufacturing the thin film transistor described.