JP2595757B2 - Thin film field effect transistor and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film field effect transistor used for a matrix display element and the like, and a method for manufacturing the same.

[Conventional technology]

A technology for forming a thin film transistor using a silicon thin film on an insulating substrate such as glass is important as a core technology for a matrix display element or the like. In order to enhance the matrix display element, a high performance thin film field effect transistor is required also as a pixel switching element. One of the measures is to reduce the burden of alignment in the photolithography process and shorten the channel of the transistor by manufacturing a thin film field effect transistor (hereinafter referred to as TFT) in a self-aligned manner. Proposed.

One way to realize self-alignment is to place the gate on the substrate side, that is, on a TFT with a so-called inverted staggered structure, place it on an amorphous silicon thin film to separate the source and drain A source / drain of an amorphous silicon thin film is formed by using the insulating film or a resist material used for forming the pattern as a mask by so-called back surface exposure in which the insulating film is exposed by light irradiated from the back surface of the substrate. By selectively implanting impurities into the region and further depositing a metal such as Cr on this surface, a low-resistance metal silicide is formed only on the surface of the amorphous silicon thin film, Gate and source
TFTs having a structure in which delicate alignment between drains is not required and a parasitic capacitance is reduced have been proposed (for example, Japanese Patent Application Nos. 61-307039 and 61-311828).

At this time, when the metal silicide used as the source / drain electrode is in direct contact with the i-layer (the region where the impurities in the amorphous silicon thin film are not doped), a hole current flows through this portion, and the TFT flows into the gate electrode of the TFT. There is a phenomenon that the drain current (OFF current) when a voltage of OV or less is applied increases nonlinearly with respect to the drain voltage.
Therefore, in order to avoid direct contact between the metal or metal silicide and the i-layer, there is a method described in Japanese Patent Application No. 1-139521. In this method, as shown in FIG. 2, two protective insulating films 7 and 8 were continuously formed on an amorphous silicon thin film 3 and this was made slightly thinner than the gate electrode 1 by back exposure. After forming a pattern and using the mask as a mask to etch the protective insulating films 7 and 8 with the same pattern, the upper protective insulating film 8 is side-etched by a predetermined amount and then passes through the lower protective insulating film 7. By implanting phosphorus with only the acceleration voltage, the lower protective insulating film 7 is formed.
The lower amorphous silicon thin film is selectively doped to form an n ⁺ layer 4 to form a source / drain. Thereby, direct contact between the i-layer and the metal is avoided, and good characteristics are obtained.

[Problems to be solved by the invention]

This method has a small number of steps and is simple in terms of process. However, since one of the two protective insulating films is side-etched, there is little controllable margin, and the width of the step when forming the step structure is limited by the film thickness. It was limited to very small conditions.

Therefore, particularly when the channel length is shortened, the intensity of the electric field applied to the drain portion becomes larger than that of a transistor having a longer channel length even at the same drain voltage, and the pseudo-Fermi level decreases in the n ⁺ layer below the protective insulating film. , N ⁺ layer is not long enough in the channel direction, so that a state occurs in which the blocking of holes is not complete. Thus, a non-linear increase in current is observed when the drain voltage is increased. This is extremely inconvenient when this TFT is used as a switching element of a pixel of an active matrix liquid crystal display.
This is a serious problem in increasing the aperture ratio and reducing the odd-number capacity.

In addition, since the step portion is ion-implanted through the first protective insulating film, the protective insulating film in this portion is in a state where phosphorus is ion-implanted. In general, the bonding state of the ion-implanted insulating film is often unstable, so that the injected carriers are easily trapped.
Electrons accelerated by receiving a strong electric field at the edges of the source and drain are easily trapped in these portions. As a result, fixed charges are generated, which causes a reduction in the reliability of the device.

An object of the present invention is to provide an amorphous silicon TFT formed in a self-aligned manner as described above, in which the region of the n ⁺ layer under the protective insulating film is expanded so that blocking of holes can be prevented even when a stronger electric field is applied to the drain. It is an object of the present invention to provide a thin-film field-effect transistor that can provide a TFT having a structure that can be performed completely and that does not impair the reliability of a protective insulating film when the TFT is realized in a self-aligned manner.

[Means for solving the problem]

According to the present invention, a gate electrode, a gate insulating film, and an amorphous silicon thin film are laminated and arranged on an insulating substrate in this order from the substrate side, and a portion of the amorphous silicon thin film immediately above the gate is wider than the gate electrode width. A first protection insulating film having a narrow width, further covering the first protection insulation film completely, and extending at least 500 ° or more in both directions of a source electrode and a drain electrode provided on both sides of a region immediately above the gate electrode; Disposing a second protective insulating film having an area not protruding from a region immediately above the electrode on the first protective insulating film;
The source electrode and the drain electrode are brought into contact with the amorphous silicon thin film not covered with the protective insulating film, and the amorphous silicon thin film not covered with the first protective insulating film does not reach the gate insulating film from the surface. A thin film field effect transistor characterized in that an appropriate region is doped with an impurity.

Further, according to the method of manufacturing a thin film field effect transistor of the present invention, after forming a gate electrode on an insulating substrate surface, a gate insulating film, an amorphous silicon thin film, and a first protective insulating film are laminated, and the first protective insulating film is formed. After applying the resist on the film surface, irradiate ultraviolet rays from the back surface of the substrate, use the already formed gate electrode as a mask, control the exposure time, form a pattern with a slightly narrowed gate electrode, and use this pattern as a mask After the first protective insulating film is etched and the resist is removed, ion implantation is performed using the first protective insulating film as a mask to dope the source / drain portions of the amorphous silicon thin film with impurities, and further to cover the entire surface with the second protective insulating film. After the formation of the protective insulating film, a resist is applied to the surface of the second protective insulating film, ultraviolet light is again irradiated from the back surface of the insulating substrate, and the exposure time is reduced using the already formed gate electrode as a mask. Protective insulating film sufficiently short compared with the time of exposing and moreover subjected to exposure by setting the time that the resist is sufficiently sensitive, to form a mask pattern of,
Thereafter, the second protective insulating film is etched to form a source electrode and a drain electrode on the surface of the amorphous silicon thin film doped with the exposed impurities.

Further, the step of exposing the pattern of the first protective insulating film in the above-described manufacturing method is performed by using the angle of the center line of the gate electrode after the application of the resist as the number of rotations so that the direction of the normal to the substrate is constant with respect to the traveling direction of the ultraviolet rays. After rotating the substrate so that it has an angle, and irradiating ultraviolet rays from the back surface of the substrate, the normal direction of the substrate further has a certain angle in the opposite direction with respect to the traveling direction of the ultraviolet rays. The substrate is fixed in a rotated state, and the substrate is exposed to light by irradiating the back surface of the substrate with ultraviolet light twice, and the first direction is determined by the angle between the normal direction of the substrate and the irradiation direction of ultraviolet light. A method for manufacturing a thin-film field-effect transistor, characterized by replacing the step of determining the position and size of a protective insulating film with respect to a gate electrode.

[Action]

Generally, if an n ⁺ layer having a sufficient thickness is formed in the source / drain region, no hole current flows through the n ⁺ layer. However, the application of a strong electric field thereto when the n ⁺ layer is thin, reduction of quasi-Fermi levels in the n ⁺ layer in the place, the presence of the hole can not be ignored. As a result, the hole current and the recombination current increase. That is, when the channel length is reduced and the drain voltage is increased, it is necessary to form the n ⁺ layer in a sufficiently wide region in order to eliminate the effect of the current caused by holes.

When the resist is exposed by irradiating ultraviolet rays from the back surface of the substrate, as in the case of the TFT of the present invention shown in FIG. When the resist 13 applied through the thin film 3 and the protective insulating film 7 is irradiated with ultraviolet rays 13, as shown in FIG. 3A, the ultraviolet rays 13 passing near the end of the gate electrode are diffracted, The pattern formed is the gate electrode 1
Is slightly reduced. As shown in FIG. 3B, since the intensity of the diffracted light 14 is smaller than that of ordinary transmitted light, if the exposure time is short, the exposure amount is not sufficient, and the resist in this portion remains during development. However, if the exposure time is long, the exposure amount becomes sufficient and is removed during development. That is, the overexposure amount is determined by the exposure time (T), and the amount (d) by which the pattern of the protective insulating film 7 recedes from the gate electrode 1 is uniquely determined. This relationship is represented by the following equation.

using the d = g (T) Therefore, when forming the first protective insulating film, the longer takes T ₁ the exposure time, when forming the second protective insulating film, the exposure time is shortened By setting T ₂ (T ₂ <T ₁ ), a relationship between the two protective insulating films 7 and 8 as shown in FIG. 4 can be formed.

At the stage where the first protective insulating film is patterned and the resist is removed, phosphorus is ion-implanted into the first protective insulating film at a low accelerating voltage. Phosphorus is doped to form an n ⁺ layer of source / drain electrodes. When a second protective insulating film is formed from above and a back exposure is performed on the second protective insulating film under the above-described conditions to form a pattern, as shown in FIG.
An n ⁺ layer 4 is formed under the protective insulating film in a region at a distance of L = g (T ₁ ) −g (T ₂ ) from the contact portion of the drain. This L can be controlled by the back exposure times T ₁ , T ₂ for the first and second protective insulating films, and a maximum of about 1 μm can be manufactured.

When the n ⁺ layer 4 is formed in a sufficiently wide area below the protective insulating film 8 in this manner, the change in the pseudo Fermi level formed by the strong electric field is absorbed therein, and the effect of the hole reaches the electrode. Since no hole current flows, a non-linear increase in current due to the drain voltage when a voltage of 0 V or less is applied to the gate electrode 1 can be prevented.

When the ion implantation is performed, the first protective insulating film 7 is used as a mask, but the implanted ions stop at the upper portion of the first protective insulating film 7 and reach the interface with the amorphous silicon thin film 3. Do not reach. For this reason, it is possible to avoid a structure in which charges are easily trapped in the protective insulating film at the interface between the protective insulating film and the amorphous silicon thin film as in the conventional example shown in FIG. 2, thereby improving the reliability of the device. .

Also, when performing back exposure, as shown in FIG.
Is fixed with the center line of the gate electrode 1 as a rotation axis until the normal direction of the substrate 10 has a certain angle (θ) with respect to the traveling direction of the ultraviolet light 13, and the ultraviolet light 13 is Upon irradiation, the pattern of the gate electrode is exposed at a position shifted from immediately above the gate electrode by F (θ) = D ₁ tan (θ ₁ ) + D ₂ tan (θ ₂ ) + D ₃ tan (θ ₃ ). Here, D ₁ , D _2, and D ₃ are the thicknesses of the gate insulating film 2, the amorphous silicon thin film 3, and the protective insulating film 7, respectively, and n ₁ , n ₂ , and n ₃ are the respective refractive indexes, θ ₁ , and θ. ₂ ,
theta ₃ Each UV 13 internally represent normal and angle of the substrate 10. Usually, the thickness of the gate insulating film 2 is 3000 mm, the thickness of the amorphous silicon thin film is 700 mm, and the thickness of the protective insulating film is about 2000 mm. The refractive indexes are about 1.5, 3.5, and 1.5, respectively, and when θ is 45 °, F is about 5000 °. When exposure is performed while the substrate is rotated in the opposite direction, the pattern is shifted in the opposite direction. As shown in FIG. 7, in the resist 12 that has been subjected to the above two back exposures, only the common portion 18 of the pattern projected by both exposures remains by development.

After patterning the first protective insulating film using the above-described exposure, ion implantation is performed, a second protective insulating film is formed thereon, and back exposure is performed by a normal method, as shown in FIG. Such a state can be realized in a self-aligned manner. At this time, L is L = F (θ) + g (T ₁ ) −g (T ₂ ). In this case, since L is mainly controlled by the rotation direction of the substrate, the process becomes somewhat complicated,
TFTs with larger L can be made.

With the above method, the n ⁺ under the channel protective film is well controlled.
The flow L of the layer can be determined. This can prevent a non-linear increase in current due to holes. Further, in this structure, since the implanted ions do not reach the interface between the first protective insulating film and the amorphous silicon thin film, the reliability of the protective insulating film is not lost.

〔Example〕

FIG. 1 (a) is a sectional view of one embodiment of the thin film field effect transistor of the first invention. FIG. 1B shows a plan view of this transistor.

Hereinafter, an example in which a TFT having the structure of the first invention is manufactured in a self-aligned manner according to the second invention will be described.

First, 500 g of Cr is sputtered on the glass substrate 10.
さ せ る Deposit. The gate electrode 1 is formed by etching the Cr thin film while removing the unnecessary Cr thin film while leaving the pattern of the gate electrode. After thoroughly washing this with pure water,
Using plasma CVD, an amorphous silicon nitride thin film of 4000 .ANG., A hydrogenated amorphous silicon thin film 3 of 700 .ANG., And an amorphous silicon nitride thin film of 2000 .ANG. Deposited on

Here, after applying the positive type polymer resist agent, by performing the exposure for 2 minutes longer than the usual back exposure time of 5 minutes, over-exposure occurs, and about 2000 ° to the gate electrode 1. The thin pattern is exposed. After this is developed and baked, the first protective insulating film 7 is etched using this resist as a mask by dry etching with high perpendicularity, avoiding side etching as much as possible. Thereafter, the first protective insulating film 7 is removed by stripping the resist.
Are formed in a self-aligned manner.

On the other hand, the dose of phosphorus is 4 × 15 ¹⁵ at an acceleration voltage of 25 kV.
Io is injected only at dose / cm ² . At this time, the acceleration voltage is stopped at an upper portion of the first protective insulating film, and is low enough that the ions implanted into the amorphous silicon thin film 3 do not reach the interface with the gate insulating film 2. Is required. In this case, the thickness of the amorphous silicon thin film 3 is 700 °, and the acceleration voltage is preferably 30 kV or less in consideration of the range of phosphorus in the amorphous silicon thin film. The metal material used later as the electrode and the amorphous silicon thin film 3 are 100
It is desirable to dope to a depth of about 200 ° or more to interact with the following surface portions. Therefore, an acceleration voltage of 10 kV or more is required. In this range, doping does not need to be performed with constant energy, and if uniformity and reproducibility are guaranteed, it is possible to perform implantation with ions distributed with energy distributed in this range.

After the ion implantation, annealing is performed at 230 ° C. for 1 hour in an argon atmosphere. As a result, the implanted phosphorus ions are electrically activated, and the n ⁺ layer 4 is formed. The annealing atmosphere is not limited to argon, but may be hydrogen. Further, the characteristics are remarkable even in the air and nitrogen, and the characteristics do not deteriorate. The pressure during annealing may be atmospheric pressure or vacuum.
The annealing may be performed in a short time using laser irradiation or the like.

Thereafter, an amorphous silicon nitride thin film 500 # is formed as the second protective insulating film 8. After applying a positive polymer resist agent thereto, the back surface is irradiated with ultraviolet rays for a normal exposure time, and the exposure is performed using the gate electrode 1 as a mask. After development and baking, the second protective insulating film is etched by using the mask as a mask by dry etching with high perpendicularity, avoiding side etching.

After removing the resist, remove the natural oxide film formed on the surface of the amorphous silicon thin film with sufficiently diluted hydrofluoric acid.
Immediately deposit a 500-mm Cr thin film by sputtering.
At this time, it is necessary that the second protective insulating film 8 is not etched with hydrofluoric acid as much as possible. For this reason, it is desirable that the second protective insulating film 8 is made of silicon nitride or the like manufactured under a condition that the etching rate is low with respect to hydrofluoric acid. This Cr thin film is etched into a pattern of the source / drain electrode 6. By this process, in a portion where the second protective insulating film does not remain, Cr silicide 5 is formed on the surface of the amorphous silicon, and functions as a source / drain electrode.

In this state, unnecessary portions of the amorphous silicon thin film are removed by dry etching. Made by this process
Even if the TFT is shortened, the TFT shows good characteristics as shown in FIG.

In this embodiment, it is necessary that the gate electrode shields ultraviolet rays used for exposure and has a low resistance enough to sufficiently control the potential. In the present embodiment, the film thickness is set to 500 °, but this may be thicker. In addition, the purpose can be achieved even with about 300 mm. It is desirable that the material be a material that does not interfere with the amorphous dielectric and is used as the gate insulating film. In addition to Cr, materials such as Mo and Ta are conceivable. Further, the resistance may be further reduced by laminating Al and Cr.

Although a silicon nitride film forms a favorable interface with amorphous silicon as a gate insulating film, the silicon nitride film may be formed into two layers by using another insulating derivative. Further, the film thickness is required to be a thickness that ensures insulation between the gate electrode and the amorphous silicon or another electrode, but may be 1000 mm or more.

Since the amorphous silicon thin film strongly absorbs ultraviolet light, it needs to have a thickness of about 1500 mm or less for back exposure.

In this embodiment, silicon nitride is used as the first protective insulating film, but this may be another insulating derivative such as silicon oxide. This also applies to the second protective insulating film.

Next, an example in which the TFT of the first structure is operated in a self-aligned manner based on the third invention will be described.

First, Cr is deposited on an insulating substrate by a thickness of 500 ° by a sputtering method. The Cr thin film is etched to remove the unnecessary Cr thin film while leaving the pattern of the gate electrode, and the remaining portion is removed to the gate electrode 1.
And Further, after this is sufficiently washed with pure water, an amorphous silicon nitride thin film of 4000 .ANG.
Is continuously deposited, and an amorphous silicon nitride thin film 2000 # is continuously deposited as the first protective insulating film 7.

Here, after applying the positive type polymer resist agent, the substrate is rotated around the center line of the gate electrode 1 so that the normal line of the substrate 10 has an angle of 45 ° with respect to the traveling direction of the ultraviolet rays. And fix it. In this state, ultraviolet rays are irradiated from the back surface, and the resist is exposed by using the gate electrode 1 as a mask and projecting it at a position shifted by about 5000 ° from immediately above the gate. At this time, since the exposure amount per unit area is cos (θ), the exposure time needs to be multiplied by 1 / cos (θ). When rotated by 45 °, about 1.4 times the exposure time is required. Further, the substrate is rotated in the opposite direction and fixed so as to have a direction of -45 °, and ultraviolet light is again irradiated from the back surface for the same time, and the gate electrode 1 is used as a mask.
The resist is exposed by projecting at a position shifted by 5000 °. 2
The pattern left by the development after the second exposure is a common portion of the area not exposed by the two exposures. this is,
This is a pattern that has entered about 5000 ° from both sides of the gate electrode 1. With this pattern, the first protective insulating film 7 is subjected to dry etching with high perpendicularity so as to prevent side etching. Thereby, the first protective insulating film 7 is formed in a self-aligned manner. Thereafter, the resist was stripped, and phosphorus was dosed at an acceleration voltage of 25 kV with a dose of 4 × 10 4
Implant only ¹⁵ dose / cm ² . This is the same as the condition described above. Thereafter, an amorphous silicon nitride thin film 500 # is formed as the second protective insulating film 8. After applying the resist, the resist is irradiated with ultraviolet light from the back surface by a usual method, and is exposed using the gate electrode 1 as a mask. With this pattern, the second protective insulating film 8 is etched.

After the resist is stripped, the natural oxide film formed on the surface of the amorphous silicon thin film 3 is removed with sufficiently diluted hydrofluoric acid, and a Cr thin film is immediately deposited by sputtering at a thickness of 500 °. This Cr thin film is etched into a pattern of the source / drain electrode 6. In the portion where the second protective insulating film does not remain by this process, the surface of the amorphous silicon thin film 3
Cr silicide 5 is formed and functions as a source / drain electrode.

In this state, unnecessary portions of the amorphous silicon thin film are removed by dry etching.

The TFT manufactured by the above process shows good characteristics as shown in FIG.

〔The invention's effect〕

As described above, by using the TFT structure manufactured according to the present invention particularly for a short-channel TFT, the OFF current can be reduced, and the reliability of the channel protective film can be improved. Very effective as a switching element for active matrix liquid crystal displays
The TFT could be created in a self-aligned manner.

[Brief description of the drawings]

1A is a cross-sectional view of one embodiment of the present invention, FIG. 1B is a plan view thereof, FIG. 2 is a cross-sectional view of a TFT having a conventional doping structure, and FIG. FIG. 4B is a diagram showing the state of diffraction of ultraviolet rays near the gate, FIG. 4B is a diagram showing the relationship between the distance from the boundary and the exposure, FIG. 4 is a diagram showing the relationship between the patterns of the two protective insulating films; FIG. 5 is a diagram showing the relationship between the two protective insulating films and the n ⁺ layer, FIG. 6 is a diagram showing one embodiment of the third invention, and FIG. FIG. 8 is a diagram showing the relationship, and FIG. 8 is a diagram showing characteristics of a TFT manufactured according to the present invention. In the figure, 1 ... gate electrode, 2 ... gate insulating film,
3 ... Amorphous silicon thin film, 4 ... n ⁺ layer, 5 ... Cr silicide, 6 ... Drain electrode or source electrode, 7 ...
First protective insulating film, 8 second protective insulating film, 10 glass substrate, 12 resist, 13 ultraviolet rays, 14 ultraviolet rays diffracted.

Claims (3)

(57) [Claims] 1. A gate electrode on an insulating substrate from a substrate side,
A gate insulating film and an amorphous silicon thin film are stacked and arranged in this order, and a first protective insulating film having a width smaller than the gate electrode width is arranged on a part of the amorphous silicon thin film immediately above the gate, and A second area which completely covers the protective insulating film and extends at least 500 ° in both directions of the source electrode and the drain electrode provided on both sides of the region immediately above the gate electrode, and has an area not exceeding the region directly above the gate electrode. A protective insulating film is provided on the first protective insulating film, the source electrode and the drain electrode are brought into contact with the amorphous silicon thin film which is not covered by the second protective insulating film, and the first protective insulating film is further covered. An amorphous silicon thin film which has not been doped with an impurity in an appropriate region not reaching the gate insulating film from the surface. 2. A gate electrode is formed on a surface of an insulating substrate, a gate insulating film, an amorphous silicon thin film, and a first protective insulating film are laminated, and a resist is applied to the surface of the first protective insulating film. By irradiating ultraviolet rays from the back surface, using the already formed gate electrode as a mask, the exposure time is controlled to form a slightly narrowed pattern of the gate electrode, and the first protective insulating film is etched using this pattern as a mask. After removing the resist, the first
Is performed by using the protective insulating film as a mask, doping impurities into the source / drain portions of the amorphous silicon thin film, further forming a second protective insulating film on the entire surface,
Resist is applied to the surface of the protective insulating film, and ultraviolet light is again irradiated from the back surface of the insulating substrate. Using the gate electrode already formed as a mask, the exposure time is sufficiently shorter than the exposure time of the first protective insulating film. Exposure is performed by setting the exposure time to a sufficient value to form a mask pattern. Thereafter, the second protective insulating film is etched, and the source electrode and the drain are formed on the surface of the amorphous silicon thin film doped with the exposed impurities. A method for manufacturing a thin-film field-effect transistor, comprising forming an electrode. 3. After forming a gate electrode on an insulating substrate, a gate insulating film, an amorphous silicon thin film, and a first protective insulating film are sequentially laminated, and a resist is applied to the first protective insulating film. The substrate is rotated and fixed so that the direction of the normal line of the substrate has a certain angle with respect to the traveling direction of the ultraviolet ray with the center line as the rotation axis, and the ultraviolet ray is irradiated from the back surface of the substrate, and then the substrate is further irradiated. The substrate is rotated and fixed so that the normal direction of the substrate has a certain angle in the opposite direction to the traveling direction of the ultraviolet light, and the gate electrode is irradiated with ultraviolet light from the back surface of the substrate twice. A thinner pattern is formed, the first protective insulating film is etched using this pattern as a mask, the resist is removed, and then the exposed amorphous silicon thin film is doped with impurities by ion implantation. Second A protective insulating film and a resist are sequentially formed, the resist is patterned by being exposed from the back surface of the substrate, the second protective insulating film is etched using the pattern as a mask, the resist is removed, and then the amorphous silicon doped with the exposed impurities is removed. A method for manufacturing a thin film field effect transistor, comprising forming a source electrode and a drain electrode on a thin film surface.