KR100670039B1 - Method for manufacturing polycrystalline silicon thin film transistor having LED region - Google Patents
Method for manufacturing polycrystalline silicon thin film transistor having LED region Download PDFInfo
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- KR100670039B1 KR100670039B1 KR1019980011154A KR19980011154A KR100670039B1 KR 100670039 B1 KR100670039 B1 KR 100670039B1 KR 1019980011154 A KR1019980011154 A KR 1019980011154A KR 19980011154 A KR19980011154 A KR 19980011154A KR 100670039 B1 KR100670039 B1 KR 100670039B1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 46
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 238000000034 method Methods 0.000 title claims description 16
- 239000010408 film Substances 0.000 claims abstract description 37
- 150000002500 ions Chemical class 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 239000003504 photosensitizing agent Substances 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 abstract description 11
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
다결정 규소 박막 트랜지스터의 제조 방법에 있어서, 절연 기판 위에 바탕 절연막을 적층하고, 바탕 절연막 위에 다결정 규소 조각을 형성하고, 다결정 규소 조각 위에 제1 및 제2 게이트 절연막을 적층한다. 제2 게이트 절연막 위에 게이트 금속을 적층하고 게이트 금속층 위에 감광제를 도포, 노광, 현상한 다음, 습식 식각하여 게이트 전극을 형성한다. 게이트 전극 형성시에 식각 차단층으로 사용된 감광제를 다시 식각 차단층으로 사용하여 제2 게이트 절연막을 건식 식각한 후, 다결정 규소 조각에 불순물 이온을 고농도로 주입한다. 이렇게 하면, LDD 영역 형성을 위해 추가되었던 감광제의 도포, 노광, 현상 공정이 생략되어 생산성을 향상시킬 수 있다.In the method for producing a polycrystalline silicon thin film transistor, a base insulating film is laminated on an insulating substrate, a polycrystalline silicon piece is formed on the base insulating film, and first and second gate insulating films are laminated on the polycrystalline silicon piece. A gate metal is laminated on the second gate insulating layer, a photosensitive agent is applied, exposed, and developed on the gate metal layer, and then wet-etched to form a gate electrode. After the second gate insulating film is dry-etched by using the photoresist used as the etch stop layer again when forming the gate electrode as the etch stop layer, impurity ions are injected into the polycrystalline silicon pieces at a high concentration. This eliminates the application, exposure, and development of the photosensitive agent added for the LDD region formation, thereby improving productivity.
Description
이 발명은 다결정 규소 박막 트랜지스터의 제조 방법에 관한 것으로서, 더 자세하게는 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a polycrystalline silicon thin film transistor, and more particularly, to a method of forming an LDD region of a polycrystalline silicon thin film transistor.
다결정 규소 박막 트랜지스터는 비정질 규소 박막 트랜지스터에 비해 트랜지스터로서의 성능이 우수하여 액정 표시 장치용 박막 트랜지스터 기판을 다결정 규소 박막 트랜지스터를 적용하여 제작할 경우 구동 회로를 직접 기판 위에 형성할 수 있는 장점이 있다. 그러나 다결정 규소 박막 트랜지스터는 누설 전류(leak current)가 큰 단점이 있다. 누설 전류가 크면 액정 표시 장치의 화소 전극과 공통 전극 사이의 전압차가 시간이 지남에 따라 급격히 감소하여 액정 표시 장치의 화질이 떨어진다. 다결정 규소 박막 트랜지스터에서 누설 전류가 큰 이유는 다결정 규소의 결정립 경계(grain boundary)에 있는 트랩(trap)에 전자가 쉽게 포획되기 때문이다. 이러한 누설 전류를 감소시키기 위한 수단으로 수소 플라즈마 처리, 더블 게이트(double gate) 구조 또는 LDD(lightly doped drain) 구조 등이 사용되고 있으며, 이중에서 가장 일반적으로 사용되는 LDD 구조는 다결정 규소의 고농도로 도핑된 드레인 영역과 도핑되지 않은 채널 영역 사이에 드레인 영역과 같은 형의 불순물로 저농도로 도핑된 영역을 형성하여 드레인 영역과 채널 영역 사이의 전기장의 세기를 약화시킴으로써 누설 전류를 감소시키는 방법이다.The polysilicon thin film transistor has superior performance as a transistor compared to the amorphous silicon thin film transistor, and thus, when the thin film transistor substrate for a liquid crystal display device is manufactured by applying the polysilicon thin film transistor, the driving circuit can be directly formed on the substrate. However, polycrystalline silicon thin film transistors have a disadvantage in that leakage current is high. If the leakage current is large, the voltage difference between the pixel electrode and the common electrode of the liquid crystal display decreases rapidly with time, and thus the image quality of the liquid crystal display is degraded. The reason for the large leakage current in polycrystalline silicon thin film transistors is that electrons are easily trapped in traps at the grain boundaries of the polycrystalline silicon. As a means for reducing the leakage current, hydrogen plasma treatment, a double gate structure or a lightly doped drain (LDD) structure is used, and the most commonly used LDD structure is a highly doped polycrystalline silicon. A method of reducing leakage current by forming a lightly doped region with an impurity of the same type as the drain region between the drain region and the undoped channel region to weaken the strength of the electric field between the drain region and the channel region.
이제, 도면을 참고로 하여 종래의 기술에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법에 관하여 설명한다. Now, a method of forming an LDD region of a polysilicon thin film transistor according to the related art will be described with reference to the drawings.
도 1a 내지 도 1e는 종래의 기술에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법을 나타내는 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming an LDD region of a polysilicon thin film transistor according to the related art.
절연 기판(1) 위에 바탕 절연막(2)을 적층하고, 바탕 절연막(2)위에 다결정 규소 조각(3)을 형성한 다음, 제1 및 제2 게이트 절연막(4, 5)을 차례로 적층한다. 제2 게이트 절연막(5) 위에 금속층을 적층하고, 금속층 위에 감광제(7)를 도포, 노광, 현상한 후, 금속층을 습식 식각하면, 도 1a에 나타난 바와 같은 형태로 제2 게이트 절연막(5) 위에 게이트 전극(6)이 형성되고 게이트 전극(6) 위에는 감광제(7)가 잔류하게 된다. 다음, 도 1b와 같이, 게이트 전극(6) 위에 잔류하는 감광제(7)를 제거하고, 다시 감광제를 도포, 노광, 현상하고 제2 게이트 절연막(5)을 식각하여 비정질 규소 조각(3)의 LDD 영역이 형성될 부분 상부에만 제2 게이트 절연막(5)이 남도록 한다. 이어서, 도 1d에 나타낸 바와 같이, n+ 이온을 기판(1) 전면에 주입하면, 도 1e에 나타낸 바와 같이, 다결정 규소 조각(3)에 이온이 저농도로 도핑된 LDD 영역과 고농도로 도핑된 드레인 영역이 형성된다. The base insulating film 2 is laminated on the insulating substrate 1, the polycrystalline silicon pieces 3 are formed on the base insulating film 2, and the first and second gate insulating films 4 and 5 are laminated in this order. After laminating a metal layer on the second gate insulating film 5, applying, exposing and developing the photosensitive agent 7 on the metal layer, and wet etching the metal layer, the metal layer is formed on the second gate insulating film 5 in the form as shown in FIG. 1A. The gate electrode 6 is formed and the photosensitive agent 7 remains on the gate electrode 6. Next, as shown in FIG. 1B, the photoresist 7 remaining on the gate electrode 6 is removed, and the photoresist is again applied, exposed, and developed to etch the second gate insulating film 5 to etch the LDD of the amorphous silicon piece 3. The second gate insulating layer 5 remains only on the portion where the region is to be formed. Subsequently, as shown in FIG. 1D, when n + ions are implanted into the entire surface of the substrate 1, as shown in FIG. 1E, the LDD region in which the polycrystalline silicon pieces 3 are doped with low concentration and the drain region in which the ion is heavily doped is shown. Is formed.
이러한 종래의 LDD 영역 형성 방법에서는 LDD 영역 형성을 위해 사진 식각 공정이 한 번 추가되고, 따라서 생산성이 떨어진다.In the conventional LDD region formation method, a photolithography process is added once to form the LDD region, and thus productivity is lowered.
본 발명이 이루고자 하는 기술적 과제는 다결정 규소 박막 트랜지스터의 생산성을 높이는 것이다.The technical problem to be achieved by the present invention is to increase the productivity of the polycrystalline silicon thin film transistor.
위와 같은 과제를 해결하기 위하여 본 발명에서는 다음과 같은 다결정 규소 박막 트랜지스터 제조 방법을 제안한다.In order to solve the above problems, the present invention proposes the following polycrystalline silicon thin film transistor manufacturing method.
절연 기판 위에 다결정 규소 조각을 형성하고, 그 위에 제1 및 제2 게이트 절연막을 차례로 적층하고, 제2 게이트 절연막 위에 습식 식각 방법을 사용하여 게이트 전극을 형성한다. 게이트 전극 형성시에 식각 차단층으로 사용한 감광제를 다시 식각 차단층으로 하여 제2 게이트 절연막을 건식 식각하고, 감광제를 제거하고, 다결정 규소 조각에 고농도로 불순물 이온을 주입한다.A polysilicon piece is formed on the insulating substrate, first and second gate insulating films are sequentially stacked thereon, and a gate electrode is formed on the second gate insulating film using a wet etching method. The second gate insulating film is dry-etched using the photoresist used as the etch stop layer at the time of forming the gate electrode again as the etch stop layer, the photoresist is removed, and impurity ions are implanted at high concentration into the polysilicon pieces.
이 때, 다결정 규소 조각을 형성하기 이전에 절연 기판 위에 바탕 절연막을 더 형성할 수 있고, 주입하는 불순물 이온은 N형 불순물일 수 있다.At this time, the base insulating film may be further formed on the insulating substrate before forming the polycrystalline silicon pieces, and the implanted impurity ions may be N-type impurities.
또는, 절연 기판 위에 다결정 규소 조각을 형성하고, 그 위에 게이트 절연막을 적층하고, 게이트 절연막 위에 습식 식각 방법을 사용하여 게이트 전극을 형성한다. 게이트 전극 형성시에 식각 차단층으로 사용한 감광제를 이온 주입 차단층으로 사용하여 다결정 규소 조각에 고농도로 불순물 이온을 주입하고, 감광제를 제거한 다음 다시 저농도로 불순물 이온을 주입한다.Alternatively, a piece of polycrystalline silicon is formed on an insulating substrate, a gate insulating film is laminated thereon, and a gate electrode is formed on the gate insulating film using a wet etching method. When the gate electrode is formed, a photoresist used as an etch blocking layer is used as an ion implantation blocking layer to inject high concentrations of impurity ions into the polycrystalline silicon pieces, remove the photosensitive agent, and then implant impurity ions at a low concentration.
이 때, 다결정 규소 조각을 형성하기 이전에 절연 기판 위에 바탕 절연막을 더 형성할 수 있고, 주입하는 불순물 이온은 N형 불순물일 수 있다.At this time, the base insulating film may be further formed on the insulating substrate before forming the polycrystalline silicon pieces, and the implanted impurity ions may be N-type impurities.
이렇게 하면, LDD 영역 형성을 위해 추가되었던 감광제의 도포, 노광, 현상 공정을 생략할 수 있다.In this way, the application, exposure and development processes of the photosensitive agent added for the LDD region formation can be omitted.
이제 첨부한 도면을 참고로 하여, 본 발명의 실시예에 대하여 상세히 설명한다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b는 본 발명의 제1 실시예에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법을 나타내는 단면도이다.2A to 2B are cross-sectional views illustrating a method of forming an LDD region of a polysilicon thin film transistor according to a first embodiment of the present invention.
절연 기판(10) 위에 산화 규소 등을 적층하여 바탕 절연막(20)을 형성하고, 바탕 절연막(20) 위에 비정질 규소를 증착하고 레이저를 조사하여 결정화하여 다결정 규소로 만든 후, 패터닝(patterning)하여 다결정 규소 조각(30)을 형성한다. 다결정 규소 조각(30) 위에 산화 규소 등을 증착하여 제1 게이트 절연막(40)을 적층하고, 산화 탄탈륨(TaOx) 등을 증착하여 제2 게이트 절연막(50)을 적층한다. 제2 게이트 절연막(50) 위에 티타늄 등으로 이루어진 게이트 금속을 증착하고, 게이트 금속 위에 감광제(70)를 도포, 노광, 현상한 다음, 게이트 금속을 습식 식각을 하여, 도 2a에 나타낸 바와 같이, 다결정 규소 조각(30) 중앙 상부의 제2 게이트 절연막(50) 위에 게이트 전극(60)을 형성한다. 이 때, 게이트 전극(60) 위에는 감광제(70)가 잔류하는데, 게이트 금속을 습식 식각하는 경우 등방성 식각이 되어 게이트 전극(60)은 감광제(70)보다 조금 더 좁은 폭을 가진다. The base insulating film 20 is formed by stacking silicon oxide or the like on the insulating substrate 10, depositing amorphous silicon on the base insulating film 20, irradiating with laser to crystallize the polycrystalline silicon, and then patterning and polycrystalline. Silicon pieces 30 are formed. The first gate insulating film 40 is deposited by depositing silicon oxide or the like on the polycrystalline silicon piece 30, and the second gate insulating film 50 is deposited by depositing tantalum oxide (TaOx) or the like. After depositing a gate metal made of titanium or the like on the second gate insulating film 50, applying, exposing and developing the photosensitive agent 70 on the gate metal, wet etching the gate metal, and as shown in FIG. 2A, a polycrystal The gate electrode 60 is formed on the second gate insulating film 50 at the center of the silicon piece 30. At this time, the photoresist 70 remains on the gate electrode 60. When the gate metal is wet etched, the photoresist 70 is isotropically etched so that the gate electrode 60 has a narrower width than the photoresist 70.
다음, 게이트 전극(60) 위의 감광제(70)를 식각 차단층으로 이용하여 제2 게이트 절연막(50)을 건식 식각하면, 도 2b에 나타낸 바와 같이, 게이트 전극(60)하부의 제2 게이트 절연막(50)만 남고 나머지 부분은 제거된다. 이 때, 제2 게이트 절연막(50)은 게이트 전극(60)보다 조금 더 넓은 폭을 가진다. Next, when the second gate insulating film 50 is dry etched using the photoresist 70 on the gate electrode 60 as an etch stop layer, as shown in FIG. 2B, the second gate insulating film under the gate electrode 60 is shown. Only 50 remains and the rest are removed. In this case, the second gate insulating layer 50 has a width slightly wider than that of the gate electrode 60.
다음, 도 2c에 나타낸 바와 같이, 감광제(70)를 제거하고 고농도로 불순물 이온을 주입하면, 다결정 규소 조각(30)의 제1 게이트 절연막(40)만으로 덮여 있는 부분은 불순물 이온에 의해 고농도로 도핑되고, 제2 게이트 절연막(50)도 덮여 있는 부분은 제2 게이트 절연막(50)에 의해 불순물 이온의 일부가 흡수되어 저농도로 도핑된다. 이 때, 제2 게이트 절연막(50)의 두께를 조절하면 이온 주입 조건이 고정되어 있더라도 LDD 영역의 이온 농도를 조절할 수 있다. 불순물 이온은 N형이나 P형 어느 것을 사용하여도 무방하나 N형 불순물을 사용하는 것이 보통이다.Next, as shown in FIG. 2C, when the photosensitive agent 70 is removed and impurity ions are implanted at a high concentration, the portion covered with only the first gate insulating film 40 of the polysilicon piece 30 is doped at high concentration by impurity ions. The portion covered with the second gate insulating film 50 is absorbed by the second gate insulating film 50 so that a part of the impurity ions are absorbed at low concentration. In this case, by adjusting the thickness of the second gate insulating layer 50, the ion concentration of the LDD region may be adjusted even if the ion implantation conditions are fixed. Impurity ions may be either N-type or P-type, but N-type impurities are usually used.
이렇게 하면, 도 2d에 나타낸 바와 같은, LDD 구조를 가지는 다결정 규소 박막 트랜지스터를 형성할 수 있다. In this way, a polycrystalline silicon thin film transistor having an LDD structure as shown in FIG. 2D can be formed.
도 3a 내지 도 3c는 본 발명의 제2 실시예에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법을 나타내는 단면도이다.3A to 3C are cross-sectional views illustrating a method of forming an LDD region of a polysilicon thin film transistor according to a second exemplary embodiment of the present invention.
절연 기판(100) 위에 산화 규소 등을 적층하여 바탕 절연막(200)을 형성하고, 바탕 절연막(200) 위에 비정질 규소를 적층하고 열처리하여 다결정 규소로 만든 후, 다결정 규소층을 패터닝하여 다결정 규소 조각(300)을 형성한다. 다결정 규소 조각(300) 위에 산화 규소 등을 적층하여 게이트 절연막(400)을 형성하고, 게이트 절연막(400) 위에 티타늄 등으로 이루어진 게이트 금속을 적층하고, 게이트 금속층 위에 감광제를 도포하고 패터닝한 후, 게이트 금속층을 습식 식각하면, 도 3a 나타낸 바와 같이, 게이트 전극(600)이 형성된다. 이 때, 게이트 전극(600)의 위에는 게이트 전극(600)보다 조금 더 넓은 폭을 가지는 감광제(700)가 잔류하는데, 이 상태에서 불순물 이온을 고농도로 주입하면, 다결정 규소 조각(300) 중에서 감광제(700)에 의해 이온 침투가 차단되어 있지 않은 부분만 고농도로 이온 도핑된다. The base insulating film 200 is formed by stacking silicon oxide or the like on the insulating substrate 100, and the amorphous silicon is laminated and heat treated on the base insulating film 200 to form polycrystalline silicon, and then the polycrystalline silicon layer is patterned to form a polycrystalline silicon piece ( 300). After depositing silicon oxide or the like on the polycrystalline silicon piece 300 to form a gate insulating film 400, laminating a gate metal made of titanium or the like on the gate insulating film 400, applying and patterning a photoresist on the gate metal layer, and then When the metal layer is wet etched, the gate electrode 600 is formed as shown in FIG. 3A. At this time, a photoresist 700 having a width slightly wider than that of the gate electrode 600 remains on the gate electrode 600. When impurity ions are implanted at a high concentration in this state, the photoresist (among the polycrystalline silicon pieces 300) Only the portion where ion penetration is not blocked by 700 is ion-doped at high concentration.
다음, 도 3b에 나타낸 바와 같이, 감광제(700)를 모두 제거하고, 불순물 이온을 저농도로 주입하면, 도 3c에 나타낸 바와 같이, 감광제(700)에 의해 이온 침투가 차단되어 있던 다결정 규소 조각(300)의 부분 중에서 게이트 전극(600)에 의해 차단되어 있지 않은 부분에 저농도로 도핑된 영역이 형성되어 LDD 영역을 이룬다.Next, as shown in FIG. 3B, when all of the photosensitive agent 700 is removed and impurity ions are implanted at low concentration, as shown in FIG. 3C, the polycrystalline silicon piece 300 in which ion permeation is blocked by the photosensitive agent 700 is blocked. A lightly doped region is formed in a portion of the C) that is not blocked by the gate electrode 600 to form an LDD region.
본 발명과 같이 다결정 규소 박막 트랜지스터의 LDD 영역을 형성하면, LDD 영역 형성을 위해 추가되었던 감광제의 도포, 노광, 현상 공정이 생략되어 생산성을 향상시킬 수 있다.If the LDD region of the polysilicon thin film transistor is formed as in the present invention, the application, exposure, and development of the photosensitive agent added for forming the LDD region may be omitted, thereby improving productivity.
도 1a 내지 도 1e는 종래의 기술에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법을 나타내는 단면도이고,1A to 1E are cross-sectional views illustrating a method of forming an LDD region of a polysilicon thin film transistor according to the prior art,
도 2a 내지 도 2d는 본 발명의 제1 실시예에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법을 나타내는 단면도이고,2A to 2D are cross-sectional views illustrating a method for forming an LDD region of a polysilicon thin film transistor according to a first embodiment of the present invention.
도 3a 내지 도 3c는 본 발명의 제2 실시예에 따른 다결정 규소 박막 트랜지스터의 LDD 영역 형성 방법을 나타내는 단면도이다.3A to 3C are cross-sectional views illustrating a method of forming an LDD region of a polysilicon thin film transistor according to a second exemplary embodiment of the present invention.
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| KR101006439B1 (en) | 2003-11-12 | 2011-01-06 | 삼성전자주식회사 | Method for manufacturing of Thin film transistor array panel |
| KR102442615B1 (en) | 2015-07-09 | 2022-09-14 | 삼성디스플레이 주식회사 | Method of fabricating thin film transistor substrate |
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| JPH05152325A (en) * | 1991-12-02 | 1993-06-18 | Matsushita Electric Ind Co Ltd | Manufacturing method of thin film transistor |
| JPH06333948A (en) * | 1993-05-25 | 1994-12-02 | Mitsubishi Electric Corp | Thin film transistor and its manufacture |
| JPH07169965A (en) * | 1992-12-01 | 1995-07-04 | Paradigm Technol Inc | Semiconductor device and manufacture thereof |
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| KR19980084467A (en) * | 1997-05-23 | 1998-12-05 | 구자홍 | Liquid Crystal Display Manufacturing Method |
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| JPH05152325A (en) * | 1991-12-02 | 1993-06-18 | Matsushita Electric Ind Co Ltd | Manufacturing method of thin film transistor |
| JPH07169965A (en) * | 1992-12-01 | 1995-07-04 | Paradigm Technol Inc | Semiconductor device and manufacture thereof |
| JPH06333948A (en) * | 1993-05-25 | 1994-12-02 | Mitsubishi Electric Corp | Thin film transistor and its manufacture |
| JPH09191111A (en) * | 1995-11-07 | 1997-07-22 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| KR19980084467A (en) * | 1997-05-23 | 1998-12-05 | 구자홍 | Liquid Crystal Display Manufacturing Method |
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| CN104658905A (en) * | 2015-02-27 | 2015-05-27 | 深圳市华星光电技术有限公司 | Etching method and substrate |
| WO2016134558A1 (en) * | 2015-02-27 | 2016-09-01 | 深圳市华星光电技术有限公司 | Etching method and substrate |
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