JP3163844B2 - Method of manufacturing inverted staggered thin film field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film field effect transistor used for a matrix display device or a contact type image sensor.

[0002]

2. Description of the Related Art A technique for forming a thin film transistor using a silicon thin film on an insulating substrate such as glass is important as a central technique for forming an active matrix liquid crystal display device. In order to improve the performance of an active matrix liquid crystal display device, a higher performance of a thin film field effect transistor (hereinafter referred to as a TFT) as a switching element of a pixel is required. As one of the measures, it has been proposed that the TFT is made self-aligned to reduce the alignment load of the photolithography process, to reduce the parasitic capacitance and shorten the channel of the TFT.

[0003] A so-called inverted staggered TFT in which a gate electrode is disposed on a substrate side and source / drain electrodes are disposed on a semiconductor thin film layer is generally used today.
It is. As a method of forming a gate electrode and a source / drain electrode in a self-aligned manner with this structure, an insulating film (passivation film) for passivation of a channel region is formed in a self-aligned manner by performing back exposure using the gate electrode as a mask. Then, ion implantation is performed using this as a mask to selectively form an n-type impurity introduction as an amorphous silicon thin film source / drain region, and then a metal such as chromium (Cr) is deposited to form an n-type impurity introduction region. A method has been proposed in which the surface portion is silicided to reduce the resistance and use it as a source / drain electrode. In this method, the delicate alignment between the gate electrode and the source / drain electrode is formed in a self-aligned manner by using the backside exposure, so that the overlap can be precisely controlled and the parasitic capacitance can be kept low. Can be.

[0004]

When the above-mentioned TFT is used in an active matrix liquid crystal display device, as shown in FIG. In most cases from the back channel side. Since this incident light generates carriers inside the amorphous silicon film, the current increases accordingly. In particular, when a negative voltage is applied to the gate electrode 2, the channel is depleted in the dark state, the drain current is suppressed to a very low level, and a so-called OFF state is obtained.
When light is irradiated, the OFF current is greatly increased by photo carriers.

[0005] The increase in the OFF current is a major obstacle to the TFT functioning as a switching element.
For example, an equivalent circuit of one pixel of a liquid crystal display is as shown in FIG. At this time, the capacity is 0.050 pf, O
Assuming that the FF resistance is 10 ¹² Ω, the time constant of this equivalent circuit is 50 ms, which is equivalent to the frame period. When the OFF current flows in this manner, the charge retention is insufficient and the luminance deviates from the set luminance, and it becomes difficult to control the luminance of the screen.

An object of the present invention is to provide a method for manufacturing an inverted staggered type TET having a small OFF current.

[0007]

According to the present invention, there is provided a method of manufacturing a reverse staggered thin film field effect transistor, comprising the steps of: forming a light-shielding gate electrode on one surface of a transparent insulating substrate;
After depositing a gate insulating film on one surface of the transparent insulating substrate to cover the gate electrode, sequentially depositing a non-doped amorphous silicon film and an amorphous silicon nitride film,
A photoresist step of applying a photoresist film on the amorphous silicon nitride film and exposing the photoresist from the other surface of the transparent insulating substrate using the light-shielding gate electrode as a mask; and Forming a channel protective film by selectively removing the amorphous silicon nitride film using the patterned photoresist film as a mask; and forming at least a surface of the amorphous silicon film pattern using the channel protective film as a mask. Forming a pair of impurity-introduced regions selectively in the portion, and sequentially covering the amorphous silicon film pattern with a first insulating layer, a non-doped amorphous silicon layer, and a second insulating layer. Applying a photoresist film on the second insulating layer, in a direction from the surface opposite to the one surface of the transparent insulating substrate to the one surface. A photoresist step of exposing and exposing the photoresist film by using the gate electrode as a mask, and the second insulating layer, the non-doped amorphous silicon layer, and the first insulating layer using the resist pattern as a mask. Forming a channel protective film composed of a first insulating layer, a non-doped amorphous silicon layer, and a second insulating layer by sequentially etching the first insulating layer, the non-doped amorphous silicon layer, and the second insulating layer. A method of manufacturing an inverted staggered thin film field effect transistor, wherein the non-doped amorphous silicon layer has a thickness of 10 to 50 nm.

[0008]

The light incident from the back channel side is considerably absorbed by the non-doped amorphous silicon layer for channel protection. Although the absorption coefficient of non-doped amorphous silicon varies considerably depending on the film quality and the wavelength of incident light, it is generally about 5 × 10 ⁵ cm ⁻¹ for visible light. At this time, if the thickness of the non-doped amorphous silicon layer is 50 nm, the transmittance of this layer becomes about 1/10.

The generation of photocarriers is almost proportional to the intensity of incident light. When the intensity of transmitted light is reduced to 1/10, the amount of photocarriers is reduced to 1/10. so it can be suppressed to about 1/10 of no layer T F T. C ₁ is smaller than the capacitance C ₂ between the gate electrode 8 and the gate electrode 12. When the distance between the gate electrode 8 and the gate electrode 12 is 0.6 μm, the conventional floating diffusion layer capacitance 0.02PF is:
It could be reduced to 0.014 PF or less. That is, it is apparent that the detection sensitivity is improved by 30% or more.

At this time, although photocarriers are generated inside the non-doped amorphous silicon layer, they have high resistance,
Moreover, since it is not a dielectric, polarization and fixed charge hardly affect the potential distribution inside the TFT.

On the other hand, when this structure is formed, a non-doped amorphous silicon layer is sandwiched between two insulating layers when forming a channel protective film, except that a normal self-aligned structure is formed. It can be formed in exactly the same way as the staggered TFT process.

Further, the non-doped amorphous silicon layer (light-shielding layer) thus manufactured is formed in a self-aligned manner with respect to the channel region of the TFT. As a result, no extra parasitic capacitance is generated.

[0013]

FIG. 1 is a sectional view showing an inverted staggered type TFT according to an embodiment of the present invention.

In this embodiment, a gate electrode 2 for selectively covering one surface of a transparent insulating substrate (glass substrate 1) and a gate electrode 2 for covering the gate electrode 2 and covering at least a predetermined region on one surface of the glass substrate 1 are provided. Gate insulating film 3 and gate electrode 2
Non-doped amorphous silicon film (non-doped a-Si: H film 5) selectively deposited on the gate insulating film 3 to intersect with
And a pair of n-type impurity introduction regions 4-1 and 4-1 selectively formed at least on the surface of the non-doped a-Si: H film 5.
4-2, a first insulating layer 8 covering a region between the pair of n-type impurity introduction regions 4-1 and 4-2 of the non-doped a-Si: H film 5, and a non-doped amorphous silicon layer ( Non-doped a-Si: H layer 9) for shielding light and second insulating layer 1
And a three-layer channel protective film made of zero.

Next, the manufacturing method of this embodiment will be described.

First, as shown in FIG. 2A, a chromium film is formed on a glass substrate 1 by a 150 nm sputtering method, a resist pattern of a gate electrode is formed by photolithography, and chromium is etched and patterned. A stripe-shaped gate electrode 2 having a width of 6 μm is formed.

Further, a 400 nm-thick silicon nitride film is deposited as a gate insulating film 3 thereon using a plasma CVD method as shown in FIG. Next, the non-doped amorphous silicon film (a-Si: H film 5) is reduced to 50 n by decomposing the SiH ₄ gas in the glow discharge plasma.
m. Next, an amorphous silicon nitride film 11 is deposited to a thickness of 250 nm by a plasma CVD method.

Here, a positive photoresist is applied, and ultraviolet light having a wavelength of 435 nm is irradiated from the back surface of the glass substrate 1. At this time, the gate electrode 2 functions as a mask, but as shown in FIG. 2C, excessive exposure is performed to form the photoresist film 12 on a pattern in which the gate electrode is narrowed. For example, the thickness of the photoresist film 12 is 1.5 μm.
, The irradiation light intensity is 7 mW / cm ² , and the exposure time is 7
Minutes and the development time is 2 minutes.

[0019] The photoresist film 12 amorphous silicon nitride film 11 as a mask to etch in g by dilute hydrofluoric acid. As a result, as shown in FIG. 2D, a striped channel protective film 11a having a width of 5 μm is formed in a self-aligned manner with respect to the gate electrode 2.

After stripping the resist, phosphorus ions are implanted at 30 kv by 4 × 10 15 / cm 2 by ion implantation. In this case, as shown in FIG.
The region of the Si: H film 5 that is not covered with the channel protective film 11a is doped with phosphorus and is doped with an n-type impurity doped region 4.
-1 and 4-2 are formed. On the other hand, doping is not performed in a region covered with the channel protective film 11a. Thus, the source / drain regions (4-
1,4-2) is formed in a self-aligned manner with respect to the gate electrode.

Thereafter, the channel protective film 11 is diluted with dilute hydrofluoric acid.
a is removed, and a channel protective film is formed again using the plasma CVD method. That is, as shown in FIG. 2F, a first insulating layer 8 (amorphous silicon nitride film having a thickness of 50 nm), an a-Si: H layer 9 and a second insulating layer 10 (a 50 nm thick film). Amorphous silicon nitride film) by plasma CVD
It is formed continuously by the method. The thickness of the a-Si: H layer 9 is at least 10 nm, preferably 30 nm.

Here, a positive photoresist is applied,
Ultraviolet light is again irradiated from the back surface of the glass substrate 1 to project a gate electrode pattern. At this time, the exposure time and the development time are controlled so that the photoresist film is slightly wider than the photoresist film 12 formed by the first back exposure. For example, when the thickness of the photoresist film is the same, the intensity of irradiation light is 7 mW / cm 2, the exposure time is 4 minutes and 30 seconds, and the development time is 1 minute and 20 seconds.

Using this resist film as a mask, the second
The insulating layer 8, the a-Si: H layer 9, and the first insulating film 8 are successively dry-etched to form a 5.7 μm-wide striped channel protective film as shown in FIG. 11b is formed.

Thereafter, the surface was treated with dilute hydrofluoric acid, a chromium film of 200 nm was deposited, and chromium silicide layers 7-1 and 7-2 were formed as shown in FIG. Pattern the chromium film to
The drain metal layers 6-1 and 6-2 are formed.

Next, as shown in FIG. 2I, a 200 nm passivation silicon nitride film 13 is deposited so as to cover the entire TFT through a step of patterning the semiconductor layer into an island shape.

As shown in FIG. 1, in the TFT thus manufactured, the region where the channel of the TFT is formed is a-S.
FIG. 5 (drain voltage 1
As shown in a graph showing drain current versus gate voltage characteristics at 0 V, the off-state current when light is irradiated from the back channel side is obtained by comparing curve 23 (conventional example) with curve 24 (one embodiment). As can be seen, the size can be reduced by about one to two digits.

[0027]

In general, in an active matrix liquid crystal display, stray light from a backlight or the like is incident on a back channel of a TFT, and display quality is deteriorated due to a decrease in resistance when the TFT is turned off. When a cell array is formed using the TFT of the present invention, a decrease in resistance at the time of off is suppressed by about one to two digits, and there is an effect that remarkable improvement can be seen against such a deterioration in display quality.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an inverted staggered TFT according to one embodiment of the present invention.

FIGS. 2A to 2C are diagrams for explaining a manufacturing method according to an embodiment;
It is a process order sectional view divided and shown to (i).

FIG. 3 is a schematic sectional view of an active matrix liquid crystal display device using an inverted staggered TFT.

FIG. 4 is an equivalent circuit diagram of one pixel of the active matrix liquid crystal display element.

FIG. 5 is a graph showing that an increase in off-state current when light enters the inverted staggered TFT T of the present invention from the back channel side is suppressed as compared with a conventional transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate electrode 3 Gate insulating film 4-1 and 4-2 n-type impurity introduction region 5 Non-doped a-Si: H layer 6-1 and 6-2 Source / drain metal layer 7 Metal silicide film 8 First Insulating film 9 Non-doped a-Si: H layer for shading 10 Second insulating film 11 Amorphous silicon nitride film 11a, 11b Channel protective film 12 Photoresist film 13 Silicon nitride film 14 Counter substrate 15 Illumination light 16 Liquid crystal 17 Capacity REFERENCE SIGNS LIST 18 common voltage terminal 19 TFT 20 scanning line 21 signal line 22 dark characteristic 23 characteristic curve at the time of conventional light irradiation 24 characteristic curve at the time of light irradiation of TFT according to the present invention

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (3)

(57) [Claims] A step of forming a light-shielding gate electrode on one surface of a transparent insulating substrate; and a step of forming a gate insulating film on one surface of the transparent insulating substrate to cover the gate electrode.
Later, non-doped amorphous silicon film and amorphous silicon nitride
Sequentially depositing a film and the amorphous silicon nitride film
Apply a photoresist film on top, and apply the photoresist
From the other surface of the transparent insulating substrate, the light-shielding gate
A photoresist step of exposing using the pole as a mask,
The photo patterned in a photoresist process
Select the amorphous silicon nitride film using the resist film as a mask
Forming the first channel protective film by removing the
The amorphous silicon is formed using the first channel protective film as a mask.
Selectively removing the rear forming a pair of impurity introduction region first channel protective film on at least a surface portion of the film,
A step of sequentially covering the amorphous silicon film with a first insulating layer, a non-doped amorphous silicon layer, and a second insulating layer; and coating a photoresist film on the second insulating layer. A photoresist for exposing and exposing the photoresist film by exposing from the surface opposite to the one surface of the transparent insulating substrate toward the one surface using the gate electrode as a mask.
A first insulating layer, a non-doped amorphous silicon layer by etching and removing the second insulating layer, the non-doped amorphous silicon layer, and the first insulating layer in this order using the resist pattern as a mask; Forming a channel protective film made of a second insulating layer, wherein the non-doped amorphous silicon layer has a thickness of 10 to 50 nm.
A method for manufacturing an inverted staggered type thin film field effect transistor, characterized by having a thickness of: 2. The method according to claim 1, wherein the impurity introduction region is formed so as to be self-aligned with the gate electrode. 3. The method of manufacturing an inverted staggered thin film field effect transistor according to claim 1, wherein a metal silicide layer is formed on the surface of the impurity introduction region in a self-aligned manner with the channel protective film.