JPH06350089A - Reverse staggered type thin film-field effect transistor - Google Patents

Abstract

PURPOSE:To reduce off-state current at the time light is applied without the generation of parasitic capacitance and to inhibit the polarization and effect of a fixed change on a back channel in a reverse staggered type self aligned TFT. CONSTITUTION:A channel protective film formed in self-alignment is in three layers of a first insulating 8, a Si:H film 9, and a second insulating layer 10 with respect to a gate electrode 2 in a reverse staggered self-aligned TFT. As a result, incident light to the channel is absorbed by the a-Si:H layer 9, thus inhibiting an increase in a photo off state current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film field effect transistor used for a matrix display device, a contact type image sensor and the like.

[0002]

2. Description of the Related Art A technique for forming a thin film transistor by using a silicon thin film on an insulating substrate such as glass is important as a central technique for forming an active matrix liquid crystal display device. In order to improve the performance of the active matrix liquid crystal display device, it is required to improve the performance of a thin film field effect transistor (hereinafter referred to as TFT) as a switching element of a pixel. As one of the measures, it has been proposed that the TFT be self-aligned to reduce the burden of alignment in the photolithography process and to reduce the parasitic capacitance and the channel of the TFT.

What is commonly used today is a so-called inverted staggered TFT in which the gate electrode is arranged on the substrate side and the source / drain electrodes are arranged above the semiconductor thin film layer.
Is. As a method of forming the gate electrode and the source / drain electrodes in a self-aligned manner with this structure, back surface exposure is performed using the gate electrode as a mask to form an insulating film (channel protective film) for passivation in the channel region in a self-aligned manner. Then, ion implantation is performed by using this as a mask to selectively form an n-type impurity introduction as an amorphous silicon thin film source / drain region, and then a metal such as chromium (Cr) is formed into a film to form an n-type impurity introduction region. There has been proposed a method of siliciding the surface portion of the to make the resistance low and using it as a source / drain electrode. In this method, since the delicate alignment between the gate electrode and the source / drain electrodes is formed in a self-aligned manner by using the backside exposure, the overlap can be precisely controlled and the parasitic capacitance can be kept low. You can

[0004]

When the above-mentioned TFT is used in an active matrix liquid crystal display device, illumination light enters from the back surface of the glass substrate 1 and light reflected on the counter substrate 14 side is reflected by the TFT as shown in FIG. Often comes from the back channel side. Since this incident light generates carriers inside the amorphous silicon film, the current increases accordingly. In particular, when a negative voltage is applied to the gate electrode 2, in the dark state, the channel is depleted, the drain current is suppressed to a very low level, and a so-called OFF state is obtained.
When irradiated with light, the photo carrier causes a large increase in the OFF current.

This increase in the OFF current is a major obstacle to the TFT functioning as a switching element.
For example, an equivalent circuit of one pixel of a liquid crystal display is as shown in FIG. At this time, the capacity is 0.050 pf, O
When the FF resistance is 10 ¹² Ω, the time constant of this equivalent circuit is 50 ms, which is equivalent to the frame period. When the OFF current flows in this way, charge retention becomes insufficient and the brightness deviates from the set brightness, making it difficult to control the brightness of the screen.

An object of the present invention is to provide an inverted staggered type TET with a small OFF current.

[0007]

An inverted staggered thin film field effect transistor according to the present invention comprises a gate electrode for selectively covering one surface of a transparent insulating substrate and the transparent insulating substrate for covering the gate electrode. A gate insulating film deposited on at least a predetermined region of the one surface, an amorphous silicon film intersecting the gate electrode and selectively deposited on the gate insulating film, and an amorphous silicon film. At least a pair of impurity introduced regions selectively formed on the surface and a first insulating layer that covers a region sandwiched by the pair of impurity introduced regions of the amorphous silicon film, a non-doped amorphous silicon layer And a channel protective film formed of the second insulating layer.

[0008]

The non-doped amorphous silicon layer for channel protection absorbs light incident from the back channel side. The absorption coefficient of non-doped amorphous silicon varies considerably depending on the film quality and the wavelength of incident light, but is usually about 5 × 10 ⁵ cm ^{−1 with} respect to visible light. At this time, if the thickness of the non-doped amorphous silicon layer is 50 nm, the transmittance of this layer becomes about 1/10.

The generation of photocarriers is almost proportional to the intensity of incident light. When the intensity of transmitted light becomes 1/10, the amount of photocarriers also becomes 1/10, and the OFF current at the time of light irradiation is non-doped amorphous silicon. It can be suppressed to about 1/10 of TET without a layer.

At this time, although photocarriers are generated inside the non-doped amorphous silicon layer, the resistance is high,
Moreover, since it is not a dielectric, polarization and fixed charges have almost no influence on the potential distribution inside the TFT.

On the other hand, in forming this structure, a reverse of a normal self-aligned structure is adopted except that a non-doped amorphous silicon layer is sandwiched between two insulating layers when forming a channel protective film. It can be manufactured in exactly the same process as the staggered type TFT.

Furthermore, the non-doped amorphous silicon layer (light-shielding layer) thus formed is formed in a self-aligned manner with respect to the channel region of the TFT. With this formation, it is added to the channel capacitance. Therefore, no extra parasitic capacitance is generated.

[0013]

FIG. 1 is a sectional view of an inverted staggered type TFT according to an embodiment of the present invention.

In this embodiment, a gate electrode 2 which selectively covers one surface of a transparent insulating substrate (glass substrate 1) and a gate electrode 2 which covers the surface of at least a predetermined region of the one surface of the glass substrate 1 are deposited. Gate insulating film 3 and gate electrode 2
Non-doped amorphous silicon film (non-doped a-Si: H film 5) selectively crossed with and deposited on the gate insulating film 3
And a pair of n-type impurity introduction regions 4-1 selectively formed on at least the surface portion of the non-doped a-Si: H film 5.
4-2, the first insulating layer 8 that covers the region sandwiched by the pair of n-type impurity introduction regions 4-1 and 4-2 of the non-doped a-Si: H film 5, the non-doped amorphous silicon layer ( Non-doped a-Si: H layer 9) for shading and second insulating layer 1
It has a three-layer channel protective film of 0.

Next, the manufacturing method of this embodiment will be described.

First, as shown in FIG. 2A, a chromium film is formed on a glass substrate 1 by a 150 nm sputtering method, a resist pattern of a gate electrode is formed by photolithography, and chromium is etched and patterned. A stripe-shaped gate electrode 2 having a width of 6 μm is formed.

Furthermore, a plasma CVD method is used to deposit a silicon nitride film as a gate insulating film 3 to a thickness of 400 nm as shown in FIG. 2 (b). Then, the non-doped amorphous silicon film (a-Si: H film 5) is depleted by 50 n by decomposing SiH ₄ gas in glow discharge plasma.
m. Next, an amorphous silicon nitride film 11 is deposited to a thickness of 250 nm by the plasma CVD method.

Here, a positive photoresist is applied, and ultraviolet light having a wavelength of 435 nm is irradiated from the back surface of the glass substrate 1. At this time, the gate electrode 2 acts as a mask, but as shown in FIG. 2C, the photoresist film 12 is formed in a pattern in which the gate electrode is thinned, so that excessive exposure is performed. For example, the thickness of the photoresist film 12 is 1.5 μm
, The irradiation light intensity is 7 mW / cm ² , and the exposure time is 7
Minutes, and the development time is 2 minutes.

The amorphous silicon nitride film 11 is etched with dilute hydrofluoric acid using the photoresist film 12 as a mask. As a result, as shown in FIG. 2D, the stripe-shaped channel protection film 11 a having a width of 5 μm is formed in self alignment with the gate electrode 2.

After stripping the resist, phosphorus ions are implanted at 30 kv by 4 × 10 15 / cm 2 by the ion implantation method. By doing so, as shown in FIG.
A region of the Si: H film 5 which is not covered with the channel protective film 11a is doped with phosphorus and the n-type impurity introduction region 4 is formed.
-1, 4-2 are formed. On the other hand, doping is not performed in the region covered with the channel protective film 11a. In this way, the source / drain regions (4-
1, 4-2) is formed in self-alignment with the gate electrode.

Thereafter, the channel protection film 11 is formed with diluted hydrofluoric acid.
After removing a, the channel protection film is formed again by using the plasma CVD method. That is, as shown in FIG. 2F, the first insulating layer 8 (amorphous silicon nitride film having a thickness of 50 nm), the a-Si: H layer 9 and the second insulating layer 10 (having a thickness of 50 nm). Amorphous silicon nitride film) plasma CVD
It is formed continuously by the method. The thickness of the a-Si: H layer 9 is at least 10 nm, preferably 30 nm.

Here, a positive photoresist is applied,
UV light is again irradiated from the back surface of the glass substrate 1 to project the gate electrode pattern. The exposure time and the development time are controlled so that the photoresist film at this time is slightly wider than the photoresist film 12 formed by the first back exposure. For example, when the photoresist films have the same thickness, the irradiation light intensity is 7 mW / cm @ 2, the exposure time is 4 minutes 30 seconds, and the development time is 1 minute 20 seconds.

Using the resist film as a mask, the second
2G, the insulating layer 8, the a-Si: H layer 9, and the first insulating film 8 are continuously dry-etched to form a striped channel protective film having a width of 5.7 μm as shown in FIG. 11b is formed.

Thereafter, this surface was treated with dilute hydrofluoric acid, and then a 200 nm chromium film was deposited to form chromium silicide layers 7-1 and 7-2 as shown in FIG. Source the chromium film by patterning
Drain metal layers 6-1 and 6-2 are formed.

Next, as shown in FIG. 2I, a 200 nm silicon nitride film 13 for passivation is deposited so as to cover the entire TFT through a step of patterning the semiconductor layer into an island shape.

In the TFT thus manufactured, as shown in FIG. 1, the region where the channel of the TFT is formed is aS.
i: Since it is covered with the H layer 9, as shown in FIG.
As shown in the graph showing the drain current vs. gate voltage characteristic at 0 V), the off current when light is irradiated from the back channel side is obtained by comparing the curve 23 (conventional example) with the curve 24 (one example). As can be seen, it can be reduced by about 1 to 2 digits from the conventional one.

[0027]

In general, in an active matrix liquid crystal display, stray light due to a backlight or the like is incident on the back channel of the TFT, and the display quality may be deteriorated due to a reduction in the resistance when the TFT is off. If the cell array is formed by using the TFT of the invention, there is an effect that a decrease in resistance when off is suppressed by about 1 to 2 digits and a remarkable improvement can be seen against such deterioration of display quality.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an inverted staggered type TFT according to an embodiment of the present invention.

2A to 2C are explanatory views of a manufacturing method according to an embodiment.
It is a process order sectional view divided and shown in (i).

FIG. 3 is a schematic cross-sectional view of an active matrix liquid crystal display element using an inverted staggered TFT.

FIG. 4 is an equivalent circuit diagram of one pixel of an active matrix liquid crystal display element.

FIG. 5 is a graph showing that an increase in off-current when light is incident on the inverted staggered TFT T of the present invention from the back channel side is suppressed as compared with a conventional transistor.

[Explanation of symbols]

 1 Glass Substrate 2 Gate Electrode 3 Gate Insulating Film 4-1, 4-2 n-type Impurity Introduction Region 5 Non-doped a-Si: H Layer 6-1, 6-2 Source / Drain Metal Layer 7 Metal Silicide Film 8 First Insulating film 9 Non-doped a-Si: H layer for light shielding 10 Second insulating film 11 Amorphous silicon nitride film 11a, 11b Channel protective film 12 Photoresist film 13 Silicon nitride film 14 Counter substrate 15 Illuminating light 16 Liquid crystal 17 Capacitance 18 common voltage terminal 19 TFT 20 scanning line 21 signal line 22 dark characteristic 23 conventional characteristic curve during light irradiation 24 characteristic curve during light irradiation of TFT according to the present invention

Claims (3)

[Claims] 1. A gate electrode that selectively covers one surface of a transparent insulating substrate, and a gate insulating film that covers the gate electrode and is deposited on at least a predetermined region of one surface of the transparent insulating substrate. An amorphous silicon film intersecting the gate electrode and selectively deposited on the gate insulating film, and a pair of impurity introduction regions selectively formed on at least a surface portion of the amorphous silicon film. And a channel protection film including a first insulating layer, a non-doped amorphous silicon layer, and a second insulating layer, which covers a region sandwiched by the pair of impurity introduction regions of the amorphous silicon film. Characteristic is an inverted staggered thin film field effect transistor. 2. The inverted staggered thin film field effect transistor according to claim 1, wherein the impurity introduction region and the channel protection film are arranged in a self-aligned manner with the gate electrode. 3. The inverted staggered thin film field effect transistor according to claim 1, wherein a metal silicide layer is formed on the surface of the impurity introduction region in a self-aligned manner with the channel protection film.