JPH11204802A - Manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve parasitic capacitance between a source electrode and pixel and feed-through voltage, greatly reduce variations of an element size between cells and performance, and reduce overall size of an element. SOLUTION: Radiant filter islands 112 are formed on a semiconductor substrate by the back side lithography. The radiant filter islands 112 permit a light at a wavelength in the lithography to pass through but reflect or do not permit a laser wavelength to pass through. By the laser-assisted doping method, a dopant is implanted in a source and drain regions 132, 134 to self-aligningly form the two regions. Then a source and drain electrodes are formed on the two regions, hence the overlap of the source electrode and the drain electrode with the gate region disappears, and a parasitic capacitance and a feed-type voltage can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Generally, in a bottom-gate transistor structure, a metal gate material is formed on a substrate. The substrate transmits ultraviolet (UV) light and does not transmit gate metal. An insulating layer is formed on the gate metal, and an active material layer for forming a channel is formed on the insulating layer. As an example of the active material layer, intrinsic hydrogenated amorphous silicon (a-
Si: H) or other similar materials. A nitride protective layer is deposited on the active material layer, and islands are formed from the protective layer in the next step. Each of these additional layers also generally transmits UV light. Next, a photoresist layer is formed on the protective layer. Thereafter, UV light is irradiated through the substrate, the insulating layer, the active material layer, and the protective layer. This UV
The light reaches the photoresist outside of the area shielded by the gate metal, exposing the photoresist. Then this U
The development of the photoresist in the region exposed by the V light is performed. The nitride protective layer is etched using the patterned photoresist as a mask. This etching is performed on all regions except for the portions where the exposure of the photoresist is shielded by the gate metal (except for some side etching). This forms a nitride protection island, which is delimited by the gate electrode. Hereinafter, the structure of this portion is referred to as “self-aligned”.

Next, a contact layer (for example, a-Si: H doped to be n +) is formed on each of the above layers. Followed by lithography (or other similar techniques)
Is used to roughly remove the portion of the contact layer located on the gate metal. Since it is difficult to selectively etch doped a-Si: H on intrinsic a-Si: H (i.e., remove the former and not remove the latter), the protective island on the surface layer is etched away with an etch-stop material. To form source and drain electrodes. The completed structure is shown in FIGS. 1 (a) and 1 (b). In the figure, a thin film transistor (TFT) 10 includes a substrate 12, a substrate 12
Gate metal 14, gate insulating layer 16, active layer 18, surface protection island 20, drain electrode 2 formed thereon
2 and a source electrode 24. However, doped a-Si: H and intrinsic a-
Since it is difficult to control the selective etching with Si: H, as shown in overlaps 28 and 30, only the previously doped a-Si: H is etched to provide a certain amount of doped a-Si: H. The a-Si: H was left so as to overlap the protection island 20. Therefore, the structure of this part is not self-aligned.

[0004] Intrinsic a- through doped a-Si: H by leaving overlaps 28 and 30
While the problem of etching in Si: H is reduced, the contact layer over the gate metal should be removed as much as possible for several reasons. The first reason is that the larger the gap 26 between the source and drain electrodes, the better the electrical insulation between the two electrodes. The second reason is
The channel length of the transistor depends on the operating characteristics of the transistor,
It is to be preset by the material and other parameters. The overlaps 28 and 30 increase the channel length and, as a result, increase the overall size of the structure. For example, channel 26, overlaps 28 and 3
Each length of 0 is 5 micrometers (μm) or more, and may be 15 μm or more in total. In today's fiercely competitive active matrix thin film sensor cells, the length of both ends including the optical sensor and the electric connection terminal is set to be about 50 μm or less. Thus, by reducing the overlap, the transistor length can be reduced, thereby increasing the area of detector material in the cell and / or the number of cells in an array of a given size.

[0005] Finally, the most important problem is the problem of formation of parasitic capacitance. This parasitic capacitance is formed at an overlapping portion between the source or drain electrode material and the gate material. The parasitic capacitance is shown in the schematic circuit diagram of FIG. 2 for a cell 50 for a display or sensing device. The cell 50 includes a TFT 52, and the TFT 52 functions as a switch for cell address. Gate 54 of TFT 52
Is connected to the gate line 60, and the drain 56 of the TFT 52 is connected to the data line 62. The source 58 of the TFT 52 is a sensor element (not shown, such as a pin photodetector) or a display element (not shown, such as a liquid crystal layer structure).
Connected to either In FIG. 2, these elements are collectively referred to as a pixel 66.

A parasitic capacitance (capacitor 64) is generated between the source and the gate due to the influence of the overlaps 28 and 30 shown in FIG. This parasitic capacitance causes a feed-through voltage on the pixel electrode. In the case of a display element, flickering of the image (abnormal transition from OFF to ON) and burn-in (abnormal transition from ON to OFF) occur. I do. In the case of a sensor element, the parasitic capacitance causes read noise.

FIG. 3 shows some adverse effects of parasitic capacitance and feedthrough voltage. FIG. 3 shows that from time t ₁ to t ₅
Voltage V _d of the gate 54 voltage V _g and the drain 56 of the TFT52 the subjected is shown. FIG. 3 also shows the actual voltage V _{pix at} the pixel 66 represented by the solid line and the ideal voltage V _{ideal at} the pixel 66 represented by the dashed line.
At time t _1, the voltage level of the data line 62 is high (typically 5~10V). On the other hand, the voltage level of the gate line 60 is low (normally 0 V). Therefore, TFT
Channel 52 is closed and the voltage is
It does not span between pixel and pixel 66, for example, in the case of a typical backlit liquid crystal display, the pixel is opaque or off.

At time t ₂ , the voltage level on data line 62 remains high, but the voltage level on gate line 60 transitions from low to high (typically 10-15V).
As a result, the channel of the TFT 52 is opened. As a result, a voltage is applied from the data line 62 to the pixel 66, and in the case of a liquid crystal with a backlight, the pixel 66 is transparent, that is, turned on. The pixel 66 has a constant specific capacitance usually indicated by C _pix . In addition, since the TFT and the pixel have an integrated structure, there is usually an overlap between the source electrode and the pixel electrode of the TFT 52. Therefore, C _{pi x} parallel capacitance C _s between the source and the pixel is generated. However, as described above, there is a capacitance between the source 58 and the gate 54 due to the overlap 30 (FIG. 1A). The gate 54 is connected to the gate line 60, and the source 58 is connected to the electrode of the pixel 66. The capacity is
It is represented by the capacitance C _gs between the gate line 60 and the pixel 66 (FIG. 2). Thus, between time t ₂ and time t ₃ the voltage as expected is applied to the pixel 66.

At time t ₃ , the voltage level on gate line 60 is switched low. Thereby, the charge in the channel of the TFT 52 disappears. However, at this time, there is a potential difference between both ends of C _gs , and due to this potential difference, C _pix
Some of the charge stored in the redistribution into C _{g s} , the voltage drop Δ
V _p occurs. This voltage drop is defined as a feedthrough voltage. At time t ₄ , the voltage level on data line 62 is low and the voltage level on gate line 60 is switched from low to high. As a result, the channel of the TFT 52 opens again. However, since the voltage level of data line 62 is low, capacitances C _pix , C _s and C _gs are discharged to the line voltage level of data line 62, thereby switching pixel 66 off. At time t _5, the voltage of the gate line 60 and data line 62 are both low. However, also in this case, there is a potential difference between both ends of C _gs , and this potential difference causes redistribution of charges from C _gs to the pixels 66, causing another feedthrough voltage drop ΔV _p .

Ideally, the off-state voltage and the on-state voltage are constant, as indicated by the dashed line V _ideal . However, the parasitic capacitance caused by the influence of the source electrode overlapping the gate electrode prevents obtaining this ideal response. In fact, when the gate voltage level at time t ₃ is changed from high to low, the voltage drop from the value set by data line 62 occurs. In the case of a display device, the aforementioned image “flickering” is caused by this feedthrough voltage.
(Fluctuation in brightness at the time of transition from the OFF state to the ON state) occurs. Similarly, at time t ₅ , the feed-through voltage prevents the complete discharge of C _pix and C _s and causes the “burn-in” (residual voltage, in this case, in the display pixel when going from on to off) of the aforementioned image. Light transmission) occurs.

Similarly, when the cell 50 is applied to a sensor device, the above-described phenomena caused by the capacitance and the feedthrough voltage cause sensor noise. That is, the feedthrough voltage from the gate line 60 through C _gs is
In addition to the readout voltage from the readout, causing a signal error.

The magnitude of the feedthrough voltage is a function of the voltage level at the data line and is given by:

That is,

ΔV _p ∝f (C _pix , C _gs ) · V _d Therefore, for example, in a gradation display application, the feedthrough voltage fluctuates according to the change in V _d , and this change is assumed to be V _d. The pixel response from the value.
This means that the gray level control is not uniform in both display and sensing device applications.

[0014]

Therefore, there is a need for a new and improved thin film transistor structure and method of making the same. The structure eliminates the overlap between both the source and drain and the gate electrode. In a TFT switch pixel having such an arrangement of the structures, a remarkable improvement in element performance can be obtained by the structure. This improvement in device performance is due to the elimination of the parasitic capacitance and the feedthrough voltage between the source electrode and the pixel. In addition, variations in element dimensions and performance between cells are significantly reduced, and the external dimensions of the element can be reduced.

[0015]

SUMMARY OF THE INVENTION The present invention is directed to a method of providing an improved thin film transistor with no overlap between electrodes. The parasitic capacitance between the source electrode and the gate electrode and the feedthrough voltage are significantly reduced or eliminated in this structure.

The features obtained by the present invention include a reduction in flicker and burn-in of an image in a display device, a reduction in readout noise in an image forming device, and an improvement in gradation level characteristics in both the display device and the image forming device. Further, according to the present invention, the size of the TFT pixel switch can be reduced.

According to the present invention, a self-aligned source and drain region of a TFT is formed by using a laser doping method. The doping mask is formed by an optical filter, which filters the wavelength (eg, about 308) of the radiation source (eg, laser) used in the doping process.
nm) and reflect the lithographic wavelength (eg, about 400 nm).
nm). The self-aligned doping mask also functions as a protective island for the channel. The entire manufacturing process is similar to the current manufacturing process for large area devices.

In one embodiment, a protective island is formed by backside lithography using the gate electrode as a mask. Then TF using front side laser doping
Doping is performed in the region very close to the channel in T, which solves the problem of edge shading when forming the source and drain regions using the gate electrode as a mask. In another embodiment, the region of the TFT closest to the channel is doped by a gas immersion laser doping method, again using a radiation filter as a mask to protect the channel region of the TFT. In another embodiment, a surface layer of a dopant material is deposited on the TFT structure, and then doped with laser energy to electrically activate the structure. Also in this case, the channel region of the TFT is protected by using the radiation filter as a mask. In yet another embodiment, the implantation process converts dopant atoms to T
After the implantation into the FT structure, the structure is electrically activated by laser annealing, and the damage caused by the influence of the implantation process is repaired. Also in this case, the radiation filter is used as a mask to protect the channel region of the TFT.

Also, the leakage current of the side wall due to the residual impurities is reduced. The reduction of the leakage current is obtained by patterning the protective layer on the outermost surface and using it as an etching mask, and then etching the side wall of the active layer to remove impurities. The outermost protective layer has appropriate dimensions, i.e., dimensions that allow alignment within the tolerances of current mask alignment technology.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 4A and 4B show
Each step of the manufacturing process according to one embodiment of the present invention is shown together with the structure of the manufactured TFT structure 100. Each step in the initial stage of manufacturing the TFT according to the present invention is the same as that in the conventional process. Specifically, the channel length is 3 to 15 μm.
m metal gate layer (eg, Cr, TiW, MoCr, etc.)
Is formed to a thickness of about 400 to 1000 mm on a transparent substrate 104 such as glass (for example, Corning 1737 manufactured by Corning Glass (Japan)) or quartz. This layer is formed by sputter deposition and standard lithographic techniques and wet etching. The metal gate layer is patterned by a known process to form the metal gate electrode 102.

On the metal gate electrode 102, a silicon nitride gate insulating layer 106 is formed by plasma-enhanced chemical vapor deposition at about 350.degree.
It is formed to a thickness of 00 °. On the gate insulating layer 106,
An about 500 ° intrinsic a-Si: H layer 108 is deposited at about 275 ° C. to form a TFT channel. Next, a radiation filter layer 110 is formed on the intrinsic a-Si: H layer 108. The radiation filter layer 110 comprises a stack of secondary layers whose thickness and composition are precisely controlled. Emission filter layer 110
The functions and features of will be described in detail later. Each of the above layers is formed using plasma enhanced chemical vapor deposition (PECVD). The fabricated structure at this stage of the process is shown in the cross-sectional view of FIG. 4 (a) and the plan view of FIG. 4 (b) (layers 106, 108 and 110 are transparent).

Next, as shown in FIGS. 5 (a) and 5 (b), a self-aligned radiation filter (or simply radiation filter) island 112 is formed from the radiation filter layer 110. FIG. A photoresist layer (not shown) is deposited on the radiation filter layer 110. The photoresist layer is patterned by back exposure (ie, through transparent substrate 104). Since the metal gate electrode 102 does not transmit light for photoresist exposure, it functions as an exposure mask. As described later, the radiation filter layer 11
0 transmits the photoresist exposure light to a considerable extent, so that the photoresist is exposed except for the portion overlapping the metal gate electrode 102. The photoresist is developed from the surface using a developer, and the radiation filter 110 is etched using a buffered HF etchant to form islands 112.

In the next step, a conductive layer for the source / drain contacts of the device is formed. Within the scope of the present invention, there are several methods for forming self-aligned TFT source / drain regions. is there. Next, some exemplary embodiments will be described.

In one embodiment, a method referred to as laser doping is used for doping semiconductor materials, wherein relatively high energy dopant atoms are generated using laser ablation. A laser pulse is applied to the translucent source layer containing the element to be doped (this source layer may be patterned and may be either n-type such as PSi or p-type such as BSi ). The source layer is provided very close to the substrate. During the application of the laser beam, the energy of the dopant atoms in the source layer increases. The laser beam also locally melts the surface layer of the substrate in the region to be doped for a short time. During the melting in a short time, the dopant atoms of high energy enter into the melted substrate surface layer. When the molten layer solidifies, the dopant atoms are distributed within the layer and become electrically activated. Since the high-temperature cycle during the doping process is as short as tens of nanoseconds, this method is substantially the same as low-temperature manufacturing. This is a-
This is particularly important in the manufacture of Si: H TFTs.

As shown in FIG. 6, at the start of laser doping, a source thin film 114 is first placed near the upper surface 116 of the a-Si: H layer 108. Source thin film 114
Is generally made of an alloy of phosphorus and silicon, and using this alloy to dope selected regions in the a-Si: H layer 108 to render the regions n-type. Source thin film 11
Numerals 4 are uniformly distributed on one surface of the carrier 118, and the carrier 118 has a property of transmitting a laser beam such as glass or quartz. Source thin film 11
A carrier 118 carrying 4 is placed in close proximity to the upper surface 116 such that the source thin film 114 faces the upper surface 116. Source thin film 114 and upper surface 11
6 has a minimum thickness of island 112 of 1
22 (eg, about 0.5 mm), up to several mm. Spacer 124 and / or island 1
12 determines the size of the gap 120. Generally, the smaller the gap between the source thin film 114 and the upper surface 116, the more the number of dopant atoms contained in the a-Si: H layer 108.

When the source thin film 114 is properly installed,
The laser beam B is applied from above the carrier 118 to the source thin film 1.
Irradiated on the area 126 in FIG. Alternatively, both ends of the entire layer 114 may be scanned by the laser. During this process, the laser ablates source thin film 114,
The high energy dopant atoms are released into the gap 120. This dopant atom has a kinetic energy of 100 eV or more. About 3 lasers suitable for this process
There is a XeCl excimer laser with a wavelength of 08 nm. An example of the source thin film 114 is PSi, which is deposited on the carrier 118 at about 250 ° C. to a thickness of about 100 ° by plasma enhanced chemical vapor deposition.

In addition to ablation of the source film 114, the energy of the laser also melts the portion of the upper surface 116 where the laser is incident. The important thing is Island 11
2 is that the laser beam B is not transmitted (for example, by the effect of reflection via interference). Because of this, the region under the island 112, ie, the channel 130, is not damaged by the laser beam. On the other hand, below region 126, dopant atoms enter layer 108, thereby forming, for example, n + doped source region 132 and n + doped drain region 134. This solves the problem that the laser cannot reach the material closest to the channel due to being hidden behind the end of the gate electrode, which cannot be solved by the related art.

This clearly shows one of the important features of the present invention. In other words, the material forming the radiation filter layer 110 transmits a considerable amount of radiation light (for example, light having a wavelength of about 400 nm) for photoresist exposure formed on the layer 110, thereby forming the island 112. It is necessary to perform
Also, it is necessary that the laser light used for ablation of the upper surface 116 to be locally melted (for example, laser light having a wavelength of about 308 nm) is not substantially transmitted. To this end, a "radiation filter" comprises: (a) transmitting the radiation used to expose the photoresist; (b) ablating one or more layers of one or more layers; and / or It is defined as a structure that can both reflect (or absorb) radiation (eg, laser light) used to melt.

However, there are many other methods for forming the source or drain contact conductive layer of the TFT. One example is a gas intrusion (gas immersion) laser doping method ("GILD"). FIG.
As shown in FIG.
Is completed at the stage of forming. After this, the device is replaced with a quartz window 18.
2 is evacuated to about 10 ^-6 Torr by a vacuum pump. Next, a dopant-containing gas 184 (eg, PF ₅ for n-type doping or BF ₃ for p-type doping) is introduced into the cell for doping. In the GILD method, the upper surface 116 is rapidly heated and melted using pulsed laser radiation. The step of doping occurs when the gas containing the dopant is absorbed by the upper surface 116 and further thermally decomposed into atoms to diffuse into the molten surface material. Upon solidification of the surface material, the doping species are electrically activated in the source region 132 and the drain region 134, which are contact regions. During this process, the a-Si channel 130 is protected by the radiation filter island 112 to prevent damage and / or doping by laser radiation.

As a method for forming a source or drain contact according to another embodiment, there is a laser treatment using a solid doping species supply layer 186 coated on the device surface, and this method is shown in FIG. Examples of sources of n-type doping species include phosphorus and alloys of phosphorus and silicon and others. The doping species source layer is formed by chemical vapor deposition or other known suitable methods. Alternatively, the solid doping species supply layer 186 may be a spin-doped thin film doped with phosphorus. As before, pulsed laser radiation (in this case, through the solid doping species source layer 186) rapidly heats and melts the upper surface 116 while activating the dopant species. This increases the energy of the atomic dopant species and increases the upper surface 1 of the Si layer near the doping species source layer 186.
It diffuses rapidly into the 16 molten parts. Again, the radiation filter island 112 prevents the TFT channel 130 from being damaged and / or doped by laser radiation. The solid doping species source layer 186 is then removed by a method known in the art (the contour of this layer is shown in broken lines in the figure).

FIGS. 24 and 25 show a method of forming a source or a drain of a TFT according to still another embodiment.
In this embodiment, a doping species is implanted into the source or drain contact area, and the radiation filter island 112 is used as an implantation mask during the implantation. The implantation is performed by an ion implantation device or an ion shower doping method. The former has a function of selecting mass and energy according to a desired ion and an implantation range, and the latter does not have a mass selecting function. FIG. 24 shows the state of this doping. However, this implantation causes crystal breakage in the implantation regions 133 and 139, which adversely affects device current characteristics. For this reason, after the implantation, pulse laser annealing is performed to repair damage such as crystal breakage due to the implantation by a thermal effect, and at the same time, activate the dopant in the source and drain regions 132 and 134. FIG. 25 shows the laser annealing process. During this laser annealing process, the radiation filter island 112 prevents laser damage to the TFT channel 130. Since the radiation filter island 112 is also used as an implantation mask and a laser annealing mask, the source region 13 where the dopant is implanted is formed.
Damage due to ions in the second and drain regions 134 is completely repaired by annealing.

FIG. 7 shows a portion 135 in the island 112.
1 shows a cross section of The island 112 (that is, the radiation filter layer 110) has a structure in which several secondary layers are stacked. As an example of this laminate, there is a laminate in which silicon dioxide 136 and silicon nitride 138 are alternately laminated. As shown, silicon nitride is selected as the top layer. This is because silicon nitride prevents doping during the laser doping process, thereby providing a high protection for the underlying material. Silicon nitride is selected for the lowermost layer 140 so that improved doping resistance and proper protection on the a-Si: H channel can be obtained. Other material systems suitable for this application include Si / SiO ₂ , Si /
There are Al ₂ O ₃ , SiO ₂ / TiO _{2 and} others, and as a basic feature, each of the two layers in each material pair has a different refractive index. As an example of the obtained structure, a so-called distributed reflector (D
BR). Another example is the so-called graded type D
There is a BR, in which the refractive index of the material changes as a function of the position in the thickness direction of the material.

Both the material type and thickness of each secondary layer play an important role in obtaining the selective transmission and reflection required for the radiation filter layer 110. Ideally, the optical thickness T of each oxide and nitride layer should be approximately a multiple of a quarter wavelength of the laser beam B, so that T = (1/4) (λ / η)
+ (M / 2) (λ / η) is established, and the optimum reflectance is obtained by matching the phase with the beam (where η is the refractive index of the material, m is a positive integer 1, 2, ...). For example, the thickness of the oxide layer 136 is
(１ ／) × (308 nm) × (1 / 1.48) = 52
nm, and the thickness of the nitride layer 138 is (１ ／) × (3
08 nm) × (1 / 2.1) = 36.7 nm (1.48 and 2.1 are the refractive indexes of silicon dioxide and silicon nitride, respectively). The thickness of the lowermost nitride layer 140 is different from the thickness of each of the other nitride layers, and is, for example, about 60 to 65 nm so that the phase is matched with the upper layer pair.
That is, since the material below the lowermost layer 140 is not SiO ₂ or SiN but a-Si: H, the phase is matched by changing the thickness of the layer 140 to that of the upper nitride layer.

Another important factor in obtaining the selective reflectance and transmittance of the radiation filter layer 110 is the number of secondary layers. By adjusting the reflection level, the a-Si: H channel under the island 112 is protected. FIG. 8 shows a simulation of the reflectivity of a 308 nm laser beam as a function of the number of oxide and nitride layer pairs that make up the radiation filter island 112. In the present embodiment, the required reflectance is set to 80% or more (however, as intended from the present invention, when a radiation source other than a 308 nm laser is used, or when a different dopant type is used, etc.) As the reflectivity varies, the 80% limit of this embodiment is not a limitation of all embodiments of the present invention). As shown in FIG. 8, this requirement is met by a radiation filter layer consisting of two layer pairs. In addition, even for a single layer pair, the reflectivity changes as a function depending on the laser output and the like.

FIGS. 9A and 9B show simulations and measured values of the light reflection spectrum of the radiation filter layer 110 composed of two layer pairs. Clearly, the simulation is in good agreement with the real data. The difference between the simulation and the measured value of the light reflectance is mainly based on the assumption that (1) the scattering is ignored in the simulation (the refractive index does not change with the change of λ), and (2) the optical thickness of each layer in the simulation. Due to the assumption of uniformity. The radiation filter layer 110 having two layer pairs is 3
It shows a reflectance of 80% at 08 nm, and this reflectance can sufficiently protect the a-Si: H channel. Wavelength 400
The transmittance of nm UV light is about 80%, at which transmittance a self-aligned backside lithography process can be performed. The total thickness of the radiation filter layer with two layer pairs is about 241 nm. This thickness is suitable for processing in a standard buffered HF wet etch.

As a final feature, the proposed island 1
12 can be made of standard insulating materials,
The island 112 can be used as a gate insulating layer. Therefore, the island 112 can be used not only for the bottom gate type TFT structure but also for the top gate type TFT structure.

Returning to the manufacturing process of the TFT structure 100, About 2
Plasma hydrogenation is performed at 50 ° C. for about 5 to 10 minutes, and the source region 1 induced by laser doping is formed.
32 and defects in the drain region 134 are prevented.

Next, as shown in FIGS. 10A and 10B, a gate via 142 (FIG. 10B) in contact with the metal gate electrode 102 is patterned and etched. Next, a metal contact layer (not shown) such as TiW / Al is deposited on the structure. Thereafter, the metal layer is patterned and etched by standard lithography and wet etching, or other conventionally known methods, to form a source electrode 144 and a drain electrode 146. The distance (indicated by Δx) between the end of the metal electrodes 144 and 146 and the end of the island 112 is set to 5 μm or more.

As shown in FIGS. 11A and 11B, a protective layer made of silicon nitride or silicon dioxide 148 is formed by PECVD and further patterned to define the width of the TFT structure 100. . Finally, the TFT structure 100 is completed by silicon etching. The silicon etching includes a source electrode 144,
Drain electrode 146, gate via 142, and patterned silicon nitride or silicon dioxide 148
This is to remove all a-Si: H other than the region covered by.

A problem common to thin film transistors is the leakage current on the side wall between the source and the drain. This leakage current is caused by impurities remaining on the side wall of the layer 18. Conventional TFT structure (FIG. 1A, FIG.
In FIG. 1B and FIG. 1C, the channel width W is defined by the width of the drain electrode 22 and the source electrode 24. Since each of the electrodes overlaps the channel, the side wall of the active layer is over-etched at the portion 150 (FIG. 1B) to reduce the leakage current. There is no effect on the electrical contact between the source region and the channel and between the drain region and the channel. The reason for this is that the a-Si: H layer is protected at the portion overlapped by the source and drain electrodes.

However, in the case of the TFT according to the present invention, the over-etching causes electrical contact between the source region and the channel and between the drain region and the channel. This is because the contact ends are not protected (ie, the electrodes do not overlap). FIG.
As shown in (b), the protective layer 148 is formed on the source electrode 144.
And the drain electrode 146 so as to cover the gap between the electrode and the radiation filter layer 112. Thereafter, even if over-etching proceeds, the source region 132 and the channel 130 and the drain region 13
No electrical contact occurs between 4 and channel 130. Further, the protective layer 148 is formed slightly narrower (for example, narrower by about 2 to 5 μm) than the radiation filter island 112 in the width W direction, so as to avoid a mask mismatch at the time of lithography. If the lithographic mask is not aligned with the radiation filter island 112, the layer 10
8 is not over-etched in the region 152 (FIG. 11C). This is because the protective layer 148 covers the region. That is, by providing the region 152 to be over-etched in the layer 108, impurities which cause a side wall leakage current are removed.

As shown in FIG. 11A, neither the source electrode 144 nor the drain electrode 146 of the TFT structure 100 in the present structure overlaps with the metal gate electrode 102. The ends of the source and drain regions coincide with the ends of the channel, ie, "self-aligned" with the channel. The parasitic capacitance C _gs due to the overlap of the source (and drain) contacts on the gate contact is eliminated, and the problem of feedthrough voltage is completely solved. Thus, the voltage characteristics at the pixel (such as pixel 66 in the configuration of FIG. 2) are represented by the dash-dot
to approximate the ideal characteristics shown by the _ideal. The analysis results for the structural element manufactured by the above-described method support the above theoretical analysis.

We have done some research on laser doping. In one of them, 100n
m of a-Si: H is reduced by a low pressure chemical vapor deposition (LPCV) method.
A film was formed on a quartz substrate by D). Phosphorus as a dopant was ablated from the substrate by laser ablation using a XeCl excimer laser.

The doping efficiency and the doping depth depend on the energy density during laser doping. The diffusion coefficient of phosphorus in the Si melt is about 10 ⁻⁴ cm ² / s, which is significantly faster than the diffusion rate in the solid phase of about 10 ⁻¹¹ cm ² / s. Since the temperature rise of the Si thin film during the pulse laser irradiation and the temperature decrease of the same thin film after the irradiation are steep, the dopant diffusion in the liquid phase is essentially efficient.
The higher the laser doping energy, the longer the melting duration and the deeper the melting depth, resulting in a higher doping revel and a deeper doping depth. FIG. 12 shows an experimental result of measuring the doping efficiency with respect to the laser doping energy density. The energy is about 150 m, which is a threshold value for melting the Si surface.
Above J / cm ² , the doping efficiency increases rapidly with increasing energy. The doping amount equivalent to the laser doping energy density of 350 mJ / cm ² is about 1.6 × 10 ¹⁴ atom / c per laser pulse.
m ² . In general, about 10 ^{1 4} atom / cm ² is TFT
Is the dose required to form the source and drain regions.

FIG. 13 is a plot of doping depth as a function of laser doping energy density. The behavior of the doping depth is similar to the melting depth as a function of laser energy density. In general, during solidification, the solid-liquid interface moves toward the surface while the dopant diffuses in the opposite direction. As a result, the doping depth is slightly shallower than the melting depth.

We have produced a number of self-aligned TFTs of the type described above. Channel length of manufactured structure is 3-10
It is in the range of μm. The overall width of the structure is about 15 μm
It is. The laser doping was performed at an energy of 230 to 250 mJ / cm ² using a XeCl laser having 10 to 100 pulses. The variation width of the gap Δx in these structures was 1 to 5 μm.

In the case of a device having a long channel, DC performance equivalent to that of a conventional TFT was observed. FIG. 14 shows the conversion characteristics of a self-aligned TFT having a channel length of about 10 μm according to the present invention. Laser doping is 250 mJ / cm ²
This was performed using a laser having a pulse number of 10 and an energy of 10.
When the voltage between the source and the drain is 10 V, the field-effect mobility, the threshold voltage, the gradient below the threshold, and the current in the off state are the same as those of the conventional a-Si: H TFT.

FIG. 15 shows a channel length of 3 μm according to the present invention.
5 shows the conversion characteristics of the self-aligned TFT of FIG. In general, when the channel length is shortened, the leakage current and the gradient below the threshold value increase as shown in the figure, and the threshold voltage decreases.
However, the mobility is not reduced by the reduction in size, which is contrary to the general wisdom that the apparent mobility of the short channel TFT is smaller than that of the long channel TFT. FIG. 16 shows a comparison of mobility with respect to channel length between a TFT manufactured according to the related art and a TFT manufactured according to the present invention. Prior art TFT data follows a well-known mobility curve, i.e., shows relatively low mobility for short channel devices. This is because the contact resistance of the short channel element is larger than the contact resistance of the short channel element. The TFT according to the present invention shows extremely high mobility even in the case of a short channel length, indicating that the contact resistance is negligible.

FIGS. 17A and 17B show output characteristics of TFTs having channel lengths of 10 μm and 3 μm, respectively.
None of the devices clearly had current crowding, indicating that device contacts were appropriate. Further, as a study of the contact, comparison was made of the on-state behavior in similar TFTs having different Δx. As shown in FIG. 18, in the range of 1 to 5 μm, the dimension of Δx does not affect the behavior of the TFT, indicating that the doped regions of the source and drain electrodes have sufficient sheet resistance. Therefore, exact alignment of the source and drain electrodes is not essential in current TFT manufacturing processes.

In most display devices, the pixel TFT operates in a linear region. The contact resistance of the TFT in the linear region is determined by the reciprocal of the output conductance. The contact resistance is the value of the intersection of the output resistance of the element at a channel length of zero. FIG.
FIG. 9 shows a comparison of the contact resistance between the electrode according to the present invention and a conventionally known electrode. The TFT of the present invention and the conventional TFT have similar channel properties and gate insulating properties. For this reason,
The slopes of both straight lines that fit each data in FIG. 19 are almost equal. The contact resistance of the conventional electrode and the laser-treated electrode when normalized to a channel width of 1 μm is 16.2 MΩ each.
.Mu.m and 0.76 M.OMEGA..mu.m. The low contact resistance of the laser-doped source and drain provides a high performance short channel a-Si: H TFT.

The short-channel TFT makes it possible to improve the filling ratio in a large-area display device. Since the on-state current of a TFT is proportional to the ratio of the channel width to the channel length, the improvement in the filling ratio is related to the square of the decrease in the channel length at a constant W / L (the ratio of the channel width to the channel length). By using the self-aligned structure shown in FIGS. 11A and 11B, the channel length of the TFT can be easily reduced.

As the size of the TFT becomes smaller, some important problems arise in the display device. One is the problem of field effect mobility in short channel TFTs. As described above, when the channel length is increased, it is necessary to make the contact resistance significantly smaller than the channel resistance to maintain the same TFT mobility. FIG. 20 shows that the channel length is 3 μm.
m, 5 μm and 10 μm laser treated aS
The experimental results of measuring the device conversion characteristics of the i: H TFT are shown. Obviously, the saturation current of the 3 μm device is almost equal to the saturation current of the 10 μm device.

Another problem relating to the miniaturization of TFTs relates to the short channel effect. Short channel effects include a decrease in threshold voltage, an increase in off-state current, and a decrease in steepness of a slope below the threshold voltage.
It is apparent from FIG. 20 that the slope below the threshold voltage and the decrease in the threshold voltage are small. 3μ
The off-state current of the m element is about 0.5 pA / μm, which is a sufficiently low value for a display device.

In summary, the present invention provides a semiconductor structure 200 as shown in FIG. The structure 200 is a gate region 202 formed on a first surface 204,
First gate end 20 located on first gate end surface 208
6 and a second gate end 210 located on a second gate end surface 212, wherein the first gate end surface 208 and the second end surface 212 are generally orthogonal to the first surface 204. And a source region 214 having a first source end 216 located at the first gate end surface 208.
Wherein the first source end 216 is
Drain region 2 having a source region 214 adjacent to, but not overlapping with, a first drain end 220 located at the second gate end surface 212.
18, wherein the first drain end 220 is adjacent to the gate region 202, but without overlapping, and the drain region 218 and the source region 214.
And a radiation filter island 222 located between the drain region 218 and the drain region 218.

Further, the structure 200 is a source electrode 224 having a first source electrode end 226 located on a plane 228 substantially parallel to the first gate end surface 208, wherein the first source electrode end 226 is A source electrode 22 spaced (eg, 5 μm) from the first gate end surface 208
4 and a drain electrode 230 having a first drain electrode end 232 located on a surface 234 substantially parallel to the second gate end surface 212, wherein the first drain electrode end 232 is Drain electrode 23 spaced (eg, 5 μm) from gate end surface 212
0 is provided. In this structure, neither the source electrode 224 nor the drain electrode 230 overlap the gate region 202.

The material properties and device characteristics of a TFT manufactured by the laser doping method according to the present invention have been described. Laser doping provides a practical method for forming source and drain regions of a-Si: H TFTs with high doping efficiency. The contact resistance of the laser-doped source and drain is about 20 times lower than a conventionally doped a-Si: H electrode. Due to this low contact resistance, the field effect mobility of the TFT can be maintained even when the channel length is shortened (the short channel effect is slightly reduced by 3 μm).
m). The off current of the 3 μm TFT is sufficiently low, and can satisfy the required specifications of the pixel switch.

Although the invention has been described with reference to several specific embodiments, it is apparent that various alternatives, modifications and variations can be made by the prior art within the scope of the present invention. For example, although the active layer of the above-described TFT is undoped intrinsic a-Si: H, the active layer may be doped to obtain desired TFT characteristics. Therefore, it is not intended that the invention be limited to the illustrated embodiment, but that it is within the scope of the appended claims and equivalents thereof, including all such alternatives, modifications and variations.

[Brief description of the drawings]

FIG. 1 is a schematic view of a thin film transistor according to the prior art.

FIG. 2 is a schematic circuit diagram of one cell in a cell array including a thin film transistor and a pixel according to the related art.

FIG. 3 is a diagram showing each voltage in the cell shown in FIG. 2 as a function of time.

FIG. 4 is a schematic view of the TFT of the present embodiment in an initial stage of a manufacturing process.

FIG. 5 is a schematic view of the TFT of the present embodiment at an intermediate stage of the manufacturing process.

FIG. 6 is a cross-sectional view showing a state in which a laser doping process is in progress at the time of manufacturing the TFT of the present embodiment.

FIG. 7 is a partial cross-sectional view of a radiation filter island of the present embodiment.

FIG. 8 is a plot of the reflectivity of a radiation filter island as a function of the number of layer pairs containing the island.

FIG. 9 is a diagram in which the reflectance of a modeled radiation filter island is plotted in a certain wavelength range.

FIG. 10 is a schematic diagram of a TFT of the present embodiment before completion.

FIG. 11 is a cross-sectional view after completion of the TFT of the present embodiment.

FIG. 12 is a diagram plotting experimental results obtained by measuring the doping efficiency with respect to the laser doping energy density in the laser doping process of the present embodiment.

FIG. 13 is a diagram plotting the doping depth as a function of the laser doping energy density in the laser doping process of the present embodiment.

FIG. 14 is a diagram showing conversion characteristics of a self-aligned TFT having a channel length of about 10 μm according to the present embodiment.

FIG. 15 is a diagram showing conversion characteristics of a self-aligned TFT having a channel length of about 3 μm according to the present embodiment.

FIG. 16 is a graph comparing mobility of a TFT manufactured according to the related art with a channel length of a TFT manufactured according to the present invention.

FIG. 17 is a diagram showing output characteristics of a TFT having a channel length of 10 μm and a TFT having a channel length of 3 μm.

FIG. 18 shows that the gap Δx between the source or drain electrode and the radiation filter island is 1 μm, 3 μm and 5 μm.
FIG. 9 is a diagram in which a gate voltage is plotted against a current between a source and a drain of a TFT having a thickness of μm.

FIG. 19 is a diagram comparing the contact resistance between the electrode of the present embodiment and a conventionally known electrode.

FIG. 20 shows channel lengths of 3 μm, 5 μm and 10 μm
It is a figure showing the experimental result which measured element conversion characteristics of a-Si: H TFT which carried out laser processing which is m.

FIG. 21 is a sectional view of a TFT according to the present embodiment.

FIG. 22 is a sectional view of a TFT in a gas intrusion (gas immersion) laser doping method of the present embodiment.

FIG. 23 is a cross-sectional view of a TFT in a laser-assisted doping method of a surface deposition doping species of the present embodiment.

FIG. 24 shows T in the dopant implantation method of the present embodiment.
It is sectional drawing of FT.

FIG. 25 is a cross-sectional view of the TFT in an annealing step in the dopant implantation method of the present embodiment.

[Explanation of symbols]

Reference Signs List 10 thin film transistor, 12 substrate, 14 gate metal, 16 gate insulating layer, 18 active layer, 20 surface protection island, 22 drain electrode, 24 source electrode, 26 gap (channel), 28, 30 overlap, 50 cell, 52 thin film transistor (TFT),
54 gate, 56 drain, 58 source, 60 gate line, 62 data line, 64 capacitor,
66 pixels, 100 TFT structure, 102 metal gate electrode, 104 transparent substrate, 106 gate insulating layer, 108
a-Si: H layer, 110 radiation filter layer, 112 filter island, 114 source thin film, 116 upper surface, 118 carrier, 120 gap, 126, 152
Region, 130 channels, 132 source regions, 13
3,139 injection region, 134 drain region, 135
136 silicon dioxide (oxide layer), 138 silicon nitride (nitride layer),
44 source electrode, 146 drain electrode, 148 silicon nitride or silicon dioxide, 142 gate via, 180 vacuum cell, 182 quartz window, 186 solid doping species source layer, 200 semiconductor structure, 202 gate region, 204 first surface, 206 One gate edge, 208 first gate edge, 210 second gate edge, 212 second gate edge, 214 source region,
216 first source end, 218 drain region, 22
0 first drain end, 222 radiation filter island, 224 source electrode, 226 source electrode end, 23
0 Drain electrode, 232 Drain electrode end.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Reni Eyle Jean United States of America Sunnyvale West Dune Ave. 115 (72) Inventor James B. Bois United States of America Los Altos Russell Avenue 1036 (72) Inventor Christopher El Chu United States of America Mountain View Esquire Avenue 234 Apartment, California 110 (72) Inventor Michael G. Hack USA Mountain View Ave, Mountain View California 372

Claims (4)

[Claims] 1. A method for forming a semiconductor structure having an active layer formed on a substrate, comprising: providing a radiation filter on a first region of the active layer; Disposing a dopant atom source on at least a portion of; and irradiating both the dopant atom source and the active layer with light toward the active layer, and applying the light to the dopant atom source. From the active layer in a region corresponding to the irradiated region and in the region other than the first region, whereby the first doping region and the second doping region. Forming a doping region in the active layer, wherein the semiconductor structure is formed at a first end formed at a first gate end and at a second gate end. Forming a first doping region as a source region having a source region end on the first gate end surface, the method further comprising: Forming the second doping region as a drain region having a drain region end at a gate end surface. 2. A method for forming a semiconductor structure, comprising: a gate having a first end formed on a first gate end and a second end formed on a second gate end on a substrate. Forming an electrode; forming an active layer on the gate electrode; forming a radiation filter layer on the active layer; forming a photoresist layer on the radiation filter layer; Using a gate electrode as a mask to limit exposure of the photoresist, exposing a portion of the photoresist layer through the substrate, the active layer, and the radiation filter layer in order; contacting the exposed portion of the photoresist; The exposed portion of the photoresist is removed together with the portion of the radiation filter layer, the first gate end surface has a first island end, and the second gate Forming a radiation filter island having a second island end on an end face; and implanting dopant atoms into first and second doping regions in the active layer by ion implantation, wherein the implantation comprises A radiation filter functioning as a mask for preventing ion implantation into the lower portion of the filter, defining a range of the first doping region and the second doping region; Annealing a second doping region to thereby form a source region having a source region end at the first gate end surface and a drain region having a drain region end at the second gate end surface in the active layer. And a method for forming a semiconductor structure. 3. The method for forming a semiconductor structure according to claim 1, wherein a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region. Forming, wherein the source electrode is formed to have a source electrode end located in a plane substantially parallel to the first gate end surface, wherein the source electrode end is within a distance of 5 μm from the first gate end surface. And the drain electrode is formed so as to have a drain electrode end positioned substantially parallel to the second gate end surface, and the drain electrode end is within 5 μm from the first gate end surface. A source electrode and the drain electrode are formed so as not to overlap with the gate region. Forming method. 4. The method according to claim 2, wherein the exposure of the photoresist is performed by ultraviolet light having a wavelength of about 400 nm, and the light irradiation is performed by light having a wavelength of about 308 nm. A method for forming a semiconductor structure.