JP3419073B2 - Thin film transistor, method of manufacturing the same, and active matrix liquid crystal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device, a thin film transistor used as the active device and the like, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A thin film transistor for an active matrix liquid crystal display device is conventionally manufactured by the steps shown in FIGS. 7 (A) to 8 (B). First, as shown in FIG. 7A, the gate electrode 103 is formed on the transparent substrate 101. Next, on the entire surface of the transparent substrate 101, the gate insulating layer 105,
A semiconductor layer (i-Si layer) 107, a channel blocking layer 109, and a photoresist layer 111 are sequentially formed.

The photoresist layer 111 is exposed from the back side of the transparent substrate 101. At this time, the gate electrode 103 serves as a mask. After developing the photoresist layer 111, FIG.
As shown in (B), a resist pattern 111A formed in self-alignment with the gate electrode 103 is formed. Using the resist pattern 111A as a mask, the channel blocking layer 109 is patterned to form the gate electrode 1
A channel blocking layer 109A is formed in a self-aligned manner with respect to No. 03.

As shown in FIG. 7C, a p-type impurity is implanted into the semiconductor layer 107 by using the patterned channel blocking layer 109A as a mask, and n-type high concentration (n ⁺ ) is provided around the channel region. Form the layers. next,
As shown in FIG. 8A, the semiconductor layer 107 is patterned to form a device area.

A metal layer such as chromium (Cr) for forming source / drain electrodes is formed on the entire surface of the substrate. By forming this metal layer, a metal silicide layer which is an alloy of metal and silicon is formed on the surface of the n ⁺ region of the semiconductor layer 107.

The metal layer is patterned as shown in FIG. 8A to form a source electrode 113 and a drain electrode 115. In order to reduce the parasitic capacitance (gate-source capacitance Cgs and gate-drain capacitance Cgd) of the thin film transistor, the source electrode 113 and the drain electrode 115 are formed apart from the channel region (i region). Between the source electrode 113 and the channel region and the drain electrode 1
The silicide layers 117 and 119 are provided between the channel region 15 and the channel region.
And n ⁺ layer.

An ITO (indium-tin oxide) film is formed on the entire surface of the substrate, and the ITO film is patterned to
As shown in FIG. 8B, the pixel electrode 121 connected to the source electrode 113 is formed.

The protective layer is formed on the entire surface of the substrate, and the terminal portion of the gate wiring, the terminal portion of the drain wiring, the pixel electrode 121, etc. are exposed, and the manufacturing of the display pixel substrate is completed.

According to the above manufacturing method, since the source / drain electrodes 113 and 115 are not arranged near the channel region, the parasitic capacitance (gate-drain capacitance Cgd and gate-source capacitance Cgs) of the thin film transistor becomes small. .

[0010]

The source / drain electrodes 113 and 115 and the channel regions (intrinsic semiconductor regions) are connected to the metal silicides 117 and 119 by n-type semiconductor layers. However, metal silicide (10 ⁴ Ω /
□) and the n-type semiconductor layer (10 ⁹ Ω / □) have a drawback that they have high resistance and lower the on-current of the thin film transistor. When the on-current of the thin film transistor becomes small, there is a problem that the writing time of each pixel becomes long and the display duty also deteriorates.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film transistor having a small parasitic capacitance and a large on-current, and a method for manufacturing the same. Another object of the present invention is to provide an active matrix liquid crystal display device having excellent characteristics.

[0012]

In order to achieve the above object, a thin film transistor according to the present invention includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed on the substrate and the gate electrode. A silicon layer formed on the gate insulating layer and provided with a channel region, a source region, and a drain region; a silicide layer formed on each of the source region and the drain region; and on the silicon layer. Channel blockin provided
The photoresist layer formed on the layer that will become
Exposure from the back side of the substrate using the gate electrode as a mask,
An exposure mask masking the channel region of the silicon layer.
By exposing from the front side of the substrate using a disk
Using the formed photoresist pattern as a mask,
The layer that will become the channel blocking layer can be etched.
Are formed in a self-aligned manner with respect to the gate electrode on said silicon layer by a, and the channel blocking layer located corresponding to the channel region of the lower, on the silicide layer as well as apart from the channel blocking layer one And a drain connected to the drain region by continuously covering a source electrode that is connected to the source region by being formed on a portion and a part of the channel blocking layer to a silicide layer on the drain region. And an electrode.

Further, a pixel electrode connected to the source electrode
It may have poles.

Further, the method of manufacturing a thin film transistor according to the present invention comprises a step of laminating a substrate, a gate electrode, a gate insulating layer and a silicon layer, and a step of providing on the silicon layer.
Formed on the layer that will be the channel blocking layer
Using the gate electrode as a mask on the photoresist layer
Exposing from the back side of the substrate, the channel area of the silicon layer
Area of the substrate using an exposure mask
Photoresist pattern formed by exposing from
As a channel blocking layer
Forming a channel blocking layer formed in a self-aligned manner on the gate electrode on the channel forming region of the silicon layer by etching the layer, and using the channel blocking layer as a mask to form the silicon layer Implanting impurities to form a channel region located below the channel blocking layer, and a source region and a drain region respectively located on both sides of the channel region, and at least the source region of the silicon layer and Forming a metal layer for forming an electrode on the drain region; and patterning the metal layer while leaving the metal silicide generated by the reaction with the metal layer on the surface of the silicon layer, the channel blocking layer A source electrode spaced apart from,
And a step of forming a drain electrode continuously covering from a part on the channel blocking layer to the silicide layer on the drain region.

Further, the active matrix liquid crystal display element according to the present invention includes a substrate, a gate electrode and a capacitance line formed on the substrate, an insulating layer arranged on the gate electrode and the capacitance line, and the insulating layer. A semiconductor layer formed on the layer, the semiconductor layer having a channel region, a source region, and a drain region facing the gate electrode, and the silicon layer.
Form on the layer that will be the channel blocking layer provided above
A mask of the gate electrode is formed on the formed photoresist layer.
And then expose from the back side of the substrate, before the silicon layer
The above-mentioned substrate is formed by using an exposure mask that masks the channel region.
A photo resist formed by exposing from the front side of the plate.
Use the gisto pattern as a mask to remove the channel block
A channel blocking layer disposed on the channel region in correspondence with the channel region and formed in a self-aligned manner with the gate electrode by etching a layer serving as an insulating layer; and on the source region and the drain. A silicide layer formed on each of the regions, a source electrode disposed apart from the channel blocking layer and connected to the source region via a silicide layer on the source region, and one of the source electrodes on the channel blocking layer. A display pixel substrate including a drain electrode continuously covering from a portion to a silicide layer on the drain region, and a pixel electrode connected to the source electrode and disposed on the gate insulating layer and facing the capacitance line. A counter substrate disposed opposite to the display pixel substrate and having a counter electrode formed thereon; Characterized in that it comprises a liquid crystal disposed between the element substrate and the counter substrate.

[0016]

According to the thin film transistor having the above structure, the gate
Channel blocking layer self-aligned with electrodes
The channel region formed using the
From the part on the blocking layer to the silicon on the drain region.
Close to the drain electrode that is continuously covered up to the
Therefore, the source and drain resistances of the thin film transistor are reduced, and the on-current of the thin film transistor is increased, as compared with the case where both the source and drain electrodes are separately arranged in the channel region. Moreover, since the source electrode is formed apart from the channel region, the capacitance between the source electrode and the gate electrode is maintained at a small value. Moreover, since so as to place the silicide layer on the source region and the drain region surface, a source electrode or a drain
The resistance value between the electrode and the channel region is also maintained at a relatively small value. Further, according to the method of manufacturing a thin film transistor according to the present invention, it is possible to manufacture a thin film transistor having the above characteristics.

According to the active matrix liquid crystal display element of the present invention, since one electrode is arranged apart from the channel region and the other electrode is arranged in contact with the channel region, there is a problem due to the parasitic capacitance of the thin film transistor. It is possible to increase the ON current while reducing the ON current.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be specifically described below with reference to the drawings by taking a display pixel substrate of an active matrix liquid crystal display device as an example.

FIG. 3 shows a schematic structure of the display pixel substrate according to this embodiment. As shown, the display pixel substrate includes a gate terminal 13, a gate line 15 connected to the gate terminal 13, a drain terminal 17, a drain line 19 connected to the drain terminal 17, and a gate on the transparent substrate 11. A thin film transistor 21 having a gate electrode connected to the line 15 and a drain electrode connected to the drain line 19
And a pixel electrode 23 connected to the source of the corresponding thin film transistor 21 and a capacitor line 25 facing the pixel electrode 23 are arranged in a matrix.

A thin film transistor having such a structure is shown in FIG.
It is manufactured by the steps shown in (A) to FIG. Note that FIGS. 1A to 2C correspond to a cross section taken along line 1-1 shown in FIG. First, a conductive layer having a thickness of about 30 to 70 nm made of aluminum, an aluminum alloy, chromium or the like is formed on a transparent substrate 11 made of glass, a flexible film or the like by vapor deposition, sputtering, etc., and patterned to form a conductive layer. The gate terminal 13, the gate wiring 15, the gate electrode GE, and the capacitance line 25 are formed.

Thereafter, as shown in FIG. 1 (A), the transparent substrate 11 has a thickness of 200 to 700 nm, preferably 300.
~ 500 nm gate insulating layer 31 made of silicon nitride (SiN) or the like, thickness 30 ~ 70 nm, preferably 40 ~ 60
semiconductor layer (i-Si layer) 33 made of amorphous silicon, polysilicon or the like having a thickness of 100 nm, a thickness of 100 to 400 nm, preferably a thickness of 150 to 250 nm of silicon nitride (Si).
N) and the like, a channel blocking (protection) layer 35,
The photoresist layer 37 is sequentially formed using a method such as plasma CVD method, sputtering, and coating.

The photoresist layer 37 is exposed from the back side of the transparent substrate 11. At this time, the gate terminal 13, the gate line 15, and the gate electrode GE serve as a mask. Further, from the front surface side of the transparent substrate 11, a photoresist layer 37 is formed using an exposure mask (not shown) masking the channel formation region.
To expose. By exposure from the back surface side and the front surface side, the photoresist layer 37 in the area other than the channel formation area is exposed.

The photoresist layer 37 was developed, and FIG.
As shown in (B), the photoresist pattern 37A is left on the channel formation region. The photoresist pattern layer 37A is used as a mask to etch the channel blocking layer 35 with hydrofluoric acid or the like (may be dry etching) to form a channel blocking layer 35A formed in self-alignment with the gate electrode GE. To do.

As shown in FIG. 1C, a p-type impurity such as phosphorus is ion-doped (ion-implanted) into the semiconductor layer 33 using the channel blocking layer 35A as a mask to form an n-type high concentration (n ⁺ ) region. Form. As shown in FIG. 2A, the semiconductor layer 33 is patterned in the shape of a device area. As a result, the channel, source and drain regions are formed. Then, the surface of the semiconductor layer 33 is treated with NH ₄ F or the like (the surface is slightly etched) in order to remove the rough surface and the natural oxide film by ion doping.

A metal such as chromium (about 10 Ω /
□) has a thickness of 50 to 200, preferably 70 to 130 nm
It is deposited by sputtering or the like to a certain thickness. By this deposition, the n-type high-concentration layer (source and drain regions) is brought into contact with the metal, and a metal silicide is formed on the contact surface.

The metal film is etched to form a source electrode SE, a drain electrode DE, a drain terminal 17 (FIG. 3) and a drain line (19) as shown in FIG. 2 (A). The source electrode SE is a channel region (i (intrinsic semiconductor)
The source region (n-type high concentration layer) and the silicide layer 41 formed on the surface thereof are connected to the channel region. On the other hand, the drain electrode is in contact with the channel region and the channel blocking layer 35A and extends on the channel blocking layer 35A.

IT is formed on the entire surface of the substrate by using sputtering or the like.
A transparent conductive film made of O (indium-tin oxide) or the like is formed and patterned to form a pixel electrode 23 connected to the source region and the source electrode SE, as shown in FIG. 2B. To do.

As shown in FIG. 2C, silicon nitride,
An overcoat layer (passivation film) 47 made of silicon oxide or the like is formed on the entire surface. Next, the overcoat layer 47 is etched to expose the gate terminal 13, the drain terminal 17, and the pixel electrode 23, and the formation of the display pixel substrate shown in FIG. 3 is completed.

As shown in FIG. 4, alignment films 57 and 59 are arranged on the display pixel substrate 51 thus formed and the counter substrate 55 on which the counter electrode 53 is formed, and further, a spacer 61 and a sealing material 63. The active matrix liquid crystal display element is completed by bonding the two via the substrate, filling the liquid crystal 65 between the two substrates, and disposing a pair of polarizing plates 67 and 69.

An equivalent circuit of a thin film transistor and a pixel of such a liquid crystal display device is shown in FIG. As shown in FIG. 5, the gate electrode GE of the thin film transistor 21 is connected to the gate line 15, the drain electrode DE is connected to the drain line 19, and the source electrode SE is formed of the pixel electrode 23, the counter electrode 53, and the liquid crystal 65 therebetween. The pixel capacitance CLC is connected to the pixel capacitance CLC formed by the pixel electrode 23 and the capacitance line 25.

In such a circuit structure, the thin film transistor 21 is turned on and the pixel electrode 23 is turned on while the gate pulse is applied to the gate electrode GE through the gate line 15 as shown in FIG. 6 (A). The voltage is shown in Fig. 6 (B).
It changes as shown in. On the other hand, when the gate pulse falls and the thin film transistor 21 is turned off, the voltage of the pixel electrode 23 is divided and lowered according to the value of the gate-source capacitance Cgs of the thin film transistor 21 (more accurately, the absolute value is lowered. ), The lowered voltage is maintained until the next writing period. Therefore, the gate-source capacitance C
If gs is large, the change in voltage when the thin film transistor 21 is turned off becomes very large, and stable gradation display cannot be performed. Therefore, it is desirable that the gate-source capacitance Cgs be small. On the other hand, the gate-drain capacitance Cgd of the thin film transistor 21 has almost no effect on the voltage of the pixel electrode 23.

If the resistance of the current path (source / drain path) of the thin film transistor 21 is large, the curve of the voltage of the pixel electrode 23 becomes gentle when the gate pulse is on, and the writing time becomes long. Therefore, it is desirable that the resistance value of the current path is small.

As described above, in the thin film transistor 21 of this embodiment, the source electrode SE connected to the pixel electrode 23 is arranged apart from the channel region (intrinsic semiconductor layer (i layer)) and the channel blocking layer 35A. So
The problem gate-source capacitance Cgs is small. Moreover, since the drain electrode DE is arranged in contact with the channel region, the resistance value of the current path of the thin film transistor 21 can be maintained at a small value. Further, since the source electrode SE is also connected to the channel region via the silicide layer 41, its resistance value is relatively small. Therefore, according to this embodiment, a thin film transistor having excellent characteristics and a display pixel substrate using the thin film transistor can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the chrome layer is formed after the semiconductor layer 33 is patterned into the shape of the device area. However, before patterning the semiconductor layer 33, a chrome layer having a thickness of 30 to 100 nm or the like is used. Metal layer (about 10Ω /
□) may be formed, and then the semiconductor layer 33 and the chromium layer may be patterned as shown in FIG.

A conductive layer of aluminum titanium or the like is formed on the structure shown in FIG. 2B, and this is patterned to
Source electrode SE, drain electrode DE, drain line 1
9, the drain terminal 17 and the like may be multilayered. Impurities implanted into the semiconductor layer 33 are not limited to p-type, but n-type impurities may be implanted to form p-type source / drain regions.

Further, in the above embodiment, the channel blocking layer remains only on the channel region, but by performing a predetermined mask during exposure from the front side of the substrate, the intersection of the gate line 15 and the drain line 19, The channel blocking layer 35 may be left at the intersection of the capacitance line 25 and the drain line 19. With such a configuration, it is possible to improve the insulation performance between layers.

[0037]

As described above, according to the present invention, it is possible to provide a thin film transistor having a small gate-source capacitance and a small current path resistance. By using such a thin film transistor as an active element of an active matrix type liquid crystal display element, it is possible to obtain a liquid crystal display element capable of stably displaying an image of an arbitrary gradation with high duty.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 3 is a plan view showing a configuration of a display pixel substrate according to an embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a liquid crystal display element according to an embodiment of the present invention.

FIG. 5 is a diagram showing an equivalent circuit of each pixel of an active matrix liquid crystal display element.

FIG. 6 is a graph showing an example of changes in gate pulse and voltage of each pixel electrode.

FIG. 7 is a diagram showing a manufacturing process of a conventional thin film transistor.

FIG. 8 is a diagram showing a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

11 ... Transparent substrate, 13 ... Gate terminal, 15 ... Gate line, 17 ... Drain terminal, 19 ... Drain line, 21 ... Thin film transistor, 23 ... Pixel electrode, 25
... Capacitance line, 31 ... Gate insulating layer (SiN), 33
... semiconductor layer (Si), 35 ... channel blocking layer, 37 ... photoresist layer, 41 ... silicide layer,
43 ... Silicide layer, 47 ... Overcoat layer, 53
... Counter electrode, 55 ... Counter substrate, 57 ... Alignment film, 59 ...
..Alignment film, 61 ... Spacer, 63 ... Sealing material, 65 ...
Liquid crystal material, 67 ... polarizing plate, 69 ... polarizing plate, 101 ...
Transparent substrate, 103 ... Gate electrode, 105 ... Gate insulating layer, 107 ... Semiconductor layer (Si), 109 ... Channel blocking layer, 111 ... Photoresist layer, 113 ...
Source electrode, 115 ... Drain electrode, 117 ... Silicide layer, 119 ... Silicide layer, 121 ... Pixel electrode

Claims (5)

(57) [Claims] 1. A substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the substrate and the gate electrode, a channel region, a source region, and a drain formed on the gate insulating layer. A silicon layer having a region, a silicide layer formed on each of the source region and the drain region, and a channel blocking layer provided on the silicon layer.
The gate on the photoresist layer formed on the layer to be
Exposure from the back side of the substrate using the electrode as a mask,
Exposure mask masking the channel region of the silicon layer
Formed by exposing from the front side of the substrate using
The photoresist pattern is used as a mask to
For etching the layer that will be the channel blocking layer
Therefore, it is formed in self-alignment with the gate electrode,
A channel blocking layer located corresponding to the channel region below, a source electrode separated from the channel blocking layer and connected to the source region by being formed on a part of the silicide layer, and the channel A drain electrode connected to the drain region by continuously covering a part of the blocking layer to the silicide layer on the drain region, the thin film transistor. 2. The thin film transistor according to claim 1, further comprising a pixel electrode connected to the source electrode. 3. A stacking step of stacking a substrate, a gate electrode, a gate insulating layer, and a silicon layer, and a channel blocking layer provided on the silicon layer.
The gate on the photoresist layer formed on the layer to be
Exposure from the back side of the substrate using the electrode as a mask ,
Use an exposure mask that masks the channel region of the silicon layer
Formed by exposing from the front side of the substrate
Using the photoresist pattern as a mask,
By etching the layer that will become the blocking layer.
The over the channel formation region of the silicon layer, wherein forming a channel blocking layer formed in self alignment with the gate electrode, the channel blocking layer as a mask, impurities are implanted into the silicon layer Te , the channel region located in correspondence with the lower of the channel blocking layer, and a source region located on both sides of the channel region, and forming a drain region, at least a source region and a drain region of the silicon layer Forming a metal layer for forming an electrode, and patterning the metal layer in a state where the metal silicide generated by the reaction with the metal layer remains on the surface of the silicon layer, and is separated from the channel blocking layer. Placed source electrode, as well as part of the channel blocking layer To the silicide layer on the drain region to form a continuous drain electrode,
A method of manufacturing a thin film transistor, comprising: 4. The method of manufacturing a thin film transistor according to claim 3, further comprising the step of forming a pixel electrode connected to the source electrode. 5. A substrate, a gate electrode and a capacitance line formed on the substrate, an insulating layer arranged on the gate electrode and the capacitance line, and formed on the insulating layer and facing the gate electrode. And a semiconductor layer having a channel region, a source region, and a drain region, and provided on the silicon layer.
On the layer that will become the channel blocking layer.
The substrate using the gate electrode as a mask on the photoresist layer
Exposing from the back side of the silicon layer to the channel region of the silicon layer.
Area of the substrate using an exposure mask
Photoresist pattern formed by exposing from
As a channel blocking layer
A channel blocking layer disposed on the channel region corresponding to the channel region and self-aligned with the gate electrode by etching a layer, and on the source region and the drain region, respectively. The formed silicide layer, the source electrode that is arranged apart from the channel blocking layer and is connected to the source region via the silicide layer on the source region, and the drain from a part on the channel blocking layer. A display pixel substrate including a drain electrode continuously covering a silicide layer on a region, a pixel electrode connected to the source electrode, disposed on the gate insulating layer, and facing the capacitance line; A counter substrate arranged facing the substrate and having a counter electrode formed thereon; and the display pixel substrate, Akuteibu matrix liquid crystal display element characterized by comprising a liquid crystal disposed between the counter substrate.