JP2659976B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a thin film transistor used for driving a liquid crystal display or the like.

(Prior Art) Amorphous silicon (hereinafter abbreviated as a-Si) thin film transistors (abbreviated as TFT) are widely used as active matrix elements of liquid crystal displays. Currently 3
A 6-inch type liquid crystal television has been developed and some have become commercial products.

Several structures are considered for amorphous silicon thin film transistors, but self-aligned TFTs have the following advantages not found in other structures. That is, it is easy to manufacture because there is no additional capacitance due to the overlap between the gate and the source and the drain, and the alignment accuracy is not strictly required between the gate and the source and the drain.

As a result, the active matrix risk is that the capacitance per gate line can be reduced. In addition, the capacitance between the gate and the source (gate-source capacitance Cg
The variation in s) can be made constant irrespective of the alignment accuracy, and when displaying a large area, the penetration of the gate pulse into the pixel electrode voltage can be made constant.

On the other hand, several methods have been proposed for manufacturing a self-aligned TFT. In this case, n-type a
-Si and wiring electrodes need to be formed by self-alignment with the gate. FIG. 7 is an example of this,
N on the positive resist left on the gate by back exposure
The mold a-Si layer 52 and the wiring electrode layer 62 are accumulated and patterned by lift-off.

n-type a-Si layer 52 serving as source and drain in a-Si TFT
Has a resistivity of about 10 ² Ωcm and a sheet resistance at 500Å of 2 ×
It is quite high at 10 ⁷ Ω / □. Therefore, usually in a-Si TFT, n
The layer is used only as a rectifying junction with the channel,
A metal is provided on the n-layer to reduce the wiring resistance.

In the self-alignment type TFT, the wiring electrode layer may be self-aligned similarly to the n-layer, or may be formed by alignment with an exposure device so as to overlap the insulating film (shown by 7 in FIG. 7) above the channel. is there. However, the latter loses the above-mentioned second feature of the self-alignment and is not desirable. In the former case, if lift-off is performed as described above, the lift-off may be incomplete and the yield may be reduced, which is not desirable.

(Problems to be Solved by the Invention) The present invention involves a complicated process resulting from the fact that the sheet resistance of the n ⁺ layer serving as the source and drain regions found in a-Si TFTs is high and cannot be used for wiring. It is intended to prevent difficulties. In other words, it is an object of the present invention to reduce the wiring resistance of the source and drain portions and reliably form a large number of transistors in a large area such as an active matrix.

[Configuration of the invention]

(Means for Solving the Problems) A thin film transistor according to the present invention is formed by (1) a step of patterning and forming a gate electrode on a transparent substrate, and sequentially stacking a gate insulating film, an amorphous silicon film, and a protective insulating film. Performing a step of applying a resist film to the protective insulating film, exposing from the transparent substrate side and leaving it on a gate electrode, etching the protective insulating film using the resist film as a mask, A step of forming a semiconductor region having a high impurity concentration to be a source and a drain by injecting a gas decomposed by discharge using the film as a mask into the amorphous silicon film and doping impurities, and depositing a metal layer on the source, A step of forming a reaction layer on an exposed surface of a semiconductor region having a high impurity concentration serving as a drain; and a step of forming a wiring electrode connected to the reaction layer. Manufacturing method of membrane transistor. (2) gate electrode, gate insulating film,
A source / drain semiconductor region having a high impurity concentration having an active layer made of amorphous silicon;
In a thin film transistor having two wiring electrodes connected to a drain, the source and the drain have a reaction layer with a thickness of 50 to 200 angstroms on the surface of a semiconductor region having a high impurity concentration, which serves as a wiring. An electrode is connected, and the wiring electrode is arranged so as not to overlap with a gate electrode. (3) a step of patterning and forming a gate electrode on a transparent substrate, a step of sequentially stacking and forming a gate insulating film, an amorphous silicon film, and a protective insulating film; and forming a resist film on the protective insulating film. Exposing from the transparent substrate side to leave on the gate electrode, etching the protective insulating film using the resist film as a mask, and discharging the gas decomposed by discharge using the protective insulating film as the amorphous silicon. Forming a semiconductor region with a high impurity concentration as a source and a drain by injecting into the film and doping with an impurity; and depositing a metal layer and forming a reaction layer Forming a semiconductor region having a high impurity concentration serving as the source and drain, and a pattern connecting the reaction layer after patterning the reaction layer. Method of manufacturing a thin film transistor comprising the steps of forming a use electrodes. (4) a semiconductor region having a gate electrode, a gate insulating film, an active layer made of amorphous silicon and having a high impurity concentration as a source and a drain, and two wiring electrodes connected to the source and the drain; In the thin film transistor, the semiconductor region with a high impurity concentration is provided in a stacked manner on an upper surface of a wiring electrode, and includes a reaction layer formed so as to overlap a surface of the semiconductor region with a high impurity concentration,
A thin film transistor, wherein the wiring electrodes are arranged so as not to overlap the gate electrodes. (5) a step of patterning and forming a gate electrode on a transparent substrate, a step of sequentially stacking and forming a gate insulating film, an amorphous silicon film, and a protective insulating film; and forming a resist film on the protective insulating film. Exposing from the transparent substrate side and leaving it on a gate electrode; etching the protective insulating film using the resist film as a mask; forming a semiconductor layer with a high impurity concentration; Applying a resist film on the layer, exposing the semiconductor layer on the protective insulating film by exposing from the transparent substrate side and etching away the semiconductor layer on the protective insulating film to form a semiconductor region having a high impurity concentration serving as a source and a drain; and Depositing a reaction layer on the exposed surface of the semiconductor region having a high impurity concentration to be the source and drain; and forming a semiconductor layer having a high impurity concentration to be the source and the drain. And a method of manufacturing a thin film transistor comprising the steps of forming a wiring electrode connected to the reaction layer after subjected to patterning into the reaction layer.

(Operation) In the a-Si TFT, it is desired that the field-effect mobility is small and the channel length L is as small as 10 μm or less. When the self-alignment is performed, the width of the gate electrode becomes the same as the channel length. However, according to the present invention, the distance between the wiring electrodes connected to the source and the drain can be made larger than the width of the gate electrode. The alignment accuracy between the electrodes can be increased up to the gate electrode width (10 μm or more). In other words, at least one of the source and drain sides is spatially separated between the gate electrode, that is, the end of the channel portion and the wiring electrode connected to the source and drain. Since the reaction layer reacting with the metal is provided on the surface together with the high source and drain semiconductor regions, the sheet resistance is reduced, and the series resistance at the source or drain can be ignored.

Embodiment An embodiment according to the present invention will be described below with reference to FIG. The manufacturing process is shown in FIG. 2 and will be described with reference to FIG.

The gate electrode 2 is patterned on the transparent glass substrate 1. The gate electrode is made of an opaque metal (for example, Mo, TA, Cr, etc.). On this, a gate insulating film 3, an i-layer amorphous silicon film 4, and an insulating film 7 for protecting a channel portion are sequentially laminated. The gate insulating film is a SiO _X or SiN _X film of about 4000Å, i
Layer amorphous silicon film is 200 to 500 Å, the protective insulating film was to no SiO _X of about 2000Å thickness using a SiN _X film.

A positive resist is applied thereon, and backside exposure from the glass substrate side is performed. The insulating film is transparent at the wavelength of the light source for exposure, and the i-layer a-Si absorbs light but transmits light because it is very thin, and the uppermost resist is exposed except for the portion where the gate is present (second resist). Figure a). In the figure, reference numeral 9a denotes an unexposed resist, and 9b denotes an exposed resist. After the development, the insulating film 7 is etched using the resist as a mask.

The insulating film 7 protects the surface of the semiconductor in the channel portion and at the same time functions as a mask when the next n ⁺ layer is formed. That is, impurities can be doped only into the exposed a-Si. The doping was performed by subjecting a gas containing phosphine (PH ₃ ) to high-frequency discharge decomposition, accelerating at a voltage applied to the substrate, and injecting phosphorus (P). The substrate was activated by setting the substrate temperature to 200 to 300 ° C., and the resistivity became 10 ⁴ Ωcm to 10 ³ Ωcm. Note that phosphorus was introduced almost entirely in the film because the i-layer a-Si was thin. (FIG. 2b) Next, Mo was deposited on the entire surface by sputtering. The metal film 10 reacted with a-Si only when deposited at room temperature, and formed a reaction layer 8. The reaction layer 8 was very thin, about 50 to 200 °, but the sheet resistance was significantly lower than that of n ⁺ a-Si. In the case of Mo, it was 10 ² to 10 ⁴ Ω / □. Since the on-resistance of the a-Si TFT is a sheet resistance of 10 ⁶ to 10 ⁷ Ω / □, the resistance of the reaction layer up to a wiring electrode to be described later can be sufficiently smaller than the on-resistance. (FIG. 2c) Next, a-Si is patterned into an island shape, a contact hole is opened, a Mo, Al laminated film is deposited, and this is patterned to form a wiring electrode 6. The wiring electrode 6 is widely patterned between the source and the drain so as not to overlap the gate. Mo between the end of the channel and the wiring electrode is removed by etching. (FIG. 2d) It can be seen that there is no increase in the number of times of photolithography and the process except for Mo sputtering for forming the reaction layer 8 from the above process. In particular, the probability of transistor failure in the active matrix, in which a large number of transistors must be formed in a large area without using lift-off, has been greatly improved as compared with the case using lift-off.

Further, it was found that the reaction layer 8 used here had a low sheet resistance but a small thickness, and was melted when a large current (several mA or more) was passed. Therefore, if there is a pinhole or the like in the gate insulating film and the gate and the a-Si are in contact with each other, the current flows between the gate and the source and the drain to melt in the region of only the reaction layer, and the gate and the wiring A short circuit between the electrodes can be prevented in a self-healing manner. The active matrix can prevent serious defects such as line defects.

The gap between the gate and the wiring electrode is a margin for alignment of the wiring electrode with the substrate, and the larger the distance, the more the alignment accuracy of the exposure device can be loosened, and a simpler exposure device can be used. . In addition, the glass used as the substrate is also problematic in that it becomes more deformable due to the heat process as the display area becomes larger, and since the large area can be handled as the alignment accuracy is loose, it is also inexpensive with a low melting point such as soda lime glass. Glass that is easily deformed can be used, resulting in a reduction in overall cost.

In the present embodiment, the sheet resistance of the reaction layer is 10 ⁻³ to 10 ⁻⁴ times the channel sheet resistance at the time of ON. Therefore, if the wiring electrode is provided with the same width as the channel width, the distance between the gate wiring electrode and the gate electrode becomes the channel width. 10 to 10 ³ times the length is allowed. Channel length 5
The distance can be as small as 50 μm as a minimum of 10 μm, and it can be said that a sufficient alignment margin can be obtained even with a 40-inch diagonal display.

In this embodiment, the impurity implantation into the i-layer a-Si is performed by plasma doping, but may be performed by ion implantation. Although Mo was used as the metal forming the reaction layer, Cr, Ti
But we have confirmed that it has the same effect.

Next, an embodiment according to another claim (5) is shown in FIG.
In this case, after the insulating film 7 is patterned by backside exposure as shown in FIG. 2B, an n + layer 51 is deposited at about 200 °.
Thereafter, a negative resist is applied, the resist is exposed again by back exposure, only the gate is removed, and the n ⁺ layer is removed by etching.

After the formation of the n ⁺ layer, the TFT is completed by the same process as described above.

The advantage of this method is that since the doping is not performed, the film quality of the n ⁺ layer is high and the junction characteristics with the i layer are good.

Next, an inverted planar type TFT according to another embodiment of the present invention is shown in FIG. In the above description, the wiring electrode 61 is provided opposite to the gate with the semiconductor interposed therebetween, but may be provided on the same side. The n ⁺ layer was formed by doping.

FIG. 5 shows a planar type as another embodiment of the present invention. That is, the i-layer a-Si, the gate insulating film, and the gate 11 are laminated in this order, the gate insulating film 31 is also patterned simultaneously with the patterning of the gate 11, the exposed i-layer portion is doped, and the metal for forming the reaction layer is formed. Deposit and etch. The wiring electrode can be formed apart from the gate. In this case, there is a feature that backside exposure is unnecessary.

Further, as another embodiment, a staggered TFT can be manufactured by the same process as in FIG. 5 after the wiring electrode 61 is formed in advance, and this is shown in FIG.

The same parts as in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. FIGS. 4 to 6 show the embodiments in which the structure of the TFT is changed. Can be formed in various ways, and the selection is broadened by the material, layout, etc. of the wiring portion in the active matrix.

〔The invention's effect〕

According to the present invention, the alignment accuracy of the wiring electrode connected to the source and drain and the gate or semiconductor layer can be remarkably relaxed.

In particular, in combination with the self-aligned formation of n ⁺ (or p ⁺ ) a-Si for the source and drain, it is possible to increase the margin of alignment accuracy while suppressing variations in TFT characteristics due to exposure deviation over a large area. , Realizing a large area and high performance of active matrix. The margin of the alignment accuracy gives a margin to the performance of the exposure apparatus, and the cost of the exposure apparatus can be improved, thereby improving the total cost and the throughput. In addition, the glass is given a margin for its own deformation, so that inexpensive glass such as soda lime glass can be used, resulting in a reduction in cost.

The above-mentioned effects are raised and can be achieved in common for all the claims. Other effects that can be achieved for each claim are described below.

(A) Phosphine in which impurity atoms (P) and hydrogen are combined is discharged and decomposed and accelerated by an electric field to be implanted, so that the inclusion of hydrogen promotes the formation of a reaction layer. As a result, the formation perfection of the reaction layer (reproducibility and stability of the resistance value) can be obtained (Claim 1).

(B) By limiting the film thickness, an increase in the off-state current of the TFT can be reduced without contacting the reaction layer with the i-layer within this range.
2).

(C) An increase in the off-state current of the TFT can be reduced.
3).

(D) Since a wiring electrode can be formed before forming a semiconductor film which generates much dust, defects due to dust (disconnection,
Short between lines is less likely to occur, and the yield is improved (claim 4).

(E) Self-alignment can be realized without using a lift-off, n-layer etching does not require selective etching with the i-layer, and the manufacturing margin is improved and the yield is improved (claim-5).

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a TFT according to an embodiment of the present invention, FIGS. 2a to 2d are cross-sectional views showing the steps of manufacturing the TFT in the order of steps, and FIGS. FIG. 7 is a cross-sectional view of a TFT formed by conventional self-alignment. DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2, 21 ... Gate electrode 3, 31 ... Gate insulating film 4 ... i-layer amorphous silicon 5 ... n ⁺ layer amorphous silicon (by doping to i layer) 51, 52 ... n ⁺ Layer amorphous silicon (due to doping at the time of film formation) 6,61,62 ... Electrode for wiring 7 ... Insulating film for channel part protection 8 ... Reaction layer

Claims (5)

(57) [Claims] A step of forming a gate electrode on a transparent substrate by patterning; a step of sequentially forming a gate insulating film, an amorphous silicon film and a protective insulating film on the transparent substrate; and forming a resist film on the protective insulating film. Attaching, exposing from the transparent substrate side and leaving on the gate electrode, etching the protective insulating film using the resist film as a mask, and etching the gas decomposed by discharge using the protective insulating film as a mask. By doping impurities into the porous silicon film
A step of forming a semiconductor region with a high impurity concentration to be a drain; a step of depositing a metal layer to form a reaction layer on an exposed surface of the semiconductor region with a high impurity concentration to be a source and a drain; A method for manufacturing a thin film transistor including a step of forming a wiring electrode. 2. A semiconductor region having a gate electrode, a gate insulating film, an active layer made of amorphous silicon and having a high impurity concentration as a source and a drain, and two wiring electrodes connected to the source and the drain. In the thin film transistor having a source, the surface of the semiconductor region having a high impurity concentration to be a drain, a reaction layer having a thickness of 50 to 200 Å, a wiring electrode is connected to the reaction layer, and the wiring electrode Wherein the thin film transistor does not overlap with the gate electrode. 3. A step of patterning and forming a gate electrode on a transparent substrate, a step of sequentially forming a gate insulating film, an amorphous silicon film, and a protective insulating film, and a step of coating a resist film on the protective insulating film. Attaching, exposing from the transparent substrate side and leaving on the gate electrode, etching the protective insulating film using the resist film as a mask, and etching the gas decomposed by discharge using the protective insulating film as a mask. By doping impurities into the porous silicon film
A step of forming a semiconductor region having a high impurity concentration to be a drain; a step of depositing a metal layer to form a reaction layer on an exposed surface of the semiconductor region having a high impurity concentration to be a source and a drain; and forming the source and drain. A method for manufacturing a thin film transistor, comprising: forming a semiconductor region having a high impurity concentration and a wiring electrode connected to the reaction layer after patterning the reaction layer. 4. A semiconductor region having a gate electrode, a gate insulating film, an active layer made of amorphous silicon and having a high impurity concentration serving as a source and a drain, and two wiring electrodes connected to the source and the drain. Wherein the semiconductor region having a high impurity concentration is provided in a stacked manner on an upper surface of a wiring electrode, and a reaction layer is formed so as to overlap a surface of the semiconductor region having a high impurity concentration; A thin film transistor in which an electrode is arranged so as not to overlap with a gate electrode. 5. A step of patterning and forming a gate electrode on a transparent substrate, a step of sequentially forming a gate insulating film, an amorphous silicon film, and a protective insulating film, and a step of coating a resist film on the protective insulating film. Attaching, exposing from the transparent substrate side and leaving on the gate electrode, etching the protective insulating film using the resist film as a mask, forming a semiconductor layer with a high impurity concentration, Depositing a resist film on the high semiconductor layer, exposing from the transparent substrate side and etching away the semiconductor layer on the protective insulating film to form a semiconductor region with a high impurity concentration serving as a source and a drain; and Depositing a layer and forming a reaction layer on an exposed surface of the semiconductor region having a high impurity concentration serving as the source and drain; and forming a reaction layer on the exposed surface of the semiconductor region having a high impurity concentration serving as the source and drain. Method of manufacturing a thin film transistor comprising the steps of forming a wiring electrode connected to the reaction layer after subjected to patterning in the body region and the reaction layer.