JP3352191B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a method for manufacturing a thin film transistor applied to an active liquid crystal display device and the like.

[0002]

2. Description of the Related Art Conventionally, a so-called active type liquid crystal display device using a non-single-crystal silicon thin film transistor (hereinafter referred to as TFT) as a switching element has been proposed as a liquid crystal display device for obtaining a high-definition image.
It has already been put to practical use.

[0003] Non-single-crystal TFTs put into practical use as liquid crystal display devices include amorphous silicon (hereinafter referred to as a-type TFTs).
Notated as si. A) the a-si TFT using the semiconductor layer as a semiconductor layer;
There are two types of poly-si TFTs using crystalline silicon (hereinafter referred to as poly-si) for the semiconductor layer.

As a structure of a TFT, a coplanar type and a stagger type are generally well known.
In the case of (1), the stagger type (reverse stagger type) is easy in terms of the manufacturing process, and thus most of the configurations are of the (reverse) stagger type.

On the other hand, poly-siTFTs often have a coplanar structure because self-alignment technology can be used.

[0006]

However, a-s
Although the iTFT has the advantage of being able to use an inexpensive glass substrate because it can be manufactured by a low-temperature process, the carrier mobility of the TFT is small, and the peripheral drive circuit is made separately.
For example, there is a disadvantage that an IC of single crystal Si must be used.

On the other hand, the poly-siTFT has the advantage that the carrier mobility is large and the peripheral driving circuit can be formed integrally, but the film forming temperature of the semiconductor layer is set at the strain point of the glass substrate (for example, a commonly used type). However, since Corning 7059 glass requires a temperature exceeding 593 ° C.), an inexpensive glass substrate cannot be used, and an expensive quartz substrate must be used. FIG. 8 shows a graph of the shrinkage ratio of the glass with respect to the heat treatment temperature. 71 is Corning 7059 glass, 72
Is for BLC glass.

[0008]

In a method of manufacturing a thin film transistor using thin film silicon as a semiconductor layer, when a silicon semiconductor layer is formed on a substrate, a first semiconductor layer on the gate electrode side of the semiconductor layer is formed as a semiconductor layer.
Plasma CV under a gas atmosphere containing iF ₄ and SiH ₄
A first step of forming crystalline silicon using the D method;
As a second semiconductor layer on the side opposite to the gate electrode of the semiconductor layer, by a plasma CVD method in a gas atmosphere in which the ratio of SiF ₄ to SiH ₄ is smaller than the gas atmosphere when forming the first semiconductor layer. The method includes a second step of forming amorphous silicon, and does not break a vacuum between the first step and the second step.

According to the method of manufacturing a thin film transistor of the present invention, a TFT having a large carrier mobility and a large off resistance, that is, a large on / off ratio can be provided at a low temperature.

Further, there is an advantage that a peripheral driving circuit can be formed on a glass substrate.

As described above, since the poly-si has a low resistivity and a large off power supply of the TFT,
In order to reduce the leakage current at the time of f, in the present invention, the region of the semiconductor layer on which the channel is not formed, which is opposite to the gate electrode, is formed of a-si, and the semiconductor layer on the gate side which forms the channel is poly-. It consists of si.

In such a semiconductor layer, the semiconductor layer on the gate electrode side is poly-si formed by plasma CVD in a gas atmosphere containing SiF ₄ and SiH _4, and the layer on the side opposite to the gate electrode has an amount of SiF ₄ . Can be realized by forming an a-si by plasma CVD.

FIG. 4 shows a flow ratio SiH ₄ and SiF _4.
The relationship between the flow rate ratio when forming a film of H ₄ / SiF ₄ and the half width (F, W, H, M) around 520 cm ^{−1 of the} Raman spectrum indicating the crystallinity of the Si film is shown.

[0014] SiH ₄ / SiF ₄ showed an amorphous structure is 9% or more, SiH ₄ / SiF ₄ is less than 9% p
It is shown to be poly-si. SiH ₄ / S
When iF ₄ = 3%, the particle size of poly-si was 200 nm. When SiH ₄ / SiF ₄ = 0, no Si film was deposited.

FIG. 5 shows the SiH ₄ / SiF ₄ ratio and the resistivity α.
Shows the relationship. When SiH ₄ / SiF ₄ is 9% or more, the resistivity increases, and when it is less than 9%, the resistivity decreases.
Corresponds to the crystallinity of the i-film.

It is unclear why dilution with SiF ₄ causes crystallization. However, SiF ₄ has an etching property, the etching action and the depositing action proceed in parallel, and hydrogen and other substances bonded to Si have to be etched. It is conceivable that F of SiF ₄ may have extracted the impurity element of (2).

[0017]

(Embodiment 1) FIG. 1 is a process diagram showing an example of the method of the present invention.

A gate electrode 2 is formed on a glass substrate 1 (Corning 7059 glass) using a metal such as Cr, Al, or Ta.

Thereafter, as shown in FIG. 1B, a plasma CVD (hereinafter referred to as P-type) is formed on the glass substrate 1 on which the gate electrode is formed.
A silicon nitride film (hereinafter referred to as SiN _x ) is formed by a CVD method.
A gate insulating film 3 composed of
Formed. At this time, the SiN _x has a gas flow ratio of NH ₃
/ SiH ₄ = 10: 1, R-F of P-CVD, power density 20 mw / cm ² , film forming pressure 27 Pa...

Thereafter, the first semiconductor layer 4 made of poly-si is set to have a gas flow ratio of SiH ₄ : SiF ₄ = 1: 30, R, F, power 20 mw / cm ² , and a film forming pressure of 13 P.
a, It was formed with a thickness of 100 nm under the condition of a substrate temperature of 400 ° C.

Then, without breaking the vacuum, the second semiconductor layer 5 made of a-si is diluted with hydrogen using SiH ₄ (flow ratio SiH ₄ : H ₂ = 1: 10) to obtain R, F, and power. 12mw / cm ² , pressure 66Pa, substrate temperature 300 ° C
Under a condition of 200 nm in thickness.

The ohmic contact layer, poly-
The sin ⁺ layer 6 was formed with a thickness of 100 nm. poly
The formation condition of the −sin ⁺ layer is PH ₃ / SiH ₄ = 200
0 ppm, SiH ₄ / SiF ₄ = 0.03, RF power 40 mw / cm ² , and substrate temperature 300 ° C.

Subsequently, as shown in FIG.
With respect to the second semiconductor layer and the poly-sin ⁺ layer, only a portion 7 used as a TFT was left in an island shape.

After this step, necessary contact holes (not shown) were opened.

As shown in FIG. 2D, the material becomes a sort / drain electrode material. For example, a metal 8 such as Al, Cr, and Ti was deposited by a sputtering method, and further patterned into a predetermined wiring shape. Thereafter, a transparent electrode such as ITO serving as a pixel electrode was deposited by a sputtering method and patterned into the shape of the pixel electrode 9.

Next, as shown in FIG. 2E, the sort / drain electrode material is patterned into desired drain electrode 8 (a) and source electrode 8 (b) shapes, and furthermore, a poly-sin ^{+ which} does not require a channel portion. The layer was removed. At this time, the drain electrode 8 is used as a mask for removing the channel portion of the n ⁺ layer.
(A) The resist used as a mask when patterning the source electrode 8 (b) may be used as it is as a mask, or the resist may be peeled off after patterning the drain electrode and the source electrode, The source electrode may be used as a mask.

Thereafter, as shown in FIG. 2F, a SiN _x film 10 as a passivation film is formed on the entire substrate by P-CVD.
Deposited by the method.

At this time, the temperature for forming the TFTs was all lower than the strain point of the glass substrate.

From the shrinkage ratio of the glass substrate shown in FIG. 8, for example, when the shrinkage ratio is 200 ppm, the shrinkage is 60 μm when the substrate length is 300 mm.

Therefore, in consideration of pattern shift and distortion, it is necessary to perform all steps of TFT fabrication at a temperature lower than the strain point of glass by 150 ° C. or more.

Thereafter, opposing glass substrates were bonded together, and liquid crystal was injected between the substrates to complete a liquid crystal display device.

FIG. 7 is a schematic view of a P-CVD apparatus in which a TFT is formed in the embodiment of the present invention.

Reference numeral 61 denotes a load chamber for inserting a substrate, 62 denotes a film forming chamber for forming a gate insulating film by a P-CVD method, 63 denotes a film forming chamber for forming a first semiconductor layer, and 64 denotes a film forming chamber for forming a second semiconductor layer. The reference numeral 65 denotes a film formation chamber for forming an n ⁺ layer, and the reference numeral 66 denotes an unload chamber for taking out a substrate. The substrates are transported from 61 to 66 without exposure to the atmosphere.

An exhaust system 67 is connected to each chamber.
A gate valve 68 is provided between each chamber, and separates the rooms.

In this embodiment, the first semiconductor layer and the second semiconductor layer are formed in separate chambers in order to increase the throughput of the process.

FIG. 3 is a sectional view of one pixel of a liquid crystal display device manufactured by using the present invention.

In FIG. 3, the TFT 7 has a polarizing plate 1 on the back.
1 is formed on a glass substrate 1.

The liquid crystal display has a polarizing plate 18 on the back (outside).
A color filter 15 and a black matrix 16 above the bus lines of TFT, drain and gate are provided on the liquid crystal side, and a common electrode 14 made of a transparent electrode such as ITO is formed thereon. And TFT
The liquid crystal 13 was injected between the glass substrates on which was formed.

Here, 12 (a) and 12 (b) are opposing electrodes for holding a storage capacitor provided in parallel with the liquid crystal in order to hold the potential of the liquid crystal.

FIG. 6 shows the Vg-Id characteristics of the inverted stagger type TFT.

Reference numeral 51 denotes a T formed by the manufacturing method of the embodiment.
The Vg-Id characteristic of the FT is denoted by reference numeral 52, in which all the semiconductor layers are formed with a gas flow ratio of SiF ₄ : SiH ₄ = 1: 30, and all layers po
5 is a Vg-Id characteristic of a TFT composed of ly-si. 5
3 is a Vg-Id characteristic of an a-si TFT prepared by diluting the entire semiconductor layer with only SiH ₄ (without SiF ₄ ) to SiH ₄ / H ₂ = 0.1. In the case of No. 51, the on characteristic was almost close to the on characteristic of the TFT of all layers poly-si, and the off characteristic was between 52 and 53.

The mobility of 51 in this embodiment is 45 cm ² / V
S, which is almost the same as the mobility 50 cm ² / V · S of 52 composed of all layers poly-si, and greatly increased compared to the mobility 0.5 cm ² / V · S of 53 of all layers a-si are doing.

(Embodiment 2) In Embodiment 1, the method of manufacturing an inverted staggered TFT has been described. However, the other three structures αTFT, namely, a normal staggered type, a lower coplanar type (electrode is on the substrate side), and an upper coplanar type. (The electrode was on the side opposite to the substrate). For these TFTs, only the order in which poly-si and a-si are deposited changes depending on whether the gate electrode is on the substrate side or on the opposite side of the substrate with the semiconductor layer interposed therebetween. Same as Example 1.

[0044]

As described above, according to the method for manufacturing a thin film transistor of the present invention, a TFT having a large mobility and a large off resistance can be provided at a low temperature.

Further, a peripheral driving circuit can be formed on a glass substrate.

[Brief description of the drawings]

FIG. 1 is a schematic view showing one example of a manufacturing process of a TFT of the present invention.

FIG. 2 is a schematic view showing one example of a manufacturing process of the TFT of the present invention.

FIG. 3 is a diagram showing a liquid crystal display device using the TFT of the present invention.

FIG. 4 is a graph showing the gas flow rate SiH ₄ / SiF ₄ ratio and the crystallinity of the obtained film.

FIG. 5: Gas flow rate SiH ₄ / SiF ₄ ratio and α of the obtained film
The figure of the graph which shows the relationship of.

FIG. 6 is a graph showing a Vg-Id characteristic of a TFT.

FIG. 7 is a schematic diagram of a P-CVD film forming apparatus.

FIG. 8 is a graph showing the contraction of glass.

[Explanation of symbols]

Reference Signs List 1 glass substrate 2 gate electrode 3 gate insulating film 4 first semiconductor layer 5 second semiconductor layer 6 n ⁺ layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/205 C23C 16/24 C23C 16/50

Claims (3)

(57) [Claims] In a method of manufacturing a thin film transistor using thin film silicon as a semiconductor layer, when forming a silicon semiconductor layer on a substrate, SiF ₄ and SiH ₄ are used as a first semiconductor layer on the gate electrode side of the semiconductor layer. A first step of forming crystalline silicon using a plasma CVD method in a gas atmosphere containing the first semiconductor layer, and a step of forming the first semiconductor layer as a second semiconductor layer opposite to a gate electrode of the semiconductor layer. S for SiH ₄ compared to gas atmosphere
Plasma CV in a gas atmosphere having a reduced proportion of iF ₄
A method for manufacturing a thin film transistor, comprising: a second step of forming amorphous silicon by a method D, wherein a vacuum is not broken between the first step and the second step. 2. The method according to claim 1, wherein the second semiconductor layer is formed after the formation of the first semiconductor layer, and the substrate temperature during the formation of the second semiconductor layer is lower than the substrate temperature during the formation of the first semiconductor layer. The method for manufacturing a thin film transistor according to claim 1, wherein: 3. The method according to claim 1, wherein the step of manufacturing the thin film transistor is performed at a temperature lower by at least 150 ° C. than a strain point of glass serving as a substrate.