KR100370451B1 - Method for manufacturing amorphous silicon thin film transistor and liquid crystal display using simple process - Google Patents

Abstract

PURPOSE: A method for manufacturing an amorphous silicon TFT(Thin Film Transistor) and an LCD(Liquid Crystal Display) using a simple process is provided to be capable of effectively reducing parasitic capacitance and improving productivity. CONSTITUTION: A gate electrode(11) is formed on an insulating substrate(10). Then, a gate isolating layer(12) made of a silicon nitride layer and a channel active layer(13) made of an amorphous silicon layer are sequentially formed on the resultant structure. An SiOF thin film(14) is formed on the channel active layer as an etching mask and an ion implanting mask. Then, a source/drain electrode(16) are selectively formed on the resultant structure. A silicide layer is formed at the source/drain electrode region as an ohmic contact layer.

Description

Method for manufacturing amorphous silicon thin film transistor and liquid crystal display device (LCD) by simple process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors used as switching elements of LCDs, and more particularly, to a method capable of reducing the number of masks when fabricating a fully self-aligning thin film transistor using two masks and applying them to LCDs.

In general, a thin film transistor (hereinafter referred to as a TFT) used as a switching element for driving a pixel electrode of an LCD is staggered in which a gate electrode and a source / drain electrode are separated with an active semiconductor layer interposed therebetween. The molds are largely classified into coplanar types in which gate electrodes and source / drain electrodes are formed on one surface of the semiconductor.

Such thin film transistors include thin film transistors using amorphous silicon or polycrystalline silicon and thin film transistors using compound semiconductors, depending on the material of the active layer. Among these, amorphous silicon (hereinafter referred to as a-Si: H) thin film transistor has excellent advantages in terms of mass production and large area. However, in general, parasitic capacitance generated between the gate electrode and the source / drain electrode of a thin film transistor causes a delay effect of the gate pulse, thereby causing a TFT-LCD image such as flicker and residual image. There is a problem that causes quality deterioration. Therefore, by reducing the overlap length between the gate and the source / drain which are generally present in the thin film transistor, the parasitic capacitance can be reduced to improve flicker and afterimage on the TFT-LCD image, thereby improving the image quality of the TFT-LCD.

In general, parasitic capacitance is generated by the overlap length between a gate electrode and a source / drain electrode in an inverted staggered thin film transistor. This parasitic capacitance causes flicker and image retention in an image in a liquid crystal display device using an inverted staggered thin film transistor as a switching element. In the present invention, two parasitic masks effectively reduce parasitic capacitance. A method of manufacturing a self-aligning thin film transistor is provided. In addition, when applied to LCD production, it is possible to produce LCD with fewer masks than existing methods, so productivity and cost reduction effect can be expected.

1 is a cross-sectional structural diagram (a) and a planar structural diagram (b) of a fully self-aligned thin film transistor using two masks according to an embodiment of the present invention.

2 is a graph showing field effect mobility characteristics of a fully self-aligned thin film transistor using two masks according to an embodiment of the present invention.

3 is a graph showing the log drain current-gate voltage characteristics of a fully self-aligned thin film transistor using two masks according to an embodiment of the present invention.

4 is a graph showing output characteristics of a fully self-aligned thin film transistor using two masks according to an embodiment of the present invention.

5 is a flowchart of manufacturing an LCD according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10 insulating substrate 11 gate electrode

12: gate insulating film (silicon nitride film)

13: active layer (amorphous silicon layer)

14 etching mask / ion implantation mask (fluorine-containing silicon oxide film:

Referred to as SiOF, Benzo CycloButene: referred to as BCB,

Silicon nitride film)

15: high concentration ion impurity amorphous layer

16 source / drain electrode (silicide layer)

In order to achieve the above object, the present invention is characterized in that two masks are used in a fully self-aligned thin film transistor in which a source / drain electrode using a gate, a gate insulating film, a channel active layer, and silicide is formed on an insulating substrate.

In a fully self-aligned thin film transistor having a gate, a gate insulating film, a channel active layer and a source / drain electrode using silicide formed on an insulating substrate according to an embodiment of the present invention, SiOF, BCB thin film is used.

In a fully self-aligned thin film transistor in which a source / drain electrode using a gate, a gate insulating film, a channel active layer, and silicide is formed on an insulating substrate, the source / drain electrodes are formed in a self-aligning manner. .

The data line of the LCD manufactured according to the embodiment of the present invention is characterized in that the silicide layer and the transparent electrode (ITO).

LCD manufactured according to an embodiment of the present invention is characterized in that the number of one or two masks can be reduced than the conventional process.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a cross-sectional structure of a fully self-aligned thin film transistor using SiOF or BCB as an etching mask / ion implantation mask according to an embodiment of the present invention.

Referring to FIG. 1, in the thin film transistor according to the exemplary embodiment, the gate 11 is formed on a predetermined portion of the insulating substrate 10. The gate 11 is formed to have slopes at both sides in order to improve step coverage of the thin films formed in a subsequent process, and is formed of metal such as Cr or Al. The gate insulating film 12 is formed on the insulating substrate 10 including the gate 11. In FIG. 1, a silicon nitride film is used as the gate insulating film 12. As shown in FIG. The active layer 13 is formed on the gate insulating film 12 above the gate 11. In the present invention, an amorphous silicon layer is formed as the active layer 13, but a hydrogenated amorphous silicon film, a polycrystalline silicon film, or a compound semiconductor may be used. A portion of the active layer 13 corresponding to the gate 11 becomes a channel region. A thin film of SiOF or BCB 14 is formed as an ion implantation mask or an etching mask on the channel region to protect the channel region of the active layer from the high concentration ion implantation for forming a low ohmic contact layer in the source / drain electrode region. Nickel is deposited by sputtering to form a source / drain electrode to form a source / drain electrode.

A method of manufacturing a fully self-aligned thin film transistor having a low dielectric constant SiOF or BCB thin film as an ion implantation mask / etch mask according to an embodiment of the present invention having the structure as described above is as follows.

First, a metal film such as Cr, Al, etc. is deposited on the insulating substrate 10, and then the gate 11 is formed by inclined etching, and the gate insulating layer 12 is formed on the insulating substrate 10 including the gate 11. Form. A nitride film is deposited as a gate insulating film on an insulating substrate using NH ₃ , SiH ₄ , Hc mixed gas by plasma excitation. The silicon nitride film (thickness: 1,000 to 3,500 kPa) is deposited at a substrate temperature of 280 ° C to 300 ° C, RF power of 80 W, and gas pressure of 520 mTorr.

Next, an amorphous silicon layer is deposited on the gate insulating film 12. At this time, the amorphous silicon layer, which is the active layer 13, is deposited in the CVD apparatus under the deposition conditions in which the xylene (SiH ₄ ) gas flow rate is 1.0 sccm, the substrate temperature is 280 to 300 ° C., the RF power is 40 W, and the gas pressure is 100 mTorr. do. Next, a SiOF thin film is deposited as an ion implantation mask for forming a resistive contact layer implanted with high concentration ions, or the BCB thin film is coated by a spin coating method (4000 / rpm, 30 seconds). SiOF thin films are four days alkylene (SiH ₄₎ gas flow rate of 0.5 sccm, SiF ₄ gas flow rate of 5 sccm, O ₂ gas flow rate 40 sccm, He gas flow rate of 100 sccm, a substrate temperature of 300 ℃, RF power 80 W, gas pressure is 190 mTorr It deposits at 1,500-3,000 Pa by phosphorus conditions. Subsequently, SiOF or BCB thin films are removed in all regions except the upper layer of the active layer channel region and the gate electrode region by a back exposure method. Phosphine (PH ₃ ) gas flow rate is 0.1 sccm, RF Power is 10 W, acceleration voltage is 3 kV, and substrate temperature is 200 Doping is carried out by the ion shower method under the conditions.

Subsequently, a nickel film is deposited on the entire surface of the substrate with an RF power of 80 W and a thickness of 400 kW by the RF sputtering method. Nickel source / drain electrodes are formed through exposure etching to form the low resistance contact layer and source / drain electrodes, and gate electrode contact holes are also formed. Heat treatment is performed at 200 ° C. for 1 hour to form silicide of the formed source / drain electrode regions of nickel. Through the heat treatment, the silicide 16 is formed on the amorphous silicon into which the high concentration impurity is implanted at the source / drain electrode, and the nickel on the stopper 14 layer does not react with SiOF or BCB used as the stopper. When the nickel is completely etched, silicide is formed only at the source / drain electrodes. Thus, a fully self-aligned thin film transistor having an SiOF or BCB thin film as an etching mask / ion implantation mask is obtained. In addition, although an amorphous silicon layer is formed as the active layer 13 in the embodiment of the present invention, a hydrogenated amorphous silicon film, a polycrystalline silicon film, or a compound semiconductor may be used.

FIG. 2 is a graph showing field effect mobility (μ _FE ) of a fully self-aligned amorphous silicon thin film transistor using an SiOF thin film prepared according to an embodiment of the present invention as an etching mask / ion implantation mask.

The threshold voltage (V _TH ) obtained from Eq. (5 _TH ) is approximately 5.72V and the field effect mobility (μ _FE ) is 0.55 cm 2 / Vs. Where I _D is the drain voltage, μ _FE is the field effect mobility, W is the width of the channel, L is the length of the channel, C _i is the capacitance of the insulating film, V _TH is the threshold voltage, and V _D is the drain voltage.

FIG. 3 is a graph showing log drain current-gate voltage characteristics of a fully self-aligned amorphous silicon thin film transistor using an SiOF thin film manufactured by the structure of FIG. 1 according to an embodiment of the present invention as an etching mask / ion implantation mask. The on / off current ratio of the hydrogenated amorphous silicon thin film transistor fabricated in this example was measured to be ≥ 10 ⁶ .

4 is a graph showing output characteristics of a fully self-aligned amorphous silicon thin film transistor using an SiOF thin film manufactured by the structure of FIG. 1 as an etching mask / ion implantation mask. As shown, the W / L of the TFT, where W represents the width of the TFT channel and L represents the length, is 60 μm / 19 μm, and when the gate voltage is 20 V, the implementation of the present invention Shows that the drain current of the thin film transistor fabricated according to the present invention is saturated at 3.4 × 10 ⁻⁶ A.

5 is a diagram illustrating an example in which a fully self-aligned thin film transistor using the two masks shown in FIG. 1 is applied to LCD manufacturing. First, the gate electrode and the storage capacitor are formed by using the first mask. Subsequently, a gate insulating layer and an amorphous silicon layer are deposited, and SiOF or SiNx is deposited as a layer serving as an etching and ion implantation mask, or BCB is coated by spin coating. Next, a stopper is formed by a backside exposure method and doped by an ion shower method to form a high concentration of ion impurity amorphous layer. Next, nickel is deposited by a sputtering method to form a source / drain data line, and then a source / drain data line is formed using the second mask. In this case, doped amorphous silicon remains in the portion forming the source / drain data line. Subsequently, in order to form a silicide layer on the source / drain data line, nickel is not annealed after the heat treatment at 200 ° C. for 1 hour. Next, a transparent electrode is deposited to form a pixel electrode and a data line, and a pixel electrode and a data line are formed using a mask # 3. Finally, a protective film is deposited and an electrode contact hole is formed. As shown in the figure, two masks are required to complete the switching element, a fully self-aligned amorphous silicon thin film transistor, one mask is required to form the data line and the pixel electrode, and one mask is formed in the protective layer and the gate contact hole. LCD can be manufactured with a total of four masks.

As described above, according to the present invention, the overlap length between the gate electrode and the source / drain electrode is fabricated by using a SiOF and BCB thin film as an etching mask / ion implantation mask and fabricating a fully self-aligned amorphous silicon thin film transistor using two masks. Can effectively reduce the parasitic capacity generated by Since SiOF and BCB are low dielectric constant materials, gate signal delay can be reduced compared to using amorphous silicon nitride as a protective film (Kyung WooK Kim, Kyu SiK Cho, Jai I1 Ryu, Keon Ho Yoo and Jin Jang, IEEE EDL vol. 21, pp. 301-303, 2000), can reduce signal interference occurring at the intersection of the gate electrode and the data electrode. In addition, the number of masks required for LCD manufacturing is reduced by one or two compared to the existing manufacturing process, which can improve productivity and reduce costs.

Claims (8)

In a thin film transistor in which a gate electrode, an active layer, and a source / drain electrode are formed on an insulating substrate, an etch mask / ion implant mask on a highly active ion implanted silicon layer as a resistive contact layer or a channel active layer for forming a high concentration n ⁺ silicon layer A thin film transistor, characterized in that the SiOF thin film is formed. Forming a gate on the insulating substrate, Forming a SiOF thin film as an etch mask / ion implantation mask on the channel active layer; Forming an SiOF thin film and a source / drain electrode on the channel active layer to be offset; Forming a silicide as an ohmic contact layer of the source / drain electrode region. The self-aligned thin film transistor of claim 1, wherein the SiOF thin film and the source / drain electrodes are offset as an etching mask / ion implantation mask on the active layer. The thin film transistor of claim 1, wherein silicide is formed on the n + silicon layer. The thin film transistor of claim 1, wherein silicide is formed on the n + silicon layer. The method of manufacturing a thin film transistor according to claim 2, wherein only two masks are used. A manufacturing method for forming a data line by laminating a silicide layer and a transparent electrode in LCD production. Forming a gate electrode and a storage capacitor on the insulating substrate; Forming a SiOF thin film as an etch mask / ion implantation mask on the channel active layer; Forming an SiOF thin film and a source / drain electrode on the channel active layer to be offset; Forming a silicide as an ohmic contact layer of the source / drain electrode region; Forming the data line by laminating a silicide and a transparent electrode.