JPH03114234A - Thin film transistor and its manufacture - Google Patents
Thin film transistor and its manufactureInfo
- Publication number
- JPH03114234A JPH03114234A JP25044889A JP25044889A JPH03114234A JP H03114234 A JPH03114234 A JP H03114234A JP 25044889 A JP25044889 A JP 25044889A JP 25044889 A JP25044889 A JP 25044889A JP H03114234 A JPH03114234 A JP H03114234A
- Authority
- JP
- Japan
- Prior art keywords
- film
- active layer
- films
- silicon nitride
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims description 125
- 238000000034 method Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000005224 laser annealing Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 description 8
- 101100054070 Rattus norvegicus Andpro gene Proteins 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241001239379 Calophysus macropterus Species 0.000 description 1
- 229910016024 MoTa Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、薄膜トランジスタおよびその製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a thin film transistor and a method for manufacturing the same.
（従来の技術） エレクトロルミネッセンス、発光ダイオード。(Conventional technology) Electroluminescence, light emitting diode.
プラズマ、蛍光表示、液８品等の表示デバイスは、表示
部の薄型化が可能であり計／１１１ｊ機器、事務機器や
コンピュータ等の端末表示装置あるいは特殊な表示装置
への用途として要求が高まっている。これらの中で薄膜
トランジスタのスイッチング素子マトリックスアレイを
用いたエレクトロルミネッセンスや液晶表示装置は、低
消費電力化や低コスト化が可能であるために表示デバイ
スとして注目されている。Display devices such as plasma, fluorescent displays, and liquid 8 types can have thinner display parts, and are in increasing demand for use in terminal display devices such as total/111J equipment, office equipment, and computers, or special display devices. There is. Among these, electroluminescent and liquid crystal display devices using switching element matrix arrays of thin film transistors are attracting attention as display devices because they can reduce power consumption and cost.
このようなスイッチングトランジスタの材料としては結
晶、多結晶、アモルファス状態のＳｉ。Materials for such switching transistors include crystalline, polycrystalline, and amorphous Si.
ＣｄＳｅ、Ｔｅ、ＣｄＳ等が用いられている。この中で
も多結晶半導体やアモルファス半導体は、低温プロセス
の薄膜技術が適応可能なためにガラス基板等の比較的低
温で取扱うことの必要な基板上にもスイッチングトラン
ジスタのアクティブマトリックス素子を形成することが
でき、低価格で大面積の表示装置を実用段階にした。CdSe, Te, CdS, etc. are used. Among these, polycrystalline semiconductors and amorphous semiconductors can be used to form active matrix elements of switching transistors even on substrates that need to be handled at relatively low temperatures, such as glass substrates, because thin film technology for low-temperature processes can be applied. , brought a low-cost, large-area display device to the practical stage.
このような中で、活性層に半導体膜と絶縁膜の多層膜を
用いた薄膜トランジスタが提唱されており （Ｍ、
Ｔｓｕｋｕｄｅ ｅｔ ａｌ
Ｊ、 Ｊ。Under these circumstances, thin film transistors using a multilayer film of a semiconductor film and an insulating film in the active layer have been proposed (M,
Tsukude et al.
J, J.
Ａ、Ｐ、Ｖｏｌ、２６．Ｎｏ、２．Ｌｌｌｌ）、半導体
膜単層を用いた場合よりも電界効果移動度が大きく増大
するいう結果が得られている。A, P, Vol, 26. No, 2. (Lllll), results have been obtained that the field effect mobility is significantly increased compared to the case where a single semiconductor film is used.
第７図は、活性層に半導体膜と絶縁膜の多層膜を用いた
従来の薄膜トランジスタ（Ｔ Ｐ Ｔ）の断面図である
。FIG. 7 is a cross-sectional view of a conventional thin film transistor (TPT) using a multilayer film of a semiconductor film and an insulating film as an active layer.
ガラス板のような透光性絶縁基板５１上にＭ。M on a transparent insulating substrate 51 such as a glass plate.
やＣｒのような金属パターンでゲート電極５２が形成さ
れ、ゲート電極５２上はＳｉＮｘ等のゲート絶縁膜５３
で覆われている。ゲート絶縁膜５３上のゲート電極５２
上に位置するところに、非晶質シリコン（ａ −Ｓ ｉ
）の半導体膜５４とＳｉＮｘからなる絶縁膜が交互に積
層された多層膜５４が所定のパターンに形成されている
。この多層膜５４上にはＳｉＮｘからなる保護膜５５が
形成されている。多層膜５４の相対向する端面にソース
電極５６．ドレイン電極５７が形成されている。ソース
電極５６．ドレイン電極５７と多層膜５４の間には、オ
ーミックコンタクト層としてｎ”ａ−５ｉ層５８が形成
されいる。A gate electrode 52 is formed with a metal pattern such as or Cr, and a gate insulating film 53 such as SiNx is formed on the gate electrode 52.
covered with. Gate electrode 52 on gate insulating film 53
At the top, amorphous silicon (a-S i
) A multilayer film 54 is formed in a predetermined pattern by alternately stacking a semiconductor film 54 and an insulating film made of SiNx. A protective film 55 made of SiNx is formed on this multilayer film 54. Source electrodes 56 . are provided on opposing end surfaces of the multilayer film 54 . A drain electrode 57 is formed. Source electrode 56. Between the drain electrode 57 and the multilayer film 54, an n''a-5i layer 58 is formed as an ohmic contact layer.
このような従来構造のＴＰＴでは、活性層である多層膜
５４の端面とｎ”ａ−３ｉ層５８の間でソース電極５６
．ドレイン電極５７とのオーミックコンタクトをとって
いるために、ｎ”ａ−８ｉ層５８のステップカバレージ
が完全でないと、良好なオーミックコンタクトがとれず
、ＴＦＴＭ性が不良になるという問題があった。また少
数のＴＰＴを生産する場合には、良好なオーミックコン
タクトが取れても、多数の場合には、いくつか不良が発
生することや、ＴＰＴ特性の再現性が得られにくいとい
うことから、量産性に関しても問題があった。In a TPT having such a conventional structure, the source electrode 56 is connected between the end surface of the multilayer film 54 serving as the active layer and the n''a-3i layer 58.
．． Since ohmic contact is made with the drain electrode 57, if the step coverage of the n''a-8i layer 58 is not complete, good ohmic contact cannot be made, resulting in poor TFTM properties. When producing a small number of TPTs, even if good ohmic contact can be made, when producing a large number of TPTs, some defects may occur, and it is difficult to obtain reproducibility of the TPT characteristics, so there are issues regarding mass production. There was also a problem.
（発明が解決しようとする課題）
以上のように従来のＴＰＴでは、活性層と半導体膜との
間で完全なオーミックコンタクトが取りにくいので、Ｔ
ＰＴが不良になったり、量産に向かないという問題があ
った。(Problems to be Solved by the Invention) As described above, in the conventional TPT, it is difficult to make perfect ohmic contact between the active layer and the semiconductor film, so the TPT
There were problems with PT becoming defective and not being suitable for mass production.
本発明は、上記事情を考慮してなされたもので、その目
的とするところは、半導体膜と絶縁膜の多層膜を活性層
として用いた薄膜トランジスタのオーミックコンタクト
特性を改善し、再現性、量産性の向上を図った薄膜トラ
ンジスタ及びその製造方法を提供することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to improve the ohmic contact characteristics of a thin film transistor using a multilayer film of a semiconductor film and an insulating film as an active layer, and to improve reproducibility and mass production. An object of the present invention is to provide a thin film transistor with improved performance and a method for manufacturing the same.
［発明の構成コ
（課題を解決するための手段）
第１の発明は、活性層に半導体膜と絶縁層の多層膜を用
いた薄膜トランジスタにおいて、活性層のソースおよび
ドレイン電極がコンタクトする端面を傾斜面とする。[Structure of the Invention (Means for Solving the Problems)] The first invention is a thin film transistor using a multilayer film of a semiconductor film and an insulating layer as an active layer, in which the end faces of the active layer with which the source and drain electrodes are in contact are inclined. Make it a face.
第２の発明は、活性層に半導体膜と絶縁層の多層膜を用
いた薄膜トランジスタにおいて、前記活性層とソース、
ドレイン電極とのコンタクト層にｎ型シリコン窒化膜を
用いる。A second invention provides a thin film transistor using a multilayer film of a semiconductor film and an insulating layer as an active layer, in which the active layer and a source,
An n-type silicon nitride film is used as a contact layer with the drain electrode.
第３の発明は、活性層にシリコン膜とシリコン窒化膜の
多層膜を用いた薄膜トランジスタを製造する際に、前記
多層膜のソースおよびドレイン電極とのコンタクト部に
、ｎ型不純物をドーピングしながらレーザ・アニールし
てｎ型のシリコン窒化膜からなるオーミックコンタクト
層を形成する。A third aspect of the invention is to manufacture a thin film transistor using a multilayer film of a silicon film and a silicon nitride film as an active layer, while doping n-type impurities into the contact portions of the multilayer film with source and drain electrodes. - Anneal to form an ohmic contact layer made of an n-type silicon nitride film.
（作用）
本発明によれば、半導体膜と絶縁膜の多層膜からなる活
性層のソース、ドレイン側端面形状をテーバ状あるいは
階段状の傾斜面にして前記活性層が基板側に順次大なる
ようにすると、活性層の厚みおよびチャンネル幅を従来
の場合と同じにしたとき、従来よりもソース、ドレイン
電極の接触面積が大きくなるのでオーミックコンタクト
が改善される。(Function) According to the present invention, the source and drain side end faces of the active layer made of a multilayer film of a semiconductor film and an insulating film are formed into tapered or stepped slopes so that the active layer gradually increases in size toward the substrate. In this case, when the thickness of the active layer and the channel width are kept the same as in the conventional case, the contact area between the source and drain electrodes becomes larger than in the conventional case, so that ohmic contact is improved.
また不純物をドーピングしながらレーザ・アニルを行う
、いわゆるレーザ・ドーピングにより活性層の端面にｎ
型のシリコン窒化膜からなるコンタクト層を形成する方
法にすればコンタクト層が活性層と別工程で堆積、パタ
ーニングされる従来法に比べて確実に低抵抗のオーミッ
クコンタクトがとれる。In addition, by performing laser annealing while doping impurities, so-called laser doping, the end face of the active layer is
By forming a contact layer made of a silicon nitride film, a low-resistance ohmic contact can be made more reliably than in the conventional method in which the contact layer is deposited and patterned in a separate process from the active layer.
（実施例）
実施例１
第１図は、本発明の第１の実施例に係わる薄膜トランジ
スタの断面図である。これを製造工程に従い説明すると
、最初にガラス基板からなる透光性絶縁基板１上に厚さ
約２０００人のＴａあるいはＭｏＴａ合金等の金属膜に
よりゲート電極２を作る。次にＣＶＤ法により、第１ゲ
ート絶縁膜であるシリコン酸化膜３を約３０００人、第
２のゲート絶縁膜であるシリコン窒化膜４を約５００人
形成し、ついで、活性層となるアンドープ非晶質シリコ
ン膜（ａ −Ｓ ｉ）膜５−１゜（２５人）とシリコン
窒化膜５−２ （５０人）を交互に積層した多層膜（約
１０層）５を形成し、更にその上に、第１の保護膜であ
るシリコン窒化膜６を約５００人、第２の保護膜である
シリコン酸化膜７を約２０００人順次形成する。以上の
絶縁膜およびａ−Ｓｉ膜は、プラズマＣＶＤ法あるいは
光ＣＶＤ法により形成する。とくに多層膜５に形成には
、光ＣＶＤ法を用いることが好ましい。(Example) Example 1 FIG. 1 is a sectional view of a thin film transistor according to a first example of the present invention. To explain this according to the manufacturing process, first, a gate electrode 2 is made of a metal film such as Ta or MoTa alloy with a thickness of about 2000 nm on a transparent insulating substrate 1 made of a glass substrate. Next, by CVD, a silicon oxide film 3, which is a first gate insulating film, is formed by about 3000 people, and a silicon nitride film 4, which is a second gate insulating film, is formed by about 500 people, and then an undoped amorphous film that becomes an active layer is formed. A multilayer film (approximately 10 layers) 5 is formed by alternately laminating a silicon nitride film 5-1° (25 people) and a silicon nitride film 5-2 (50 people), and then About 500 people sequentially formed the silicon nitride film 6, which is the first protective film, and about 2,000 people formed the silicon oxide film 7, which was the second protective film. The above insulating film and a-Si film are formed by plasma CVD or photo-CVD. In particular, it is preferable to use a photo-CVD method for forming the multilayer film 5.
次に、第１の保護膜６および第２の保護膜７をパターニ
ングし、それをマスクとして、活性層である多層膜５を
エツチングして基板側にいくにつれて幅が大となるよう
に、テーバをつけて加工する。このようなテーバ加工は
例えば、ａ−Ｓｉ膜５−１とシリコン窒化膜５−２に対
するエツチング速度がほぼ等しく、かつテーバ・エツチ
ングが行われるように条件設定されたＣＤＥ等により、
可能である。次に、例えばプラズマＣＶＤ法を用いて、
コンタクト層となるｎ”ａ−３ｉ膜８を約５００人形成
し、さらにスパッタリング法を用いて、Ｍｏ膜を約５０
０人、Ａｌ１膜を約１．ｃｚｍ形成し、これをパターニ
ンすることによりソース電極９、ドレイン電極１０を作
る。Next, the first protective film 6 and the second protective film 7 are patterned, and using the patterned patterns as a mask, the multilayer film 5 that is the active layer is etched so that the width becomes larger toward the substrate. Attach and process. Such Taber etching is performed, for example, by using CDE or the like in which conditions are set so that the etching rates for the a-Si film 5-1 and the silicon nitride film 5-2 are approximately equal and Taber etching is performed.
It is possible. Next, for example, using a plasma CVD method,
Approximately 500 layers of n''a-3i film 8 were formed as a contact layer, and then approximately 500 layers of Mo film were formed by sputtering.
0 people, Al1 film about 1. A source electrode 9 and a drain electrode 10 are formed by forming a czm and patterning it.
この様な構造のＴＰＴでは、端面が垂直である従来構造
と比較して、コンタクト層であるｎ”ａ−３ｉ膜８のカ
バレージが良くなる。また膜厚とチャンネル幅が従来と
同じであれば、活性層中で実際に電子が伝導するアンド
−プロ−３ｉ膜５−１とｎ″ａ−Ｓｔ膜８との接触面積
が大きくなることから、ソース、ドレイン電極９，１０
のオーミックコンタクト特性が改善される。以上により
、良好なＴＰＴ特性が得られた。In a TPT with such a structure, the coverage of the n''a-3i film 8, which is a contact layer, is better compared to a conventional structure in which the end face is vertical.Also, if the film thickness and channel width are the same as the conventional one, , since the contact area between the and-pro-3i film 5-1 and the n″a-St film 8 through which electrons actually conduct in the active layer becomes large, the source and drain electrodes 9, 10
ohmic contact characteristics are improved. As a result of the above, good TPT characteristics were obtained.
また活性層であるアンド−プロ−５ｔ膜５−１とシリコ
ン窒化膜５−２の多層膜５を光ＣＶＤにより形成した場
合には、プラズマ中の荷電粒子による損傷がなくなるこ
とから、界面特性が改善され、ＴＰＴの電界効果移動度
の増大が認められた。Furthermore, when the multilayer film 5 of the AND-PRO-5T film 5-1 and the silicon nitride film 5-2, which is the active layer, is formed by photo-CVD, there is no damage caused by charged particles in the plasma, so the interface properties are improved. It was observed that the field effect mobility of TPT was improved.
実施例２
第２図は、第２の実施例を示す薄膜トランジスタの断面
図である。なお第１図と同一機能部分には同一符号を付
し、詳しい説明は省略する。Example 2 FIG. 2 is a sectional view of a thin film transistor showing a second example. Note that the same functional parts as in FIG. 1 are denoted by the same reference numerals, and detailed explanations will be omitted.
この実施例が先に説明した第１の実施例と異なる点は、
活性層であるアンド−プロ−８ｉ膜５−１とシリコン窒
化膜５−２の多層膜５の端面形状が、リニアなテーバで
はなく、階段状構造となっていることにある。This embodiment differs from the first embodiment described above as follows:
The end face shape of the multilayer film 5 of the AND-PRO-8i film 5-1 and the silicon nitride film 5-2, which is the active layer, is not a linear tapered structure but a stepped structure.
このような構造とすることにより、アンド−プロ−Ｓｉ
膜５−１とｎ”ａ−Ｓｉ膜８との接触面積がさらに大き
くなることから、ソース、ドレイン電極９，１０のオー
ミックコンタクト特性が一層改善される。By having such a structure, and-pro-Si
Since the contact area between the film 5-1 and the n''a-Si film 8 is further increased, the ohmic contact characteristics of the source and drain electrodes 9 and 10 are further improved.
実施例３
第３図は、第３の実施例を示す薄膜トランジスタの断面
図である。なお第１図と同一機能部分には同一符号を付
し、詳しい説明は省略する。Example 3 FIG. 3 is a sectional view of a thin film transistor showing a third example. Note that the same functional parts as in FIG. 1 are denoted by the same reference numerals, and detailed explanations will be omitted.
この実施例が先に説明した実施例１，２と異なる点を以
下に述べる。The differences between this embodiment and the previously described embodiments 1 and 2 will be described below.
多層膜５を形成するまでは、実施例１，２と同様であり
、この上に保護膜としてシリコン窒化膜６で厚さ約１０
００人形成する。次に、窒化膜６のパターンを形成し、
この窒化膜６（あるいは、窒化膜６上に形成した金属膜
等）をマスクとして、レーザ・ドーピングを行う。例え
ば、ＰＨ３ガス中で、エキシマレーザからのレーザ光を
照射する。The steps up to the formation of the multilayer film 5 are the same as in Examples 1 and 2, and a silicon nitride film 6 is formed on this as a protective film to a thickness of about 10 mm.
Form 00 people. Next, a pattern of the nitride film 6 is formed,
Laser doping is performed using this nitride film 6 (or a metal film or the like formed on the nitride film 6) as a mask. For example, laser light from an excimer laser is irradiated in PH3 gas.
これにより、多層膜５のうちソース、ドレイン電極９，
１０がコンタクトする部分を変質させる。As a result, in the multilayer film 5, the source and drain electrodes 9,
10 changes the quality of the contact area.
そしてｎ型のシリコン窒化膜層８−１に変質させた部分
を含めて活性層をパターン形成した後、スパッタリング
法等を用いて、Ｍｏ膜を約５００人、ＡＩ膜を約５００
０人形成し、ソース電極９．ドレイン電極１０を作る。After patterning the active layer including the altered portion of the n-type silicon nitride film layer 8-1, a sputtering method or the like is used to form a Mo film of about 500 layers and an AI film of about 500 layers.
Form the source electrode 9. A drain electrode 10 is made.
この実施例の構造および方法によるＴＰＴでは、多層膜
５の一部がレーザ・ドーピングによってｎ型シリコン窒
化膜８−１に変換されるため、多層膜５とオーミックコ
ンタクト層を別の膜形成工程で形成するのと異なり、両
者の界面には異物が介在することはなく組織的にも完全
に連続的になる。In the TPT according to the structure and method of this embodiment, a part of the multilayer film 5 is converted into the n-type silicon nitride film 8-1 by laser doping, so the multilayer film 5 and the ohmic contact layer are formed in separate film formation steps. Unlike the conventional method, there are no foreign substances present at the interface between the two, and the structure is completely continuous.
従って、活性層中で実際に電子が伝導するアンド−プロ
−Ｓｉ膜５−１とｎ型のシリコン窒化膜８−１との接触
が良好となり、ソース、ドレイン電極９．１０とのオー
ミックコンタクト特性が改善され、良好なＴＰＴ特性が
得られる。Therefore, the contact between the and-pro-Si film 5-1, through which electrons actually conduct in the active layer, and the n-type silicon nitride film 8-1 is good, and the ohmic contact characteristics with the source and drain electrodes 9.10 are improved. is improved, and good TPT characteristics can be obtained.
本発明は、上記実施例に限られるものではない。The present invention is not limited to the above embodiments.
例えば、実施例１〜３では逆スタガー型を示したが、本
発明はコプレーナ型のＴＰＴにも適応できる。第１図〜
第３図に構成、製法をコプレーナ型ＴＰＴに適応した実
施例の構造をそれぞれ第４図〜第６図に示す。For example, in Examples 1 to 3, an inverted stagger type was shown, but the present invention can also be applied to a coplanar type TPT. Figure 1~
FIG. 3 shows the structure of an embodiment in which the construction and manufacturing method are adapted to a coplanar TPT, and FIGS. 4 to 6 respectively show the structure.
さらに、活性層である半導体膜と絶縁膜の多層膜の半導
体膜は、微結晶シリコン膜や多結晶シリコン膜でも良く
、絶縁膜は、シリコンカーバイト等でもよい。Furthermore, the semiconductor film of the multilayer film of a semiconductor film and an insulating film, which is an active layer, may be a microcrystalline silicon film or a polycrystalline silicon film, and the insulating film may be silicon carbide or the like.
［発明の効果］
本発明によれば、活性層に多層膜を用いた薄膜トランジ
スタの活性層とソース、ドレイン電極との間でのオーミ
ックコンタクトを改善することができ、ＴＰＴ特性が不
良になるということもなくなるので、再現性、ｆｆｉ産
性の高い薄膜トランジスタを得ることができる。[Effects of the Invention] According to the present invention, it is possible to improve the ohmic contact between the active layer and the source and drain electrodes of a thin film transistor using a multilayer film in the active layer, thereby eliminating the problem of poor TPT characteristics. Therefore, a thin film transistor with high reproducibility and high ffi productivity can be obtained.
第１図は、本発明の第１の実施例に関わる薄膜トランジ
スタの断面図、第２図は、第２の実施例の断面図、第３
図は、第３の実施例の断面図。
第４図〜第６図は、コプラナＴＰＴに適応した実施例の
断面図、第７図は、従来の薄膜トランジスタの断面図で
ある。
１・・・透光性絶縁基板、２・・・ゲート電極、３・・
・ゲート絶縁膜（シリコン酸化膜）、４・・・ゲート絶
縁膜（シリコン窒化膜）、５・・・半導体膜と絶縁膜の
多層膜からなる活性層、５−１・・・アンド−プロ−８
ｌ膜、５−２・・・シリコン窒化膜、６・・・保護膜（
シリコン窒化膜）、７・・・保護膜（シリコン酸化膜）
、８・・・ｎ＋ａ−８ｉ膜、８−１・ｎ型のシリコン窒
化膜、９・・・ソース電極、１０・・・ドレイン電極。
出願代理人FIG. 1 is a sectional view of a thin film transistor according to a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment, and FIG.
The figure is a sectional view of the third embodiment. 4 to 6 are cross-sectional views of an embodiment adapted to a coplanar TPT, and FIG. 7 is a cross-sectional view of a conventional thin film transistor. 1... Transparent insulating substrate, 2... Gate electrode, 3...
・Gate insulating film (silicon oxide film), 4... Gate insulating film (silicon nitride film), 5... Active layer consisting of a multilayer film of a semiconductor film and an insulating film, 5-1... And-pro- 8
l film, 5-2... silicon nitride film, 6... protective film (
silicon nitride film), 7...protective film (silicon oxide film)
, 8... n+a-8i film, 8-1... n-type silicon nitride film, 9... source electrode, 10... drain electrode. Application agent
Claims (3)
された、半導体膜と絶縁膜が交互に積層された多層膜か
らなる活性層と、この活性層の相対向する端面にコンタ
クトするソースおよびドレイン電極と、前記活性層の上
部または下部にゲート絶縁膜を介して配設されたゲート
電極とを有する薄膜トランジスタにおいて、前記活性層
の前記ソースおよびドレイン電極がコンタクトする端面
を傾斜面としたことを特徴とする薄膜トランジスタ。(1) A substrate, an active layer formed in a predetermined pattern on this substrate and consisting of a multilayer film in which semiconductor films and insulating films are alternately laminated, and a source and a drain that are in contact with opposing end surfaces of this active layer. A thin film transistor having an electrode and a gate electrode disposed above or below the active layer with a gate insulating film interposed therebetween, characterized in that end faces of the active layer with which the source and drain electrodes are in contact are sloped faces. thin film transistor.
された、半導体膜と絶縁膜が交互に積層された多層膜か
らなる活性層と、この活性層の相対向する端面にコンタ
クトするソースおよびドレイン電極と、前記活性層の上
部また下部にゲート絶縁膜を介して配設されたゲート電
極とを有する薄膜トランジスタにおいて、前記活性層と
前記ソースおよびドレイン電極とのコンタクト層としｎ
型のシリコン窒化膜を用いたことを特徴とする薄膜トラ
ンジスタ。(2) a substrate, an active layer formed in a predetermined pattern on the substrate and consisting of a multilayer film in which semiconductor films and insulating films are alternately laminated, and a source and a drain that are in contact with opposing end surfaces of this active layer. In a thin film transistor having an electrode and a gate electrode disposed above or below the active layer via a gate insulating film, a contact layer between the active layer and the source and drain electrodes may be used.
A thin film transistor characterized by using a type of silicon nitride film.
された、シリコン膜とシリコン窒化膜が交互に積層され
た多層膜からなる活性層と、この活性層の相対向する端
面にコンタクトするソースおよびドレイン電極と、前記
活性層の上部または下部にゲート絶縁膜を介して配設さ
れたゲート電極とを有する薄膜トランジスタの製造方法
において、前記多層膜の前記ソースおよびドレイン電極
がコンタクトする部分に、ｎ型不純物をドーピングしな
がらレーザ・アニールを施してｎ型シリコン窒化膜から
なるコンタクト層を形成する工程を有することを特徴と
する薄膜トランジスタの製造方法。(3) a substrate, an active layer formed on the substrate in a predetermined pattern and consisting of a multilayer film in which silicon films and silicon nitride films are alternately laminated; a source in contact with opposing end surfaces of the active layer; In the method for manufacturing a thin film transistor having a drain electrode and a gate electrode disposed above or below the active layer via a gate insulating film, an n-type A method for manufacturing a thin film transistor, comprising the step of forming a contact layer made of an n-type silicon nitride film by performing laser annealing while doping with impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25044889A JPH03114234A (en) | 1989-09-28 | 1989-09-28 | Thin film transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25044889A JPH03114234A (en) | 1989-09-28 | 1989-09-28 | Thin film transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03114234A true JPH03114234A (en) | 1991-05-15 |
Family
ID=17208028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25044889A Pending JPH03114234A (en) | 1989-09-28 | 1989-09-28 | Thin film transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03114234A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5825050A (en) * | 1995-05-25 | 1998-10-20 | Nec Corporation | Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof |
| US5915173A (en) * | 1994-07-13 | 1999-06-22 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor and method for fabricating the same |
| US7858982B2 (en) | 2004-09-24 | 2010-12-28 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
| US7942111B2 (en) | 1997-06-16 | 2011-05-17 | Robert Bosch Gmbh | Method and device for vacuum-coating a substrate |
-
1989
- 1989-09-28 JP JP25044889A patent/JPH03114234A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5915173A (en) * | 1994-07-13 | 1999-06-22 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor and method for fabricating the same |
| US5825050A (en) * | 1995-05-25 | 1998-10-20 | Nec Corporation | Thin film transistor having tapered active layer formed by controlling defect density and process of fabrication thereof |
| US7942111B2 (en) | 1997-06-16 | 2011-05-17 | Robert Bosch Gmbh | Method and device for vacuum-coating a substrate |
| US7858982B2 (en) | 2004-09-24 | 2010-12-28 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
| US8252639B2 (en) | 2004-09-24 | 2012-08-28 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
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