JPH08236775A - Film transistor, and its manufacture - Google Patents

Abstract

PURPOSE: To prevent the pollution at the interface of a channel by bringing the active layers consisting of amorphous semiconductors provided at source and drain electrodes into direct contact with an insulating film in a recess. CONSTITUTION: A gate insulating film 2 consisting of a stacked insulating film of an SiOx film and an SiNx film is made all over the surface, using plasma CVD method. Next, after successive formation, they are etched to form a picture element electrode 4, ITO/Cr stacked films 5 and 6, and an n<+> -type amorphous silicon film 7. Next, removing the surface of the gate insulating film 2 on the gate electrode 1 of a TFT part will form a recess in the surface. Then, an amorphous film to serve as an active layer 8 is made all over the surface, and this amorphous silicon film, the ITO/Cr stacked plates 5 and 6, and the n<+> -type amorphous silicon film 7 are patterned to form an active layer 7, source and drain electrodes 5 and 6, and an ohmic contact layer 7. At this time, since there is no pollution on the surface of the gate insulating film 2, favorable channel screen can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) using a non-single crystal semiconductor for an active layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art A display device using electroluminescence, a light emitting diode, plasma, liquid crystal, etc. can display a thin display unit, and therefore can be used as a terminal display for televisions, measuring instruments, office equipment, computers and the like. It is expected to develop as an application to equipment.

Among these display devices, an active matrix type liquid crystal display device (hereinafter, simply referred to as a liquid crystal display device) using a thin film transistor as a switching element has recently attracted attention.

In such a liquid crystal display device, generally, when the screen becomes a large screen with a diagonal of 10 inches or more, a TFT array substrate is formed using a glass substrate to suppress an increase in production cost. Therefore, an amorphous silicon film that can be formed at a low temperature is used as the active layer of the thin film transistor.

FIG. 8 is a plan view of a TFT array substrate of a conventional active matrix type liquid crystal display using an amorphous silicon film as an active layer. In addition, FIG.
FIG. 9 is a cross-sectional view taken along the line AA ′ of the TFT array substrate of FIG. 8. In the figure, the left side shows the TFT section and the right side shows the gate electrode pad section.

In the figure, 101 indicates a gate electrode made of a refractory metal such as Cr or Mo-Ta alloy provided on a translucent insulating substrate (not shown) such as a glass substrate. 101 is covered with a gate insulating film 102 made of an insulator such as SiN _x and SiO _x .

An active layer 103 made of amorphous silicon is formed on the gate insulating film 102 in the region where the gate electrode 101 is formed. The active layer 103 is n.
Source / drain electrodes 105, 10 via ohmic contact layer 104 made of ⁺ -type amorphous silicon
I am in contact with 6. Here, the term “source / drain electrode (main electrode)” is used because the main electrode can be the source electrode and the drain electrode depending on the usage state.

One source / drain electrode 105 is connected to the signal wiring 107, and the other source / drain electrode 10 is connected.
6 is connected to the pixel electrode 108. Further, a passivation film 109 made of an insulating material such as SiN _x is formed on the TFT portion in order to improve durability. In FIG. 8, 110 is a through hole and 111 is an auxiliary capacitance electrode.

However, the conventional TFT array substrate thus constructed has the following problems. That is, when etching the n ⁺ -type amorphous silicon film to be the ohmic contact layer 104, the active layer 10
Since 3 (amorphous silicon film) is thinned by etching, it is necessary to form the active layer 103 in advance to a large thickness, generally about 200 to 300 nm. This causes a problem that the formation time of the active layer 103 becomes long and the productivity is lowered. In addition, there arises a problem that management of the etching process becomes complicated.

As a TFT array substrate capable of solving such a problem, one using a thin film transistor having a structure in which a channel protective film 112 is provided on an active layer 103 as shown in FIG. 10 has been proposed.

With such a TFT array substrate, the active layer 103 can be thinned to a thickness of about 50 to 20 nm. However, in the step of forming an insulating film to be the channel protective film 112, for example, a SiN _x film having a thickness of about 200 nm,
Furthermore, a new step of patterning the insulating film is required, which causes a problem of low productivity.

As a TFT array substrate which does not require a channel protective film, a structure obtained by forming an active layer 103 after forming an ohmic contact layer 104 is proposed as shown in FIG.

With such a TFT array substrate, the active layer 103 is not etched when etching the n ⁺ type amorphous silicon film to be the ohmic contact layer 104. Therefore, the active layer 10
Since it is not necessary to form 3 to be thick or to form a channel protective film, it is possible to prevent a decrease in productivity.

However, this type of TFT array substrate has the following problems. That is, the etchant used for forming the source / drain electrodes 105 and 106 and the etching residue generated during the formation of the source / drain electrodes 105 and 106 may be the gate insulating film 102 and the active layer 10.
3 remains on the interface with 3 (channel interface), and there is a problem that the TFT characteristics and durability deteriorate.

For example, the source / drain electrodes 105, 1
When Mo was used for 06, elements such as Mo were detected from the channel interface. Moreover, when ITO (indium tin oxide) was used, elements such as In were detected from the channel interface.

Further, the source / drain electrodes 105, 1
When forming 06, there is a problem that mobile ions such as Na and K from the photoresist and the like are mixed into the channel interface and the threshold voltage fluctuates. Such a problem of threshold voltage fluctuation becomes remarkable especially in the case of long-time operation.

[0017]

As described above, the conventional TF capable of preventing a decrease in productivity without using a channel protective film.
The T-array substrate has a problem that the channel interface is contaminated when the source / drain electrodes are formed and the TFT characteristics and the like are deteriorated.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a thin film transistor having a structure capable of preventing contamination of a channel interface and a method of manufacturing the thin film transistor.

[0019]

In order to achieve the above object, a thin film transistor according to the present invention is formed with an insulating film having a recess formed on the surface thereof and below the insulating film so as to face the recess. A pair of source / drain electrodes formed on the insulating film other than the recess so as to face the gate electrode via the gate electrode, and the insulation of the recess provided on the source / drain electrode. And an active layer made of an amorphous semiconductor that is in direct contact with the film.

The method of manufacturing a thin film transistor according to the present invention comprises the step of forming an insulating film covering the gate electrode,
Forming a conductive film on the gate electrode and then etching the conductive film to form a pair of source / drain electrodes facing each other through the gate electrode; and the gate exposed during the etching. After removing the surface of the insulating film on the electrode and forming the amorphous semiconductor film on the entire surface,
And a step of forming an active layer by etching the amorphous semiconductor film.

[0021]

Since the thin film transistor according to the present invention has a structure in which the gate electrode is present under the insulating film having the concave portion formed on the surface, the channel interface is contaminated by the method of manufacturing the thin film transistor according to the present invention. A thin film transistor can be manufactured without inviting.

That is, according to the method of manufacturing a thin film transistor according to the present invention, the active layer is formed after the surface of the insulating film is removed. Therefore, when the insulating film is removed, it is present in the insulating film. The pollution is also removed at the same time. Therefore, the active layer comes into contact with the insulating film whose surface is clean, so that the contamination of the channel interface can be prevented.

[0023]

Embodiments will be described below with reference to the drawings. (First Embodiment) FIGS. 1A to 1D are process sectional views showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention.
In the figure, the left side shows the TFT section and the right side shows the gate electrode pad section.

First, as shown in FIG. 1A, a conductive film made of a refractory metal such as Cr or Mo-Ta alloy, which will be the gate electrode 1, is formed on a translucent insulating substrate (not shown) such as a glass substrate. After forming, the conductive film is patterned to form the gate electrode 1.

Next, as shown in FIG. 1 (b), Si is formed on the entire surface.
A gate insulating film 2 made of a laminated insulating film of an O _x film (upper insulating film) and a SiN _x film (lower insulating film) is formed by using a plasma CVD method.

Next, as shown in FIG. 3B, a conductive film to be the pixel electrode 4 and IT to be source / drain electrodes are formed on the entire surface.
ITO / Cr laminated films 5 and 6 of O film and Cr film, n ⁺ type amorphous silicon film 7 to be an ohmic contact layer
After sequentially forming, these are continuously etched,
The pixel electrode 4 having a predetermined shape is formed, and the ITO / C
r laminated film 5, 6 and n ⁺ type amorphous silicon film 7
Is processed into a predetermined shape.

At this stage, the source / drain electrodes and the ohmic contact layer having the predetermined shapes have not been formed yet. Further, in the figure, although 3 is the same conductive film as the pixel electrode 4, it is not used as a pixel electrode.

In the above etching, by etching so that the angle θ of the etching end face becomes a taper of 50 degrees or less, it is possible to effectively prevent the film formed in the subsequent step from being cut off.

Next, as shown in FIG. 3C, the surface of the gate insulating film 2 on the gate electrode 1 in the TFT portion is removed. As a result, a recess is formed on the surface of the gate insulating film 2.
When the gate insulating film 2 is the SiN _x film, for example, by an etchant such as hydrofluoric acid or buffered hydrofluoric acid, SiN _x
The surface of the film is removed by etching by about 10 nm.

By such etching removal, a conductive film to be the pixel electrode 4 and ITO to be the source / drain electrodes are formed.
Contamination formed on the surface of the gate insulating film 2 (for example, etching residue) when the ITO / Cr laminated films 5 and 6 of the film and the Cr film and the n ⁺ type amorphous silicon film 7 to be the ohmic contact layer are etched. And damage can be removed.

Here, when the amount of the gate insulating film 2 removed is large, the aspect ratio of the concave portion formed on the surface of the gate insulating film 2 becomes large, and the active layer 8 formed in a later step causes step breakage in the concave portion. Alternatively, a pinhole-like defect occurs in the recessed gate insulating film 2.

On the contrary, if the removal amount is small, contamination and damage remain. Especially in the case of a large area, if the removal amount is small, it becomes difficult to completely remove contamination and damage. According to the research conducted by the present inventor, it was found that the removal amount is preferably about 5 to 50 nm.

Next, as shown in FIG. 1D, after forming an amorphous silicon film (amorphous semiconductor film) having a thickness of about 50 nm to be the active layer 8 on the entire surface, this amorphous silicon film, ITO / Cr By patterning the laminated films 5 and 6 and the n ⁺ type amorphous silicon film 7, an active layer 7 having a predetermined pattern, source / drain electrodes (signal wiring) 5,
The source / drain electrode 6 and the ohmic contact layer 7 are formed. Here, the source / drain electrodes 5 are integral with the signal wiring.

At this time, since the surface of the gate insulating film 2 is not contaminated or damaged, the interface (channel interface) between the gate insulating film 2 and the active layer 8 becomes good. Therefore, deterioration of TFT characteristics and durability can be prevented.

Finally, in order to improve reliability and characteristics, as shown in FIG. 1D, after depositing a SiN _x film on the entire surface, the SiN _x film is patterned to form a TFT on the TFT portion. The protective film 9 is formed. At this time, the gate insulating film 2 in the gate electrode pad portion is also patterned at the same time to form a gate electrode take-out port. (Second Embodiment) FIGS. 2A to 2D are process sectional views showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention.
In the figure, the left side shows the TFT section and the right side shows the gate electrode pad section.

First, as shown in FIG. 2A, a conductive film made of a refractory metal such as Cr or Mo-Ta alloy which will be the gate electrode 21 is formed on a translucent insulating substrate (not shown) such as a glass substrate. After forming, the conductive film is patterned to form the gate electrode 21.

Next, as shown in FIG. 2 (b), Si is formed on the entire surface.
A gate insulating film 22 made of a laminated insulating film of an O _x film (lower insulating film) and a SiN _y film (upper insulating film) is formed by plasma CVD.
It is formed using the method. The thickness of the SiN _y film is 10 nm
The degree.

Next, as shown in FIG. 3B, a SiN _z film 23 having an etching rate faster than that of the SiN _y film is formed on the gate insulating film 22. The thickness of the SiN _z film 23 is set to a level such that the underlying SiN _y film is not contaminated or damaged during etching in a post process, for example, about 10 nm. The thickness of the SiN _y film is preferably in the range of 5 to 20 nm.

The etching rate ratio (SiN _z film 2
The etching rate of 3 / the etching rate of the SiN _y film) is, for example, 10 or more when dilute hydrofluoric acid or buffered hydrofluoric acid is used as an etchant. The etching rate ratio is preferably 5 or more.

Next, as shown in FIG. 3B, a conductive film to be the pixel electrode 25 and I to be the source / drain electrodes are formed on the entire surface.
After the ITO / Cr laminated films 26 and 27 of the TO film and the Cr film and the n ⁺ type amorphous silicon film 28 to be the ohmic contact layer are sequentially formed, these are continuously etched to form the pixel electrode 25 having a predetermined shape. At the same time, the ITO / Cr laminated film 26 and the n ⁺ type amorphous silicon film 28 are processed into a predetermined shape. In the figure,
24 is the same conductive film as the pixel electrode 25, but is not used as a pixel electrode.

At this time, similarly to the first embodiment, it is preferable to prevent the film formed in a later step from being disconnected by etching so that the angle of the etching end face becomes a taper of 50 degrees or less.

Next, as shown in FIG. 2C, the SiN _z film 23 on the gate electrode 21 in the TFT portion is removed by using an etchant such as dilute hydrofluoric acid or buffered hydrofluoric acid. As a result, the gate insulating film 22 without contamination or damage appears on the surface.

At this time, since the etching rate of the SiN _y film, which is the upper insulating film forming the underlying gate insulating film 22, is sufficiently slower than that of the SiN _z film 23, the SiN _z on the gate electrode 21 is well controlled. The film 23 can be selectively removed completely.

By removing the SiN _z film 23 as described above,
The conductive film to be the pixel electrode 25, the ITO / Cr laminated films 26 and 27 to be the source / drain electrodes, and the n ⁺ -type amorphous silicon film 28 to be the ohmic contact layer were formed on the SiN _z film 23 formed by etching. Removes pollution and damage.

Next, as shown in FIG. 2D, after forming an amorphous silicon film having a thickness of about 50 nm to be the active layer 29 on the entire surface, this amorphous silicon film and ITO are formed.
The / Cr laminated films 26, 27 and the n ⁺ type amorphous silicon film 28 are patterned to form the active layer 29, the source / drain electrodes 26, 27 and the ohmic contact layer 28 having a predetermined pattern. Here, the source / drain electrodes 5 are integral with the signal wiring.

At this time, since the surface of the gate insulating film 22 is not damaged, the interface (channel interface) between the gate insulating film 22 and the active layer 29 becomes good. Therefore, deterioration of TFT characteristics and durability can be prevented.

Finally, in order to improve reliability and characteristics, as shown in FIG. 2E, after depositing a SiN _x film on the entire surface, the SiN _x film is patterned to form a TFT on the TFT portion. The protective film 30 is formed. At this time, the gate insulating film 22 of the gate electrode pad portion is also patterned at the same time,
An extraction port for the gate electrode 31 is formed.

In the case of this embodiment, since the gate insulating film 22 is not etched at all in the step of FIG. 2B, unlike the first embodiment, the gate insulating film 22 is basically free from pinhole-like defects. Does not occur.

Further, in the present embodiment, the difference in etching rate ratio is used to make SiN _{z that} is contaminated or damaged.
Since the film 23 is selectively removed, it is extremely easy to control the depth of the recess formed on the surface of the laminated insulating film composed of the gate insulating film 22 and the SiN _z film 23 on the gate electrode 21 of the TFT part. .

Therefore, according to this embodiment, it is possible to more effectively prevent the step breakage of the active layer 29 as compared with the first embodiment. Furthermore, for the same reason, in the case of the present embodiment, even if the screen is large, the SiN _z film 23 in which damage or the like has occurred can be removed more reliably than in the first embodiment. (Third Embodiment) FIGS. 3 and 4 are sectional views showing steps in a method of manufacturing a thin film transistor according to a third embodiment of the present invention. In the figure, the left side shows the TFT section and the right side shows the gate electrode pad section.

First, as shown in FIG. 3A, a conductive film made of a refractory metal such as Cr or Mo-Ta alloy, which will be the gate electrode 31, is formed on a transparent insulating substrate (not shown) such as a glass substrate. After forming, the conductive film is patterned to form the gate electrode 31.

Next, as shown in FIG. 3 (b), Si is formed on the entire surface.
A gate insulating film 32 made of a laminated insulating film of an O _x film (lower insulating film) and a SiN _y film (upper insulating film) is formed by plasma CVD.
It is formed using the method. The thickness of the SiN _y film is 10 nm
The degree.

Next, as shown in FIG. 9B, after forming a SiN _z film 33 having a thickness of about 10 nm, which has a faster etching rate than the SiN _y film on the gate insulating film 32, the gate of the gate electrode pad portion is formed. Gate insulating film 32 on electrode 31
Are removed by etching to form an outlet for the gate electrode 31. At this time, due to the difference in etching rate between the SiN _y film and the SiN _z film 33, a tapered take-out port can be easily formed.

The etching rate ratio (SiN _z film 3
The etching rate of 3 / the etching rate of the SiN _y film) is, for example, 10 or more when dilute hydrofluoric acid or buffered hydrofluoric acid is used as an etchant.

Next, as shown in FIG. 3C, a conductive film to be the pixel electrode 35 and I to be source / drain electrodes are formed on the entire surface.
After the ITO / Cr laminated films 36 and 37 of the TO film and the Cr film and the n ⁺ type amorphous silicon film 38 to be the ohmic contact layer are sequentially formed, these are continuously etched to form the pixel electrode 35 having a predetermined shape. While being formed, the ITO / Cr laminated films 36 and 37 and the n ⁺ type amorphous silicon film 38 are processed into a predetermined shape. In addition,
In the figure, 34 is the same conductive film as the pixel electrode 35, but it is not used as a pixel electrode.

Next, as shown in FIG. 4A, the SiN _z film 33 on the gate electrode 31 in the TFT section is removed by using an etchant such as dilute hydrofluoric acid or buffered hydrofluoric acid. As a result, the gate insulating film 32 without contamination or damage appears on the surface.

At this time, since the etching rate of the SiN _y film, which is the upper insulating film that constitutes the underlying gate insulating film 32, is sufficiently slower than that of the SiN _z film 33, the SiN _z on the gate electrode 31 is well controlled. The film 33 can be selectively removed completely.

By removing the SiN _z film 33 as described above,
The conductive film to be the pixel electrode 35, the ITO / Cr laminated films 36 and 37 to be the source / drain electrodes, and the n ⁺ -type amorphous silicon film 38 to be the ohmic contact layer were formed on the SiN _z film 33 formed by etching. Removes pollution and damage.

Next, as shown in FIG. 4B, after forming an amorphous silicon film having a thickness of about 50 nm to be the active layer 39 on the entire surface, this amorphous silicon film and ITO are formed.
The / Cr laminated films 36, 37 and the n ⁺ type amorphous silicon film 38 are patterned to form an active layer 3 having a predetermined pattern.
9, source / drain electrodes 36 and 37, and ohmic contact layer 38 are formed. Here, the source / drain electrodes 36 are integrated with the signal wiring.

At this time, since the surface of the gate insulating film 32 is not contaminated or damaged, the interface (channel interface) between the gate insulating film 32 and the active layer 39 becomes good. Therefore, deterioration of TFT characteristics and durability can be prevented.

Finally, in order to improve reliability and characteristics, as shown in FIG. 4C, after depositing a SiN _x film on the entire surface, the SiN _x film is patterned to form a TFT on the TFT portion. The protective film 40 is formed.

In this embodiment, the same effect as the second embodiment can be obtained, and the following effects can also be obtained. In this embodiment, the ITO / C serving as the source / drain electrodes 36 and 37 is formed.
The r laminated film and the conductive film to be the pixel electrode 35 are the gate insulating film 3
Before forming on the gate electrode 2, the gate electrode take-out port is formed.

Therefore, during the manufacturing process, the gate electrode 3
1 and the signal line 34, the gate electrode 31 and the pixel electrode 3
Dielectric breakdown due to static electricity generated between
It is possible to prevent fluctuations in T characteristics.

Further, since the gate electrode take-out port is formed by etching using the resist pattern, a contaminated portion is formed by impurities derived from the resist pattern and the like. In the case of this embodiment, the contaminated portion is SiN _z. Since the film 33 is removed in the removal step, the adverse effect of the contaminated portion can be sufficiently reduced. (Fourth Embodiment) FIGS. 5A to 5C are process sectional views showing a method of manufacturing a thin film transistor according to a fourth embodiment of the present invention.
In the figure, the left side shows the TFT section and the right side shows the gate electrode pad section.

First, as shown in FIG. 5A, a conductive film made of a refractory metal such as Cr or Mo-Ta alloy, which will be the gate electrode 41, is formed on a translucent insulating substrate (not shown) such as a glass substrate. After forming, the conductive film is patterned to form the gate electrode 41.

Next, as shown in FIG. 5 (b), Si is formed on the entire surface.
A gate insulating film 42 made of a laminated insulating film of an O _x film (lower insulating film) and a SiN _y film (upper insulating film) is formed by plasma CVD.
It is formed using the method. The thickness of the SiN _y film is 10 nm
The degree.

Next, as shown in FIG. 9B, after forming a SiN _z film 43 having a thickness of about 10 nm which has a faster etching rate than the SiN _y film on the gate insulating film 42, the gate of the gate electrode pad portion is formed. Gate insulating film 42 on electrode 41
Are removed by etching to form an outlet for the gate electrode 41. At this time, due to the difference in etching rate between the SiN _y film and the SiN _z film 43, a tapered take-out port can be easily formed.

The etching rate ratio (SiN _z film 4
The etching rate of 3 / the etching rate of the SiN _y film) is, for example, 10 or more when dilute hydrofluoric acid or buffered hydrofluoric acid is used as an etchant.

Next, as shown in FIG. 5C, a conductive film which becomes the pixel electrode 45 and I which becomes the source / drain electrodes are formed on the entire surface.
After the ITO / Cr laminated films 46 and 47 of the TO film and the Cr film and the n ⁺ type amorphous silicon film 48 to be the ohmic contact layer are sequentially formed, these are continuously etched to form the pixel electrode 45 having a predetermined shape. At the same time as the formation, the ITO / Cr laminated films 46 and 47 and the n ⁺ type amorphous silicon film 48 are processed into a predetermined shape. In addition,
In the figure, 44 is the same conductive film as the pixel electrode 45, but is not used as a pixel electrode.

Next, as shown in FIG. 5D, the SiN _z film 43 on the gate electrode 41 in the TFT section is removed by using an etchant such as dilute hydrofluoric acid or buffered hydrofluoric acid. As a result, the gate insulating film 42 without contamination or damage appears on the surface.

At this time, since the etching rate of the SiN _y film, which is the upper insulating film forming the underlying gate insulating film 42, is sufficiently slower than that of the SiN _z film 43, the SiN _z on the gate electrode 41 is well controlled. The film 43 can be selectively removed completely.

By removing the SiN _z film 43 as described above,
Contamination formed on the SiN _z film 43 generated when the conductive film to be the pixel electrode 45, the ITO / Cr laminated film 47 to be the source / drain electrodes, and the n ⁺ type amorphous silicon film 48 to be the ohmic contact layer were etched. And damage can be removed.

Finally, as shown in FIG. 5E, an amorphous silicon film having a thickness of about 50 nm to be the active layer 49 and a Si film having a thickness of 200 nm to be the TFT protective film 50 are formed on the entire surface.
After sequentially forming an N _x film, the amorphous silicon film, the SiN _x film, the ITO / Cr laminated film and n
By patterning the ⁺ type amorphous silicon film at the same time, the active layer 49, the source / drain electrodes 46 and 47, the ohmic contact layer 48, and the TFT protective film 50 having a predetermined pattern are formed. Here, the source / drain electrodes 46 are integral with the signal wiring.

At this time, since the surface of the gate insulating film 42 is not damaged, the interface (channel interface) between the gate insulating film 42 and the active layer 49 becomes good. Therefore, deterioration of TFT characteristics and durability can be prevented.

In this embodiment, the same effect as that of the third embodiment can be obtained, and further the following effect can be obtained. That is,
In this embodiment, since the amorphous silicon film to be the active layer 49 and the SiN _x film to be the TFT protective film 50 are simultaneously patterned, the amorphous silicon film to be the active layer 39 and the SiN _x film to be the TFT protective film 50 are formed. The number of steps is reduced and the manufacturing process can be simplified as compared with the third embodiment in which patterning is performed in different steps. (Fifth Embodiment) FIGS. 6 and 7 are process cross-sectional views showing a method of manufacturing a thin film transistor according to a fifth embodiment of the present invention. In the figure, the left side shows the TFT section and the right side shows the gate electrode pad section.

First, as shown in FIG. 6A, a conductive film made of a refractory metal such as Cr or Mo-Ta alloy, which will be the gate electrode 51, is formed on a transparent insulating substrate (not shown) such as a glass substrate. After forming, the conductive film is patterned to form the gate electrode 51.

Next, as shown in FIG. 6 (b), Si is formed on the entire surface.
A gate insulating film 52 made of a laminated insulating film of an O _x film (lower insulating film) and a SiN _y film (upper insulating film) is formed by plasma CVD.
It is formed using the method. The thickness of the SiN _y film is 10 nm
The degree.

Next, as shown in FIG. 9B, after forming a SiN _z film 53 having a thickness of about 10 nm, which has a faster etching rate than the SiN _y film, on the gate insulating film 52, the gate of the gate electrode pad portion is formed. Gate insulating film 52 on electrode 51
Are removed by etching to form an outlet for the gate electrode 51. At this time, due to the difference in etching rate between the SiN _y film and the SiN _z film 53, a tapered take-out port can be easily formed.

The etching rate ratio (SiN _z film 5
The etching rate of 3 / the etching rate of the SiN _y film) is, for example, 10 or more when dilute hydrofluoric acid or buffered hydrofluoric acid is used as an etchant.

Next, as shown in FIG. 6C, an ITO film to be the source / drain electrodes and the pixel electrode 55 is formed on the entire surface,
An n ⁺ type amorphous silicon film to be the ohmic contact layer 58 is sequentially formed.

Then, an n ⁺ type amorphous silicon film 58 is formed.
After coating a negative resist or an image reverse resist (not shown) on the top, the resist is exposed from the back surface to form a resist pattern (not shown) in self-alignment with the gate electrode 51.

Next, by using the resist pattern as a mask, the ITO film and the n ⁺ -type amorphous silicon film are continuously etched to form a pattern shown in FIG.
As shown in FIG. 3, the pixel electrode 55 integrated with the source / drain electrode having a predetermined shape is formed, and the n ⁺ type amorphous silicon film 58 is processed into a predetermined shape. At this time, the SiN _z film 53 of the gate electrode 51 in the TFT section is damaged or contaminated. In the figure, 54
Is the same conductive film as the pixel electrode 55, but is not used as the pixel electrode.

Next, as shown in FIG. 7A, after forming a conductive film to be the source / drain electrodes 56 on the entire surface, the conductive film is patterned to form the source / drain electrodes 56.
To form. At this time, S of the gate electrode 51 of the TFT section
Contamination or damage occurs in the iN _z film 53. The source / drain electrodes 56 are integrated with the signal wiring.

Next, as shown in FIG. 7B, the SiN _z film 53 on the gate electrode 51 in the TFT section is removed using an etchant such as dilute hydrofluoric acid or buffered hydrofluoric acid. As a result, the gate insulating film 52 without contamination or damage appears on the surface.

At this time, since the etching rate of the SiN _y film, which is the upper insulating film forming the underlying gate insulating film 52, is sufficiently slower than that of the SiN _z film 53, the SiN _z on the gate electrode 51 is well controlled. The film 53 can be selectively removed completely.

Finally, as shown in FIG. 7C, an amorphous silicon film having a thickness of about 50 nm to be the active layer 59 and a Si film having a thickness of 200 nm to be the TFT protective film 60 are formed on the entire surface.
After sequentially forming an N _x film, the amorphous silicon film, the SiN _x film, the ITO / Cr laminated film and n
By patterning the ⁺ type amorphous silicon film at the same time, an active layer 59, an ohmic contact layer 58 and a TFT protective film 60 having a predetermined pattern are formed.

At this time, since the surface of the gate insulating film 52 is not damaged, the interface (channel interface) between the gate insulating film 52 and the active layer 59 becomes good. Therefore, deterioration of TFT characteristics and durability can be prevented.

In this embodiment, the same effect as that of the fourth embodiment can be obtained, and the following effects can also be obtained. That is,
In this embodiment, since the resist patterns used for etching the ITO film and the n ⁺ type amorphous silicon film are formed in a self-aligned manner by backside exposure, misalignment between layers (films) can be reduced.

The present invention is not limited to the above embodiment. For example, in the above embodiment, as the insulating film to be removed in a subsequent process (channel interface protective layer), was used advantageously the SiN _x film to prevent contamination by mobile ions such as Na ions, SiO _x film An insulating film such as the above may be used.

The use of the SiO _x film has the following advantages. That is, when the ITO film is patterned, if the base is a SiN _x film, the film quality of the ITO film is SiN _x.
The patterning accuracy may not be good because it changes on the _x film and sand etching occurs, but such an inconvenience does not occur in the SiO _x film.

Further, the etching of the channel interface protective film is generally performed by using an etchant such as dilute hydrofluoric acid as in the above embodiment, but the point is that the channel interface protective film can be etched. .

In the case where the amorphous silicon film is formed by the plasma CDV apparatus, the channel interface protection film is formed before the amorphous silicon film by the plasma process using H ₂ in the vacuum chamber of the plasma CVD apparatus. The surface may be removed by etching.

In this case, the TFT characteristics can be improved by nitriding the surface of the remaining channel protection film by plasma treatment using NH ₃ subsequent to the above etching removal.

Note that etching removal may be performed by plasma treatment using NH ₃ instead of H ₂ . Further, in the above embodiment, Cr and Mo-Ta are given as examples of the high melting point metal material which is the gate electrode material, but other high melting point metal materials (for example, Ti) may be used. Also,
Polycrystalline silicon may be used as the gate electrode material. In this case, in order to reduce the resistance, it is preferable to use impurity-doped polycrystalline silicon. Furthermore, a laminated film of a refractory metal film and a polycrystalline silicon film may be used as the gate electrode. In addition, various modifications can be made without departing from the scope of the present invention.

[0095]

As described above in detail, according to the present invention, by adopting the structure in which the gate electrode is present under the insulating film having the concave portion formed on the surface thereof, the TFT having no channel interface contamination can be obtained. It will be realized.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing the manufacturing method of the first half of the thin film transistor according to the third embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing the manufacturing method of the latter half of the thin film transistor according to the third embodiment of the present invention.

FIG. 5 is a process sectional view showing a method of manufacturing a thin film transistor according to a fourth embodiment of the present invention.

FIG. 6 is a process sectional view showing the manufacturing method of the first half of the thin film transistor according to the fifth embodiment of the present invention.

FIG. 7 is a process cross-sectional view showing the manufacturing method of the latter half of the thin film transistor according to the fifth embodiment of the present invention.

FIG. 8 is a plan view of a TFT array substrate of a conventional active matrix type liquid crystal display.

9 is a cross-sectional view taken along the line AA ′ of the TFT array substrate of FIG.

FIG. 10 is a sectional view of another conventional TFT array substrate.

FIG. 11 is a sectional view of still another conventional TFT array substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate electrode 2 ... Gate insulating film 3 ... Pixel electrode 5 ... Source / drain electrode (signal wiring, ITO / Cr laminated film) 6 ... Source / drain electrode (ITO / Cr laminated film) 7 ... Ohmic contact layer (n ⁺ Type amorphous silicon film) 8 ... Active layer 9 ... TFT protective film 21 ... Gate electrode 22 ... Gate insulating film 23 ... SiN _z film 25 ... Pixel electrode 26 ... Source / drain electrodes (signal wiring, ITO / Cr)
Laminated film) 27 ... Source / drain electrodes (ITO / Cr laminated film) 28 ... Ohmic contact layer (n ⁺ type amorphous silicon film) 29 ... Active layer 30 ... TFT protective film 31 ... Gate electrode 32 ... Gate insulating film 33 ... SiN _z film 35 ... Pixel electrode 36 ... Source / drain electrodes (signal wiring, ITO / Cr
Laminated film 37 ... Source / drain electrode (ITO / Cr laminated film) 38 ... Ohmic contact layer (n ⁺ type amorphous silicon film) 39 ... Active layer 40 ... TFT protective film 41 ... Gate electrode 42 ... Gate insulating film 43 ... SiN _z film 45 ... Pixel electrode 46 ... Source / drain electrode (signal wiring, ITO / Cr
Laminated film) 47 ... Source / drain electrode (ITO / Cr laminated film) 48 ... Ohmic contact layer (n ⁺ type amorphous silicon film) 49 ... Active layer 50 ... TFT protective film 51 ... Gate electrode 52 ... Gate insulating film 53 ... SiN _z film 55 ... Source / drain electrodes (pixel electrodes) 56 ... Source / drain electrodes (signal wiring, ITO / Cr)
Laminated film) 58 ... ohmic contact layer (n ⁺ type amorphous silicon film) 59 ... active layer 60 ... TFT protective film

Claims (2)

[Claims] 1. An insulating film having a recess formed on a surface thereof, a gate electrode formed below the insulating film so as to face the recess, and a portion other than the recess so as to face the gate electrode. A pair of source / drain electrodes formed on the insulating film, and an active layer made of an amorphous semiconductor provided on the source / drain electrodes and in direct contact with the insulating film in the recess. Is a thin film transistor. 2. A step of forming an insulating film covering a gate electrode, and a conductive film is formed on the gate electrode, the conductive film is etched, and a pair of source / opposite electrodes facing each other via the gate electrode. Forming a drain electrode; removing a surface of the insulating film on the gate electrode exposed during the etching; forming an amorphous semiconductor film on the entire surface; and then etching the amorphous semiconductor film. And a step of forming an active layer.