JP2004193248A - Image display device and its manufacturing method - Google Patents

Image display device and its manufacturing method Download PDF

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JP2004193248A
JP2004193248A JP2002357824A JP2002357824A JP2004193248A JP 2004193248 A JP2004193248 A JP 2004193248A JP 2002357824 A JP2002357824 A JP 2002357824A JP 2002357824 A JP2002357824 A JP 2002357824A JP 2004193248 A JP2004193248 A JP 2004193248A
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film
insulating film
gate
interlayer insulating
display device
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JP4984369B2 (en
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Yoshiaki Toyoda
善章 豊田
Takeshi Sato
健史 佐藤
Takeo Shiba
健夫 芝
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To lower the manufacturing cost of an image display device employing polysilicon TFTs and reduce the interlayer capacitance between the gate line and the signal line. <P>SOLUTION: The image display device having a plurality of thin film transistors on a substrate SUB is provided with a plurality of gate lines GO, a plurality of signal lines SDO intersected with the gate lines in the state of a matrix, a bottom gated thin film transistor, a channel region (a) having a lamination structure of a gate electrode G1/a gate insulating film GI/a polycrystalline silicon film PSI from the substrate side, and a source electrode and a drain electrode having the lamination structure of a gate insulating film GI/an interlayer insulating film INT/a non-single crystal silicon film HDA, a metal film SDI from the substrate side. A multi-crystal silicon film is formed so as to contact the gate insulating film, the interlayer insulating film and the non-single crystal silicon film. Further, the device has an insulating firm laminated with the gate insulating film GI and the interlayer insulating film INT at the intersecting part (b) between the signal line and the gate line. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、画像表示装置及びその製造方法に係り、特に低コストで製造するに好適な画像表示装置及びその製造方法に関する。
【０００２】
【従来の技術】
ポリシリコン薄膜トランジスタ（以下、ＴＦＴと略記する）は、アモルファスシリコンＴＦＴよりも移動度が２桁以上高く優れた性能を有する。この特長を活かした例として、例えば非特許文献１に記載されているアクティブマトリクス型液晶表示装置が挙げられる。この表示装置は、周辺駆動回路の一部をポリシリコンＴＦＴで構成することにより、画素部と周辺駆動回路との接続端子数が低減でき、高精細な画像表示ができる。
【０００３】
従来のポリシリコンＴＦＴの製造方法を製造工程図である図２〜図４に従って述べる。
【０００４】
先ず、図２に示すように、ガラス基板ＳＵＢ上にバッファ層として酸化シリコン膜Ｌ１を１００ｎｍ堆積し、さらにプラズマＣＶＤ法によりアモルファスシリコン層を５０ｎｍ堆積する。次にＸｅＣｌエキシマレーザを照射しアモルファスシリコン層を結晶化し、周知のホトエッチング工程により、島状のポリシリコン層ＰＳＩを得る。その後、プラズマＣＶＤ法によりゲート絶縁膜ＧＩを１００ｎｍ堆積し、さらにゲート電極Ｇ１を形成する。
【０００５】
次に、図３に示すように、ゲート電極Ｇ１をマスクとして、リンのイオン打ち込みによって低濃度ｎ型ポリシリコン層ＬＤＮを形成の後、不図示の低濃度ｎ型ポリシリコン層ＬＤＮ上部に設けられたレジストをマスクとして高濃度ｎ型ポリシリコン層ＨＤＮを形成する。
【０００６】
図４に示すように、全体を覆うように酸化シリコンからなる層間絶縁膜ＩＮＴを形成し、不純物活性化のため６００℃の炉アニールを５時間行う。さらに、層間絶縁膜ＩＮＴに設けたコンタクトスルーホールを介して、ソース／ドレイン電極ＳＤ１を形成する。
【０００７】
従来のポリシリコンＴＦＴは、低抵抗のソース／ドレイン領域を形成するためにイオン打ち込み及び不純物活性化の工程が必要であり、スループットを低下させていた。
【０００８】
これらの工程を省略する手段として、従来のアモルファスシリコンＴＦＴのように、シリコン層の上に、高濃度ｎ型アモルファスシリコン層とソース／ドレイン電極を積層する方法がある。この例を図５に示す。
【０００９】
図５に示すように、ゲート絶縁膜ＧＩ形成の後、アモルファスシリコン層ＡＳＩおよびチャネルエッチング防止膜Ｌ３を形成し、高濃度ｎ型アモルファスシリコン層ＨＤＡとソース／ドレイン電極ＳＤ１を積層することにより、イオン打ち込みおよび不純物活性化の工程を省くことができる。
【００１０】
しかし、この構造ではゲート線Ｇ０と信号線ＳＤ０との交差部分の容量が大きいため、画像信号の高速書き換えや、画面の大型化が困難となっていた。さらに、従来のアモルファスシリコンＴＦＴの構造をポリシリコンＴＦＴに適用した場合、ポリシリコンはアモルファスシリコンよりも移動度が２桁以上高いため、オフ電流が増加する問題がある。
【００１１】
上記の問題の中で、容量を減少させるためには、ゲート線Ｇ０と信号線ＳＤ０との間に絶縁膜を形成することが有効である。しかし、この方法では絶縁膜を形成するためのホトエッチング工程か追加されるためスループットが低下しコスト高となってしまう。
【００１２】
また、オフ電流を低下させるためには、特許文献１に記載のように多結晶半導体層と高濃度不純物層との間に、低濃度不純物層を形成する方法がある。しかしこの方法では、低濃度不純物層を形成するためのホトエッチング工程が追加されるためスループットが低下しコスト高となってしまう。
【００１３】
【非特許文献１】
ソサイアテイ フォア インフォメーション ディスプレイ インタナショナル シンポジウム ダイジエスト オブ テクニカル ペーパーズ １７２頁（Ｓｏｃｉｅｔｙ ｆｏｒ Ｉｎｆｏｒｍａｔｉｏｎ Ｄｉｓｐｌａｙ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｓｙｍｐｏｓｉｕｍ Ｄｉｇｅｓｔ ｏｆ Ｔｅｃｈｎｉｃａｌ Ｐａｐｅｒｓ ｐｐ．１７２）（１９９９）
【特許文献１】
特開平７−１３１０３０号公報
【００１４】
【発明が解決しようとする課題】
したがって、本発明の目的は、上記従来の問題点を解消することにあり、その第１の目的は、ゲート線と信号線との交差部における容量を低下させ、かつ製造コストの低い画像表示装置を提供することにある。
【００１５】
そして第２の目的は、オフ電流を低下させ、かつ製造コストの低い画像表示装置を提供することにある。
【００１６】
【課題を解決するための手段】
上記本発明の目的は、以下に発明の特徴点を記載した画像表示装置及びその製造方法により達成される。
【００１７】
すなわち、本発明の画像表示装置は、基板上に複数の薄膜トランジスタを有する画像表示装置であって、前記基板上に、複数のゲート線と、これらゲート線にマトリクス状に交差する複数の信号線とを有し、前記薄膜トランジスタはボトムゲート型であり、チャネル領域は基板側から、ゲート電極／ゲート絶縁膜／多結晶シリコン膜が順次積層された積層構造を有し、ソース電極及びドレイン電極部は基板側から、ゲート絶縁膜／層間絶縁膜／非単結晶シリコン膜／金属膜が順次積層された積層構造を有しており、前記多結晶シリコン膜は前記ゲート絶縁膜及び前記層間絶縁膜及び前記非単結晶シリコン膜にそれぞれ接して形成されており、前記信号線と前記ゲート線との交差部において、前記ゲート絶縁膜と前記層間絶縁膜との積層絶縁膜を有することを特徴とする。
【００１８】
また、本発明の画像表示装置の製造方法の特徴は、基板上にボトムゲート型薄膜トランジスタを形成する工程にあり、基板上に、ゲート電極を形成する工程と、前記ゲート電極上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に層間絶縁膜を形成する工程と、前記層間絶縁膜上に非単結晶シリコン膜を形成する工程と、前記非単結晶シリコン膜上に金属膜を形成する工程と、レジストをマスクにして前記金属膜を加工し、さらにサイドエッチングにより、レジストに対し前記金属膜を縮小加工し、ソース電極及びドレイン電極を形成する工程と、前記同レジストをマスクにして、前記非単結晶シリコン膜及び前記層間絶縁膜をエッチングする工程と、前記ゲート絶縁膜及び前記層間絶縁膜及び前記非単結晶シリコン膜に接して多結晶シリコン膜を形成する工程とを含むことを特徴とする。
【００１９】
本発明の画像表示装置は、ボトムゲート型ポリシリコン薄膜トランジスタ（ＴＦＴ）を用いることにより、イオン打ち込み及び不純物活性化の工程を省略でき、且つ前記金属膜と、前記非単結晶シリコン膜と、前記層間絶縁膜の加工を同一のレジストマスクを用いて行うためホトエッチング工程を追加することがなく画像表示装置の低コスト化が可能である。
【００２０】
本発明の画像表示装置は、ゲート電極と同層のゲート線と、ソース／ドレイン電極と同層の信号線との間に、ゲート絶縁膜と層間絶縁膜の積層絶縁膜が形成されているため、層間容量を低減でき、画像表示装置の大型化、画像信号の高速書き換えが可能である。
【００２１】
また、ゲート電極に電圧を印加した場合、層間絶縁膜側面部に接して形成された多結晶シリコン膜に誘起されるキャリア濃度は、ゲート絶縁膜に接して形成された多結晶シリコン膜に誘起されるキャリア濃度よりも低い。従って、本発明の薄膜トランジスタはオフセット構造を有しており、オフ電流の低減が可能である。
【００２２】
なお、ここで使用している非単結晶シリコン膜という用語は、単結晶シリコン膜ではないと言う意味であり、具体的にはアモルファスシリコン膜、もしくは多結晶シリコン膜、あるいはこれら両者を部分的に含む膜を意味している。
【００２３】
【発明の実施の形態】
本発明の代表的な実施の形態を以下に説明する。
（１）本発明の画像表示装置の基板に形成された代表的なボトムゲート型ポリシリコンＴＦＴの構造及びゲート線と信号線の交差部を図１の断面図に示す。この図は画像表示装置の製造工程の中で画素電極ＰＸ１を形成した後の状態を示している。なお、図１のａ部はＴＦＴ領域を、ｂ部はゲート線と信号線の交差部をそれぞれ示している。ガラス基板ＳＵＢ上にバッファ層Ｌ１として酸化シリコンが設けられ、この基板上にＴＦＴ及び画像表示装置として必要な駆動回路などが形成されている。
【００２４】
図１において、符号Ｇ１はゲート電極、ＧＩはゲート絶縁膜、ＩＮＴは層間絶縁膜、ＰＳＩはポリシリコン膜（多結晶シリコン膜）、ＨＤＡは高濃度ｎ型アモルファスシリコン層（非単結晶シリコン膜の一例）、ＳＤ１はソース／ドレイン電極（金属膜）、Ｌ２は保護絶縁膜、ＰＸ１は画素電極、Ｇ０はゲート線、ＳＤ０は信号線をそれぞれ示す。
（２）上記ＴＦＴの好ましい構成として、ソース／ドレイン電極ＳＤ１及び信号線ＳＤ０を形成する金属膜は、非単結晶シリコン膜に対し、自己整合的に縮小加工されていることである。
（３）上記ゲート電極上部の層間絶縁膜ＩＮＴは、テーパ状に加工されており、非単結晶シリコン膜と接する層間絶縁膜ＩＮＴの端部のゲート絶縁膜上の投影点と、ゲート絶縁膜ＧＩと接する層間絶縁膜ＩＮＴの端部との間隔をＴ１とし、前記層間絶縁膜ＩＮＴの膜厚をＴ２としたとき、これら両者の関係をＴ１＞Ｔ２としたことである。つまり、層間絶縁膜ＩＮＴの膜厚Ｔ２よりも間隔Ｔ１を長くする。これにより、チャネル領域に、レーザー結晶化工程を含む製造工程で多結晶シリコン膜を形成する際に良質なポリシリコンが得られる。
（４）また、上記（３）の場合とは逆に、これら両者の関係をＴ１≦Ｔ２としてもよい。これにより、オン電流が大きくとれる、オフセット長のバラツキを制御（小さく）できるなどの効果がある。
（５）上記ゲート絶縁膜ＧＩは、高誘電率膜と酸化シリコン膜との積層膜であることが好ましい。高誘電率膜としては、例えばＡｌ２Ｏ３、Ｙ２Ｏ３、Ｌａ２Ｏ３、Ｔａ２Ｏ５、ＺｒＯ２、ＬａＡｌＯ３、ＺｒＴｉＯ４、ＨｆＯ２、ＳｒＺｒＯ３、ＴｉＯ２、ＳｒＴｉＯ３、ＳｒＢｉ２Ｔａ２Ｏ９、（ＢａｘＳｒ１−ｘ）ＴｉＯ３、Ｐｂ（ＺｒｙＴｉ１−ｙ）Ｏ３等、周知の高誘電率材料が挙げられる。
（６）上記ゲート絶縁膜ＧＩはゲート電極Ｇ１の酸化膜と酸化シリコン膜との積層膜であることが好ましい。
（７）また、上記ゲート絶縁膜及び上記層間絶縁膜に接する多結晶シリコン膜の幅をＷ１とし、ゲート電極の幅をＷ２としたとき、これら両者の関係をＷ１＜Ｗ２とすることである。これにより、画像表示装置を液晶表示装置で構成したとき、バックライトによる光リーク電流の発生を抑制することができる。層間絶縁膜ＩＮＴに接する多結晶シリコンＰＳＩはオフセットの役割を果たすためオフ電流を低減することが可能である。
（８）本発明の好ましい画像表示装置は、一対の絶縁性基板と、これらに挟まれた液晶層を有する液晶表示装置であって、この液晶表示装置は複数の薄膜トランジスタを有しており、薄膜トランジスタはソース電極及びドレイン電極と、絶縁膜を介してソース電極及びドレイン電極上部に形成された画素電極を有しており、ソース電極及びドレイン電極と画素電極との間に電圧を印加することにより、基板に対し平行な横方向電界を発生させ、横方向電界により液晶の配向を制御することを特徴とする。
（９）基板上に薄膜トランジスタで構成された複数のＣＭＯＳを有する画像表示装置であって、前記薄膜トランジスタはボトムゲート型であり、チャネル領域は基板側から、ゲート電極／ゲート絶縁膜／多結晶シリコン膜が順次積層された積層構造を有し、ソース電極及びドレイン電極部は基板側から、ゲート絶縁膜／層間絶縁膜／非単結晶シリコン膜／金属膜が積層された積層構造を有しており、ｎ型薄膜トランジスタは、前記非単結晶シリコン膜がｎ型導電性を有し、前記多結晶シリコン膜はゲート絶縁膜及び層間絶縁膜及びｎ型非単結晶シリコン膜にそれぞれ接して形成されており、ｐ型薄膜トランジスタは、前記層間絶縁膜の側面部及び前記金属膜の側面部に接してｐ型非単結晶シリコン膜が形成されており、前記多結晶シリコン膜はゲート絶縁膜及び前記ｐ型非単結晶シリコン膜に接して形成されていることを特徴とする。
（１０）上記多結晶シリコン膜を形成する工程は、プラズマＣＶＤ法で成膜するアモルファスシリコン膜の形成工程と、前記アモルファスシリコン膜をアニールして多結晶化する工程とを含むことを特徴とする。
（１１）上記多結晶シリコン膜を形成する工程を、触媒ＣＶＤ法により形成する工程としたことを特徴とする。これにより、ＣＶＤ法でもアニール処理なしで直接多結晶シリコン膜を形成することができる。
（１２）上記非単結晶シリコン膜を形成する工程を、触媒ＣＶＤ法により形成する工程とし、多結晶シリコンを含む膜を形成する工程としたことを特徴とする。
（１３）上記非単結晶シリコン膜を形成する工程を、プラズマＣＶＤ法により形成する工程とし、アモルファスシリコンを含む膜を形成する工程としたことを特徴とする。
【００２５】
【実施例】
以下、図面にしたがい本発明の実施例を具体的に説明する。
（実施例１）
図１、図６〜図１４を用いて第１の実施例を説明する。
図６は、液晶を用いた画像表示装置の構成図である。複数のゲート線Ｇ０と、複数のゲート線にマトリクス状に交差する複数の信号線ＳＤ０とを有し、ゲート線と信号線との交点には画素ＴＦＴ１０３が配置されている。なお、同図中の符号１００は画素、１０１はドレインドライバ回路、１０２はゲートドライバ回路、１０４は保持容量、１０５は液晶容量、Ｃ０はコモン線をそれぞれ示す。
【００２６】
図７は、図６に示した画素１００の平面レイアウト図である。なお、図７中の符号Ｇ１はゲート電極、ＳＤ１はソース／ドレイン電極、ＰＳＩはポリシリコン膜、ＩＮＴは層間絶縁膜、ＨＤＡは高濃度ｎ型アモルファスシリコン層、Ｃ１はコモン線、ＰＸ１は画素電極をそれぞれ示す。
【００２７】
図８は図７中のＡ−Ａ’での断面図であり、画素電極ＰＸ１と対向電極ＰＸ２とで液晶容量を形成している。ゲート電極Ｇ１は、バックライト２０４からＴＦＴを構成するチャネル及びオセット領域Ｗ１内のポリシリコン膜ＰＳＩへ照射される光を遮光し、光リーク電流の発生を防止する（Ｗ１＜Ｗ２）。また、ブラックマトリックスＢＭは、対向基板ＳＵＢ側からポリシリコン膜ＰＳＩへ照射される光を遮光する。
【００２８】
なお、図８中の符号２００は液晶層、２０３は偏光板、２０１は配向膜、２０２は保護絶縁膜、ＣＦはカラーフィルタ、Ｗ１はチャネル及びオセット領域の幅、Ｗ２はゲート電極Ｇ１の幅をそれぞれ示す。
【００２９】
図１は、既に説明したようにボトムゲート型ポリシリコンＴＦＴの構造及びゲート線と信号線の交差部の断面図を示したもので、図８において画素電極ＰＸ１形成後の構成を示している。
【００３０】
また、図９は図７中のＢ−Ｂ’での断面図であり、コモン電極Ｃ１（ゲート電極Ｇ１と同じ導電層）と画素電極ＰＸ１とで保持容量を形成している。
【００３１】
以下、図１に示すＴＦＴの製造方法を図１０〜図１４に示した断面工程図に従って述べる。
【００３２】
先ず図１０に示すように、ガラス基板ＳＵＢ上に酸化シリコン膜（ＳｉＯ２）からなるバッファ層Ｌ１をプラズマＣＶＤ法により膜厚１００ｎｍ堆積し、さらにスパッタリング法によりゲート線Ｇ０、ゲート電極Ｇ１、コモン電極Ｃ１となるＡｌを２５０ｎｍ堆積し、周知のホトエッチング工程によりＡｌをパターンニングする（この図ではゲート電極Ｇ１のみを示している）。
【００３３】
次に図１１に示すように、プラズマＣＶＤ法によりゲート絶縁膜ＧＩ（本実施例では酸化シリコン膜）を１００ｎｍ、層間絶縁膜ＩＮＴ（本実施例では窒化シリコン膜）を５００ｎｍ、高濃度ｎ型アモルファスシリコン膜ＨＤＡ（本実施例ではリンドープアモルファスシリコン膜）５０ｎｍを堆積し、さらにソース／ドレイン電極ＳＤ１となるＴｉ−ＴｉＷ−Ａｌ−ＴｉＷ−Ｔｉの５層金属膜Ｍ１を形成する。
【００３４】
ここで金属膜Ｍ１の最下層のＴｉ膜は、高濃度ｎ型アモルファスシリコン膜ＨＤＡとＡｌとのコンタクト抵抗の低減、Ａｌの高濃度ｎ型アモルファスシリコン膜中への拡散防止等の役割を果たす。また、最上層のＴｉは、Ａｌと画素電極ＰＸ１とのコンタクト抵抗を低減する役割を果たす。
【００３５】
その後、図１２に示すように、周知のホトエッチング工程によりチャネル領域をパターンニングし、５層金属膜Ｍ１を選択的に除去する。この時サイドエッチングによりレジストＲＥＳ下部の５層金属膜も除去され縮小加工される。
【００３６】
次に、図１３に示すように、レジストＲＥＳを後退させながら、高濃度ｎ型アモルファスシリコン層ＨＤＡと層間絶縁膜ＩＮＴをエッチングし、層間絶縁膜ＩＮＴをテーパ状に加工する。この時、後のレーザ結晶化工程において良質なポリシリコン膜を得るために、高濃度ｎ型アモルファスシリコン層ＨＤＡと接する層間絶縁膜ＩＮＴの端部のゲート絶縁膜ＧＩ上の投影点と、ゲート絶縁膜ＧＩと接する層間絶縁膜ＩＮＴの端部との間隔Ｔ１は、層間絶縁膜の膜厚Ｔ２より大きい（Ｔ１＞Ｔ２）であることが望ましい。
【００３７】
図１４に示すように、レジストＲＥＳを除去した後、プラズマＣＶＤ法によりアモルファスシリコン層を５０ｎｍ堆積し、ＸｅＣｌエキシマレーザを照射しアモルファスシリコン層を結晶化し、周知のホトエッチング工程により、島状のポリシリコン層ＰＳＩを形成する。
【００３８】
その後、全体を覆うように窒化シリコンよりなる膜厚５００ｎｍの保護絶縁膜Ｌ２を形成し、さらに保護絶縁膜Ｌ２に設けたコンタクトスルーホールを介してインジウム錫酸化物（ＩＴＯ）からなる画素電極ＰＸ１とソース／ドレイン電極ＳＤ１とがコンタクトされる。この状態を図１のａ部に示している。
【００３９】
本実施例によれば、イオン打ち込みおよび不純物活性化アニールを省略できるため、スループットが向上する。さらに、ソース／ドレイン電極ＳＤ１の加工と層間絶縁膜ＩＮＴの加工を同一マスク（レジストＲＥＳ）で行うため、ホトエッチング工程を追加することがなく、低コストの画像表示装置が得られる。また、ゲート線Ｇ０と信号線ＳＤ０との間に層間絶縁膜ＩＮＴを有するため、寄生容量が低減でき、画像信号の高速書き込み、画面の大型化が可能となる。
【００４０】
本実施例によれば、層間絶縁膜ＩＮＴに接するポリシリコン層ＰＳＩはオフセットの役割を果たすためオフ電流を低減することが可能である。
【００４１】
なお、図８に示すように、バックライト２０４による光リーク電流の発生を抑制するために、高濃度ｎ型アモルファスシリコン層ＨＤＡはソース側、ドレイン側ともにゲート電極Ｇ１にオーバーラップしており、チャネル領域及びオフセット領域を形成するポリシリコン膜の幅Ｗ１は、ゲート電極の幅Ｗ２よりも短くする必要がある（Ｗ１＜Ｗ２）。
【００４２】
（実施例２）
図１５は本発明の第２の実施例を示すものであり、図７中のＡ−Ａ’での断面図に該当し、画素電極ＰＸ１形成後の構成である。すなわち、図１５は、実施例１におけるゲート絶縁膜ＧＩを、窒化シリコン膜ＧＩ２と酸化シリコン膜ＧＩ１との積層膜にした構造である。
【００４３】
本実施例によれば、ゲート絶縁膜に酸化シリコンよりも誘電率の高い窒化シリコンを併用することによりＴＦＴの高性能化が可能である。また、酸化シリコン膜ＧＩ１は、層間絶縁膜ＩＮＴをエッチングする際、ゲート絶縁膜がエッチングされるのを防止する役割と、ポリシリコン層ＰＳＩとゲート絶縁膜との界面準位を低減する役割を果たしている。
【００４４】
（実施例３）
図１６は本発明の第３の実施例を示すものであり、図７中のＡ−Ａ’での断面図に該当し、画素電極ＰＸ１形成後の構成である。すなわち、図１６は、実施例２におけるゲート絶縁膜ＧＩを、ゲート電極の陽極酸化膜ＧＩ３（本実施例では酸化アルミニウム膜）と酸化シリコン膜ＧＩ１との積層膜にした構造である。
【００４５】
本実施例によれば、ゲート絶縁膜を陽極酸化により形成するためプロセスが簡略化できる。さらには、ゲート絶縁膜として誘電率の高い酸化アルミニウムを併用するため、酸化シリコン膜単独の場合よりもＴＦＴの高性能化が可能である。
【００４６】
（実施例４）
本発明の第４の実施例を図１７〜図１９を用いて説明する。図１７は本発明の画像表示装置の回路ブロック構成図である。本実施例ではゲートドライバ回路１０２がＴＦＴにより構成されており、図中にゲートドライバ回路の一部であるブートストラップ回路の構成図を示す。画素１００の平面レイアウト図は図７と同様である。図７中のＡ−Ａ’での断面図は図８と同様である。図７中のＢ−Ｂ’での断面図は図９と同様である。
【００４７】
図１８にブートストラップ回路１０６の平面レイアウト図を示す。図１９は図１８中のＣ−Ｃ’での断面図で、画素電極ＰＸ１形成後の構成を示す。実施例１において層間絶縁膜ＩＮＴを成膜後、周知のホトエッチング工程によりコンタクト領域を開口し、その後、高濃度ｎ型アモルファスシリコン層ＨＤＡおよびソース／ドレイン電極ＳＤ１を形成することにより図１９の構造を得る。
【００４８】
本実施例によれば、画素部を駆動する周辺駆動回路の一部を、画素部と同一基板上に、しかも画素部と同様のポリシリコンＴＦＴで構成することにより、画素部と周辺駆動回路との接続端子数が低減でき、高精細な画像表示ができる。さらに、周辺駆動回路を構成するＬＳＩ数を削減できるため、画像表示装置の低コスト化が可能である。
【００４９】
（実施例５）
本発明の第５の実施例を図２０〜図２４を用いて説明する。本実施例における画像表示装置の構成図は図１７と同様である。図２０は画素１００の平面レイアウト図である。また、図２１はゲートドライバ回路１０２の一部であるブートストラップ回路１０６の平面レイアウト図である。図２２は図２０中のＤ−Ｄ’での断面図、図２３は図２１中のＥ−Ｅ’での断面図であり、画素電極ＰＸ１形成後の構成を示す。
【００５０】
この図２３に示すゲートドライバ回路１０２を構成するＴＦＴは、実施例１において層間絶縁膜ＩＮＴ成膜後、周知のホトエッチング工程によりゲート電極上方の層間絶縁膜を除去し、その後、高濃度ｎ型アモルファスシリコン層ＨＤＡおよびソース／ドレイン電極ＳＤ１を形成している。この時、回路高性能化のため、図２３に示した回路を構成するＴＦＴのゲート電極Ｇ１と高濃度不純物アモルファスシリコン層ＨＤＡとのオーバーラップ長ＯＦＦ２は、図２２に示した画素を構成するＴＦＴのゲート電極Ｇ１と高濃度不純物アモルファスシリコン層ＨＤＡとのオーバーラップ長ＯＦＦ１よりも短いことが望ましい。すなわち、ＯＦＦ１（画素のＴＦＴにおけるＧ１とＨＤＡとのオーバーラップ長）＞ＯＦＦ２（ゲートドライバ回路のＴＦＴにおけるＧ１とＨＤＡとのオーバーラップ長）の関係が望ましい。
【００５１】
図２４はゲートドライバ回路１０２を示す図２１中のＦ−Ｆ’での断面図であり、画素電極ＰＸ１形成後の構成を示す。ゲート電極Ｇ１とソース／ドレイン電極ＳＤ１とで容量を形成している。
【００５２】
本実施例によれば、図２３に示したように、ゲートドライバ回路１０２を構成するＴＦＴにはオフセット領域がないため、ＴＦＴのオン電流を高くでき、回路の高性能化が可能である。
【００５３】
（実施例６）
本発明の第６の実施例を図２５〜図３１を用いて説明する。本実施例における画像表示装置の構成図は図６と同様である。ただし、実施例１の図１に示した画素を構成するＴＦＴのチャネル領域を構成する構造が、本実施例ではこの後に図２６で説明するように異なっている。
【００５４】
図２５は、画素１００の平面レイアウト図である。図２６は図２５中のＧ−Ｇ’での断面図であり、画素電極ＰＸ１形成後の構成を示している。図２６に示すＴＦＴの製造方法を、図２７〜図３１に示す断面工程図に従って述べる。
【００５５】
先ず、図２７に示すように、実施例１で説明した図１０と同様に、ガラス基板ＳＵＢ上にバッファ層Ｌ１、ゲート電極Ｇ１を形成する。
【００５６】
次に、図２８に示すように、プラズマＣＶＤ法によりゲート絶縁膜ＧＩ、層間絶縁膜ＩＮＴを形成し、触媒ＣＶＤ法により高濃度ｎ型ポリシリコン層ＨＤＮを形成し、スパッタリングによりソース／ドレイン電極ＳＤ１となるＴｉ−ＴｉＷ−Ａｌ−ＴｉＷ−Ｔｉの５層金属膜Ｍ１を形成する。なお、この工程で実施例１と異なるのは、実施例１ではプラズマＣＶＤ法により高濃度ｎ型アモルファスシリコン層ＨＤＡを形成したが、ここでは触媒ＣＶＤ法により高濃度ｎ型ポリシリコン層ＨＤＮを形成した。
【００５７】
その後、図２９に示すように、周知のホトエッチング工程によりチャネル領域をパターンニングし、５層金属膜を選択的に除去する。この時サイドエッチングによりレジストＲＥＳ下部の５層金属膜も除去する。この製造工程は実施例１の図１２とほぼ同じであるが、図２９に示すように５層金属膜Ｍ１のサイドエッチングの量が実施例１の場合より少し浅い。
【００５８】
次に、図３０に示すように、異方性エッチング（ここでは周知のドライエッチング）により、高濃度ｎ型ポリシリコン層ＨＤＮと層間絶縁膜ＩＮＴをエッチングする。
【００５９】
次に、図３１に示すように、レジスト除去の後、触媒ＣＶＤ法によりポリシリコン層を１００ｎｍ堆積し、周知のホトエッチング工程により、島状のポリシリコン層ＰＳＩを形成する。なお、実施例１ではプラズマＣＶＤ法によりアモルファスシリコンを形成してからレーザアニールでポリシリコンとしたが、ここでは触媒ＣＶＤ法により直接ポリシリコン層を形成しているので、レーザアニールは不要であり工程が簡略化される。
【００６０】
その後、全体を覆うように窒化シリコンよりなる膜厚５００ｎｍの保護絶縁膜Ｌ２を形成し、さらに保護絶縁膜Ｌ２に設けたコンタクトスルーホールを介して画素電極ＰＸ１とソース／ドレイン電極ＳＤ１とがコンタクトされ、図２６に示した構造の画素を構成するＴＦＴが得られる。
【００６１】
本実施例によれば、図３０に示したように、層間絶縁膜ＩＮＴをドライエッチングにより加工するため、チャネル長のバラツキを低減できる。さらにオフセット長が層間絶縁膜の膜厚で制御できるため、オフセット長のバラツキを低減でき、ＴＦＴ性能の均一性を向上できる。この場合、高濃度ｎ型ポリシリコン層ＨＤＮと接する層間絶縁膜ＩＮＴの端部のゲート絶縁膜ＧＩ上の投影点と、ゲート絶縁膜ＧＩと接する層間絶縁膜ＩＮＴの端部との間隔Ｔ１は、層間絶縁膜ＩＮＴの膜厚Ｔ２以下であることが望ましい（Ｔ１＞Ｔ２）。
【００６２】
（実施例７）
本発明の第７の実施例を図３２〜図４１を用いて説明する。
図３２は画像表示装置の構成図である。本実施例ではゲートドライバ回路１０２が画素部と同一基板上に形成されたＴＦＴにより構成されており、図中にゲートドライバ回路の一部であるＣＭＯＳ１０７の構成図を示す。
【００６３】
図３３は図３２に示した画素１００の平面レイアウト図である。図３３中のＨ−Ｈ’での断面図は図２６と同様である。
【００６４】
図３４は図３２のゲートドライバ回路１０２中のＣＭＯＳ１０７の平面レイアウト図である。
【００６５】
図３５は図３４中のＪ−Ｊ’での断面図であり、画素電極ＰＸ１形成後の構成を示す。図３５に示すＴＦＴの製造方法を図３６〜図４１に示した断面工程図に従って述べる。
【００６６】
先ず、図３６に示すように、実施例６と同様に、ガラス基板ＳＵＢ上にバッファ層Ｌ１、ゲート電極Ｇ１を形成し、ゲート絶縁膜ＧＩ、層間絶縁膜ＩＮＴ、高濃度ｎ型ポリシリコン層ＨＤＮ、Ｔｉ−ＴｉＷ−Ａｌ−ＴｉＷ−Ｔｉの５層金属膜Ｍ１（ソース／ドレイン電極ＳＤ１となるもの）を順次形成する。さらに周知のホトエッチング工程によりＣＭＯＳ用に２種のチャネル領域（ｐチャネル／ｎチャネル）をパターンニングし、５層金属膜にサイドエッチングを施した後、異方性エッチング（周知のドライエッチング）により、高濃度ｎ型ポリシリコン層ＨＤＮと層間絶縁膜ＩＮＴをエッチングする。
【００６７】
その後、図３７に示すように、ｐチャネルＴＦＴを除く領域（この図では右側のｎチャネル領域）にマスク絶縁膜Ｌ４を形成し、マスク絶縁膜Ｌ４及びソース／ドレイン電極ＳＤ１をマスクにして高濃度ｎ型ポリシリコン層と層間絶縁膜を除去する。
【００６８】
次に図３８に示すように、高濃度ｐ型ポリシリコン層ＨＤＰを触媒ＣＶＤ法により形成し、さらに図３９に示すように、異方性エッチング（ここではドライエッチング）により層間絶縁膜ＩＮＴ側面を除く高濃度ｐ型ポリシリコン層を除去する。
【００６９】
その後、図４０に示すようにマスク絶縁膜Ｌ４を除去し、続いて図４１に示すように、触媒ＣＶＤ法によりポリシリコン層ＰＳＩを１００ｎｍ堆積し、周知のホトエッチング工程により、島状のポリシリコン層ＰＳＩを形成する。このようにして図３５に示す構造のＣＭＯＳが形成される。
【００７０】
本実施例では、ＣＭＯＳを用いて回路を構成するため、周辺駆動回路の小型化、低電力化が可能である。
【００７１】
（実施例８）
図４２は本発明の第８の実施例となる画像表示装置の構成図である。図４３は図４２中の画素１００の平面レイアウト図を示す。保持容量１０４は、コモン電極Ｃ１とソース／ドレイン電極ＳＤ１とで構成されており、液晶容量１０５は画素電極ＰＸ１とソース／ドレイン電極ＳＤ１とで構成されている。また、画素電極ＰＸ１、コモン電極Ｃ１、コモン線Ｃ０は全て同一層で形成されている。
【００７２】
本実施例によれば、ＴＦＴ基板上に形成された画素電極ＰＸ１とソース／ドレイン電極ＳＤ１との間の横方向電界によって液晶を駆動するため、液晶の複屈折性による色変化を抑制でき、液晶表示装置の広視野角化が可能である。
【００７３】
（実施例９）
本発明の第９の実施例における画像表示装置の構成図は図６と同様である。
図４４に画素１００の平面レイアウト図を示す。保持容量１０４は、コモン電極Ｃ１と画素電極ＰＸ１とで構成されており、液晶容量１０５は画素電極ＰＸ１と対向電極ＰＸ２とで構成されている。
【００７４】
ＴＦＴ基板上に形成された画素電極ＰＸ１と、対向基板上に形成された対向電極ＰＸ２は、それぞれパターンニングされており、基板上に突起状の電極が形成されている。この電極により電圧印加時の液晶分子配向方向を斜めに制御する。
【００７５】
本実施例によれば、基板上に突起状の電極を形成し、電圧印加時の液晶分子が斜めに配向される方向が、一画素内において複数の方向になるように制御するため、液晶表示装置の広視野角化が可能である。
【００７６】
以上実施例１から実施例９に記載の画像表示装置において、基板ＳＵＢは必ずしもガラス基板である必要はなく、例えばプラスチックなどの他の絶縁性基板であってもよい。
【００７７】
バッファ層Ｌ１としては、酸化シリコン膜の代わりに窒化シリコン膜あるいは酸化シリコン膜と窒化シリコン膜との積層膜を用いても良い。窒化シリコン膜をバッファ層として用いれば、ガラス基板ＳＵＢ内の不純物がゲート絶縁膜ＧＩ中に拡散侵入するのを効果的に防止できる。
【００７８】
また、ゲート電極Ｇ１の材料は、Ａｌに限らずＴｉ、Ｔａ等周知の電極材料であっても良い。層間絶縁膜ＩＮＴは酸化シリコン膜あるいは酸化シリコン膜と窒化シリコン膜との積層膜であっても良いし、他の周知の低誘電率材料であっても良い。
【００７９】
実施例２に記載の画像表示装置において、ゲート絶縁膜ＧＩ２の材料は、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｌａ２Ｏ３、Ｔａ２Ｏ５、ＺｒＯ２、ＬａＡｌＯ３、ＺｒＴｉＯ４、ＨｆＯ２、ＳｒＺｒＯ３、ＴｉＯ２、ＳｒＴｉＯ３、ＳｒＢｉ２Ｔａ２Ｏ９、（ＢａｘＳｒ１−ｘ）ＴｉＯ３、Ｐｂ（ＺｒｙＴｉ１−ｙ）Ｏ３等の周知の高誘電率材料であっても良い。
【００８０】
実施例３に記載の画像表示装置において、ゲート電極Ｇ１の材料は、Ｔｉ、Ｚｒ、Ｈｆ、Ｔａ、Ｎｂまたはそれらの合金等、その酸化膜が高誘電率材料である周知の電極材料であっても良い。また、酸化の方法は、陽極酸化に限らず酸素プラズマ処理であっても良い。
【００８１】
実施例８及び実施例９に記載の画像表示装置において、画素ＴＦＴ１０３の断面構造は、実施例１〜３、実施例６に記載のいずれであっても良い。また、ゲートドライバ回路１０２を構成するＴＦＴの断面構造は実施例４、実施例５、実施例７に記載のいずれであっても良い。保持電極は、コモン電極Ｃ１の代わりに前段のゲート線Ｇ０の一部を用いることも可能である。
【００８２】
本発明は、表示手段として液晶を用いるものに限らずエレクトロルミネッセンスを利用した画像表示装置にも適用できる。
【００８３】
【発明の効果】
以上詳述したように、本発明によりゲート線と信号線との交差部における容量を低下させ、かつ製造コストの低い画像表示装置、さらにはオフ電流を低下させ、かつ、製造コストの低い画像表示装置をそれぞれ実現するという所期の目的を達成することができる。
【００８４】
すなわち、本発明は、ボトムゲート型ＴＦＴを用いることにより製造コストを低減でき、かつ、ゲート線と信号線との間に層間絶縁膜を形成することにより、層間容量を低減した画像表示装置を提供できる。
【図面の簡単な説明】
【図１】実施例１の薄膜トランジスタの断面図。
【図２】従来のポリシリコン薄膜トランジスタの製造工程の一例を示す断面図。
【図３】従来のポリシリコン薄膜トランジスタの製造工程の一例を示す断面図。
【図４】従来のポリシリコン薄膜トランジスタの製造工程の一例を示す断面図。
【図５】従来のアモルファスシリコン薄膜トランジスタ及びゲート線と信号線との交差部の断面図。
【図６】本発明に係る液晶表示装置の構成図。
【図７】本発明に係る液晶表示装置における画素の平面レイアウト図。
【図８】図７中のＡ−Ａ’断面図。
【図９】図７中のＢ−Ｂ’断面図。
【図１０】実施例１の製造工程を示す断面図。
【図１１】実施例１の製造工程を示す断面図。
【図１２】実施例１の製造工程を示す断面図。
【図１３】実施例１の製造工程を示す断面図。
【図１４】実施例１の製造工程を示す断面図。
【図１５】実施例２の薄膜トランジスタの断面図。
【図１６】実施例３の薄膜トランジスタの断面図。
【図１７】実施例４及び実施例５の液晶表示装置の構成図。
【図１８】実施例４の液晶表示装置におけるブートストラップ回路の平面レイアウト図。
【図１９】実施例４の薄膜トランジスタの断面図。
【図２０】実施例５の液晶表示装置における画素の平面レイアウト図。
【図２１】実施例５の液晶表示装置におけるブートストラップ回路の平面レイアウト図。
【図２２】実施例５の液晶表示装置における画素を構成する薄膜トランジスタの断面図。
【図２３】実施例５の液晶表示装置における周辺駆動回路を構成する薄膜トランジスタの断面図。
【図２４】実施例５の液晶表示装置における周辺駆動回路を構成する容量素子の断面図。
【図２５】実施例６の液晶表示装置における画素の平面レイアウト図。
【図２６】実施例６の薄膜トランジスタの断面図。
【図２７】実施例６の製造工程を示す断面図。
【図２８】実施例６の製造工程を示す断面図。
【図２９】実施例６の製造工程を示す断面図。
【図３０】実施例６の製造工程を示す断面図。
【図３１】実施例６の製造工程を示す断面図。
【図３２】実施例７の液晶表示装置の構成図。
【図３３】実施例７の液晶表示装置における画素の平面レイアウト図。
【図３４】実施例７の液晶表示装置におけるＣＭＯＳの平面レイアウト図。
【図３５】実施例７の液晶表示装置におけるＣＭＯＳを構成する薄膜トランジスタの断面図。
【図３６】実施例７の製造工程を示す断面図。
【図３７】実施例７の製造工程を示す断面図。
【図３８】実施例７の製造工程を示す断面図。
【図３９】実施例７の製造工程を示す断面図。
【図４０】実施例７の製造工程を示す断面図。
【図４１】実施例７の製造工程を示す断面図。
【図４２】実施例８の液晶表示装置の構成図。
【図４３】実施例８の液晶表示装置における画素の平面レイアウト図。
【図４４】実施例９の液晶表示装置における画素の平面レイアウト図。
【符号の説明】
ＳＵＢ…ガラス基板、ＰＳＩ…ポリシリコン膜、ＡＳＩ…アモルファスシリコン膜、Ｌ１…バッファ層、Ｌ２…保護絶縁膜、Ｌ３…チャネルエッチング防止膜、Ｌ４…マスク絶縁膜、Ｇ０…ゲート線、Ｇ１…ゲート電極、ＳＤ０…信号線、ＳＤ１…ソース／ドレイン電極、Ｃ０…コモン線、Ｃ１…コモン電極、ＧＩ…ゲート絶縁膜、ＧＩ１…酸化シリコン膜、ＧＩ２…窒化シリコン膜、ＧＩ３…ゲート電極の陽極酸化膜、ＩＮＴ…層間絶縁膜、ＨＤＡ…高濃度ｎ型アモルファスシリコン層、ＨＤＮ…高濃度ｎ型ポリシリコン層、ＬＤＮ…低濃度ｎ型ポリシリコン層、ＨＤＰ…高濃度ｐ型ポリシリコン層、Ｍ１…５層金属膜、ＰＸ１…画素電極、ＰＸ２…対向電極、ＲＥＳ…レジスト、ＣＦ…カラーフィルタ、ＢＭ…ブラックマトリックス、１００…画素、１０１…ドレインドライバ回路、１０２…ゲートドライバ回路、１０３…画素ＴＦＴ、１０４…保持容量、１０５…液晶容量、１０６…ブートストラップ回路、１０７…ＣＭＯＳ、２００…液晶層、２０１…配向膜、２０２…保護絶縁膜、２０３…偏光板、２０４…バックライト。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image display device and a method for manufacturing the same, and more particularly to an image display device suitable for being manufactured at low cost and a method for manufacturing the same.
[0002]
[Prior art]
Polysilicon thin film transistors (hereinafter abbreviated as TFTs) have excellent performance in that the mobility is two orders of magnitude higher than that of amorphous silicon TFTs. An example utilizing this feature is, for example, an active matrix type liquid crystal display device described in Non-Patent Document 1. In this display device, the number of connection terminals between the pixel portion and the peripheral drive circuit can be reduced by forming a part of the peripheral drive circuit with a polysilicon TFT, and a high-definition image display can be performed.
[0003]
A conventional method for manufacturing a polysilicon TFT will be described with reference to FIGS.
[0004]
First, as shown in FIG. 2, a 100-nm-thick silicon oxide film L1 is deposited as a buffer layer on a glass substrate SUB, and a 50-nm-thick amorphous silicon layer is deposited by a plasma CVD method. Next, the amorphous silicon layer is crystallized by irradiating a XeCl excimer laser, and an island-shaped polysilicon layer PSI is obtained by a known photo-etching process. Thereafter, a gate insulating film GI is deposited to a thickness of 100 nm by a plasma CVD method, and a gate electrode G1 is formed.
[0005]
Next, as shown in FIG. 3, after the low concentration n-type polysilicon layer LDN is formed by ion implantation of phosphorus using the gate electrode G1 as a mask, the low concentration n-type polysilicon layer LDN is provided on the low concentration n-type polysilicon layer LDN (not shown). A high-concentration n-type polysilicon layer HDN is formed using the resist as a mask.
[0006]
As shown in FIG. 4, an interlayer insulating film INT made of silicon oxide is formed so as to cover the whole, and furnace annealing at 600 ° C. is performed for 5 hours to activate impurities. Further, source / drain electrodes SD1 are formed through contact through holes provided in the interlayer insulating film INT.
[0007]
Conventional polysilicon TFTs require ion implantation and impurity activation steps in order to form low-resistance source / drain regions, thus reducing throughput.
[0008]
As means for omitting these steps, there is a method of laminating a high-concentration n-type amorphous silicon layer and source / drain electrodes on a silicon layer as in a conventional amorphous silicon TFT. This example is shown in FIG.
[0009]
As shown in FIG. 5, after the formation of the gate insulating film GI, an amorphous silicon layer ASI and a channel etching prevention film L3 are formed, and the high-concentration n-type amorphous silicon layer HDA and the source / drain electrode SD1 are laminated to form ions. The steps of implanting and activating impurities can be omitted.
[0010]
However, in this structure, since the capacity at the intersection of the gate line G0 and the signal line SD0 is large, it has been difficult to rewrite the image signal at high speed and to enlarge the screen. Furthermore, when the structure of a conventional amorphous silicon TFT is applied to a polysilicon TFT, the mobility of polysilicon is higher than that of amorphous silicon by two digits or more, so that there is a problem that the off-current increases.
[0011]
In order to reduce the capacitance among the above problems, it is effective to form an insulating film between the gate line G0 and the signal line SD0. However, in this method, a photoetching step for forming an insulating film is added, so that the throughput is reduced and the cost is increased.
[0012]
In order to reduce the off-state current, there is a method of forming a low-concentration impurity layer between a polycrystalline semiconductor layer and a high-concentration impurity layer as described in Patent Document 1. However, in this method, a photoetching step for forming a low-concentration impurity layer is added, so that the throughput is reduced and the cost is increased.
[0013]
[Non-patent document 1]
Society for Information Display International Symposium Digest of Technical Papers pp. 172 (Society for Information Display International Symposium Digest of Technical Papers pp. 1992).
[Patent Document 1]
JP-A-7-131030
[0014]
[Problems to be solved by the invention]
Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and a first object of the present invention is to reduce the capacitance at the intersection of a gate line and a signal line and to reduce the manufacturing cost. Is to provide.
[0015]
A second object is to provide an image display device with reduced off-current and low manufacturing cost.
[0016]
[Means for Solving the Problems]
The above object of the present invention is attained by an image display device and a method of manufacturing the same, in which the features of the present invention are described below.
[0017]
That is, the image display device of the present invention is an image display device having a plurality of thin film transistors on a substrate, and a plurality of gate lines and a plurality of signal lines crossing the gate lines in a matrix on the substrate. The thin film transistor is a bottom gate type, the channel region has a laminated structure in which a gate electrode / gate insulating film / polycrystalline silicon film is sequentially laminated from the substrate side, and the source electrode and the drain electrode portion are From the side, a gate insulating film / interlayer insulating film / non-single-crystal silicon film / metal film is sequentially laminated, and the polycrystalline silicon film includes the gate insulating film, the interlayer insulating film, and the non-crystalline silicon film. A stacked insulating film formed of the gate insulating film and the interlayer insulating film at an intersection of the signal line and the gate line; Characterized in that it has.
[0018]
Further, a feature of the method for manufacturing an image display device of the present invention is a step of forming a bottom-gate thin film transistor on a substrate, a step of forming a gate electrode on the substrate, and a step of forming a gate insulating film on the gate electrode. Forming, forming an interlayer insulating film on the gate insulating film, forming a non-single-crystal silicon film on the interlayer insulating film, and forming a metal film on the non-single-crystal silicon film Process, processing the metal film using a resist as a mask, further processing the metal film to reduce the resist by side etching, forming a source electrode and a drain electrode, using the same resist as a mask, Etching the non-single-crystal silicon film and the interlayer insulating film; and contacting the gate insulating film, the interlayer insulating film and the non-single-crystal silicon film with a polycrystalline silicon film. Characterized in that it comprises a step of forming a silicon film.
[0019]
According to the image display device of the present invention, the steps of ion implantation and impurity activation can be omitted by using a bottom gate polysilicon thin film transistor (TFT), and the metal film, the non-single-crystal silicon film, and the interlayer Since the processing of the insulating film is performed using the same resist mask, the cost of the image display device can be reduced without adding a photoetching step.
[0020]
In the image display device of the present invention, a stacked insulating film of a gate insulating film and an interlayer insulating film is formed between a gate line in the same layer as the gate electrode and a signal line in the same layer as the source / drain electrodes. In addition, the interlayer capacitance can be reduced, the size of the image display device can be increased, and image signals can be rewritten at high speed.
[0021]
Further, when a voltage is applied to the gate electrode, the carrier concentration induced in the polycrystalline silicon film formed in contact with the side surface of the interlayer insulating film is induced in the polycrystalline silicon film formed in contact with the gate insulating film. Lower than the carrier concentration. Therefore, the thin film transistor of the present invention has an offset structure, and can reduce off current.
[0022]
Note that the term non-single-crystal silicon film used here means that it is not a single-crystal silicon film. Specifically, an amorphous silicon film, a polycrystalline silicon film, or both of these are partially used. Containing film.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
A typical embodiment of the present invention will be described below.
(1) A cross-sectional view of FIG. 1 shows a structure of a typical bottom gate type polysilicon TFT formed on a substrate of an image display device of the present invention and an intersection of a gate line and a signal line. This figure shows a state after the pixel electrode PX1 is formed in the manufacturing process of the image display device. 1A shows a TFT region, and FIG. 1B shows an intersection of a gate line and a signal line. Silicon oxide is provided as a buffer layer L1 on a glass substrate SUB, and a TFT, a driving circuit necessary for an image display device, and the like are formed on the substrate.
[0024]
In FIG. 1, reference symbol G1 denotes a gate electrode, GI denotes a gate insulating film, INT denotes an interlayer insulating film, PSI denotes a polysilicon film (polycrystalline silicon film), and HDA denotes a high-concentration n-type amorphous silicon layer (a non-single-crystal silicon film). One example), SD1 is a source / drain electrode (metal film), L2 is a protective insulating film, PX1 is a pixel electrode, G0 is a gate line, and SD0 is a signal line.
(2) A preferable configuration of the TFT is that the metal film forming the source / drain electrode SD1 and the signal line SD0 is reduced in size in a self-aligned manner with respect to the non-single-crystal silicon film.
(3) The interlayer insulating film INT above the gate electrode is processed into a tapered shape, and a projection point on the gate insulating film at the end of the interlayer insulating film INT in contact with the non-single-crystal silicon film, and the gate insulating film GI The relationship between the two is T1> T2, where T1 is the distance from the end of the interlayer insulating film INT in contact with and T2 is the thickness of the interlayer insulating film INT. That is, the interval T1 is longer than the film thickness T2 of the interlayer insulating film INT. Thereby, high-quality polysilicon can be obtained when a polycrystalline silicon film is formed in a channel region in a manufacturing process including a laser crystallization process.
(4) Contrary to the case of (3), the relationship between the two may be set to T1 ≦ T2. As a result, there are effects that the ON current can be increased and the variation of the offset length can be controlled (reduced).
(5) The gate insulating film GI is preferably a laminated film of a high dielectric constant film and a silicon oxide film. As the high dielectric constant film, for example, Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , ZrO 2 , LaAlO 3 , ZrTiO 4 , HfO 2 , SrZrO 3 , TiO 2 , SrTiO 3 , SrBi 2 Ta 2 O 9 , (Ba x Sr 1-x ) TiO 3 , Pb (Zr y Ti 1-y ) O 3 And other well-known high dielectric constant materials.
(6) The gate insulating film GI is preferably a laminated film of an oxide film and a silicon oxide film of the gate electrode G1.
(7) When the width of the polycrystalline silicon film in contact with the gate insulating film and the interlayer insulating film is W1 and the width of the gate electrode is W2, the relationship between the two is W1 <W2. Thus, when the image display device is configured by a liquid crystal display device, it is possible to suppress the occurrence of light leakage current due to the backlight. Since the polycrystalline silicon PSI in contact with the interlayer insulating film INT plays a role of an offset, the off-state current can be reduced.
(8) A preferred image display device of the present invention is a liquid crystal display device having a pair of insulating substrates and a liquid crystal layer sandwiched therebetween, and the liquid crystal display device has a plurality of thin film transistors. Has a source electrode and a drain electrode, and a pixel electrode formed on the source electrode and the drain electrode with an insulating film interposed therebetween, and by applying a voltage between the source electrode and the drain electrode and the pixel electrode, A horizontal electric field parallel to the substrate is generated, and the liquid crystal alignment is controlled by the horizontal electric field.
(9) An image display device having a plurality of CMOSs formed of thin film transistors on a substrate, wherein the thin film transistors are of a bottom gate type, and a channel region is a gate electrode / gate insulating film / polycrystalline silicon film from the substrate side. Have a laminated structure in which a gate insulating film / interlayer insulating film / non-single-crystal silicon film / metal film are laminated from the substrate side, In the n-type thin film transistor, the non-single-crystal silicon film has n-type conductivity, and the polycrystalline silicon film is formed in contact with a gate insulating film, an interlayer insulating film, and an n-type non-single-crystal silicon film, respectively. In the p-type thin film transistor, a p-type non-single-crystal silicon film is formed in contact with a side surface of the interlayer insulating film and a side surface of the metal film. Characterized in that it is formed in contact with the gate insulating film and the p-type non-single crystal silicon film.
(10) The step of forming the polycrystalline silicon film includes a step of forming an amorphous silicon film formed by a plasma CVD method and a step of annealing the amorphous silicon film to make it polycrystalline. .
(11) The step of forming the polycrystalline silicon film is a step of forming by a catalytic CVD method. Thus, the polycrystalline silicon film can be formed directly without annealing even in the CVD method.
(12) The step of forming the non-single-crystal silicon film is a step of forming by a catalytic CVD method and a step of forming a film containing polycrystalline silicon.
(13) The step of forming the non-single-crystal silicon film is a step of forming by a plasma CVD method and a step of forming a film containing amorphous silicon.
[0025]
【Example】
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
(Example 1)
A first embodiment will be described with reference to FIGS. 1 and 6 to 14.
FIG. 6 is a configuration diagram of an image display device using a liquid crystal. It has a plurality of gate lines G0 and a plurality of signal lines SD0 crossing the plurality of gate lines in a matrix, and a pixel TFT 103 is arranged at the intersection of the gate lines and the signal lines. In the figure, reference numeral 100 denotes a pixel, 101 denotes a drain driver circuit, 102 denotes a gate driver circuit, 104 denotes a storage capacitor, 105 denotes a liquid crystal capacitor, and C0 denotes a common line.
[0026]
FIG. 7 is a plan layout diagram of the pixel 100 shown in FIG. In FIG. 7, G1 is a gate electrode, SD1 is a source / drain electrode, PSI is a polysilicon film, INT is an interlayer insulating film, HDA is a high-concentration n-type amorphous silicon layer, C1 is a common line, and PX1 is a pixel electrode. Are respectively shown.
[0027]
FIG. 8 is a cross-sectional view taken along the line AA ′ in FIG. 7, and a liquid crystal capacitance is formed by the pixel electrode PX1 and the counter electrode PX2. The gate electrode G1 blocks light emitted from the backlight 204 to the channel forming the TFT and the polysilicon film PSI in the offset region W1, thereby preventing the occurrence of a light leakage current (W1 <W2). The black matrix BM blocks light emitted from the counter substrate SUB to the polysilicon film PSI.
[0028]
8, reference numeral 200 denotes a liquid crystal layer, 203 denotes a polarizing plate, 201 denotes an alignment film, 202 denotes a protective insulating film, CF denotes a color filter, W1 denotes the width of the channel and the offset region, and W2 denotes the width of the gate electrode G1. Shown respectively.
[0029]
FIG. 1 shows a structure of a bottom gate type polysilicon TFT and a cross-sectional view of an intersection of a gate line and a signal line as described above. FIG. 8 shows a structure after the pixel electrode PX1 is formed.
[0030]
FIG. 9 is a cross-sectional view taken along the line BB ′ in FIG. 7, in which a common electrode C1 (the same conductive layer as the gate electrode G1) and the pixel electrode PX1 form a storage capacitor.
[0031]
Hereinafter, a method for manufacturing the TFT shown in FIG. 1 will be described with reference to the cross-sectional process diagrams shown in FIGS.
[0032]
First, as shown in FIG. 10, a silicon oxide film (SiO 2) is formed on a glass substrate SUB. 2 ) Is deposited to a thickness of 100 nm by a plasma CVD method, and 250 nm of Al to be a gate line G0, a gate electrode G1, and a common electrode C1 is deposited by a sputtering method, and the Al is patterned by a known photo-etching process. (Only the gate electrode G1 is shown in this figure).
[0033]
Next, as shown in FIG. 11, a gate insulating film GI (a silicon oxide film in this embodiment) is 100 nm, an interlayer insulating film INT (a silicon nitride film in this embodiment) is 500 nm, and a high-concentration n-type amorphous film is formed by a plasma CVD method. A silicon film HDA (in this embodiment, a phosphorus-doped amorphous silicon film) of 50 nm is deposited, and a five-layer metal film M1 of Ti-TiW-Al-TiW-Ti to be the source / drain electrode SD1 is formed.
[0034]
Here, the lowermost Ti film of the metal film M1 plays a role of reducing contact resistance between the high-concentration n-type amorphous silicon film HDA and Al, preventing diffusion of Al into the high-concentration n-type amorphous silicon film, and the like. Further, the uppermost layer Ti plays a role of reducing the contact resistance between Al and the pixel electrode PX1.
[0035]
Thereafter, as shown in FIG. 12, the channel region is patterned by a well-known photo-etching process, and the five-layer metal film M1 is selectively removed. At this time, the five-layer metal film below the resist RES is also removed by side etching, and is reduced.
[0036]
Next, as shown in FIG. 13, while the resist RES is recessed, the high-concentration n-type amorphous silicon layer HDA and the interlayer insulating film INT are etched to process the interlayer insulating film INT into a tapered shape. At this time, in order to obtain a high-quality polysilicon film in the subsequent laser crystallization step, a projection point on the gate insulating film GI at an end of the interlayer insulating film INT in contact with the high-concentration n-type amorphous silicon layer HDA, It is desirable that the distance T1 between the film GI and the edge of the interlayer insulating film INT in contact with the film GI is larger than the film thickness T2 of the interlayer insulating film (T1> T2).
[0037]
As shown in FIG. 14, after removing the resist RES, an amorphous silicon layer is deposited to a thickness of 50 nm by a plasma CVD method, and the amorphous silicon layer is crystallized by irradiating a XeCl excimer laser. A silicon layer PSI is formed.
[0038]
Thereafter, a 500-nm-thick protective insulating film L2 made of silicon nitride is formed so as to cover the entirety, and a pixel electrode PX1 made of indium tin oxide (ITO) is formed through a contact through hole provided in the protective insulating film L2. The source / drain electrode SD1 is contacted. This state is shown in part a of FIG.
[0039]
According to this embodiment, the ion implantation and the impurity activation annealing can be omitted, so that the throughput is improved. Further, since the processing of the source / drain electrode SD1 and the processing of the interlayer insulating film INT are performed using the same mask (resist RES), a photoetching step is not added, and a low-cost image display device can be obtained. Further, since the interlayer insulating film INT is provided between the gate line G0 and the signal line SD0, parasitic capacitance can be reduced, and high-speed writing of image signals and enlargement of a screen can be realized.
[0040]
According to the present embodiment, since the polysilicon layer PSI in contact with the interlayer insulating film INT plays a role of an offset, the off current can be reduced.
[0041]
As shown in FIG. 8, the high-concentration n-type amorphous silicon layer HDA overlaps the gate electrode G1 on both the source side and the drain side in order to suppress the occurrence of light leakage current due to the backlight 204, The width W1 of the polysilicon film forming the region and the offset region needs to be shorter than the width W2 of the gate electrode (W1 <W2).
[0042]
(Example 2)
FIG. 15 shows a second embodiment of the present invention, which corresponds to a cross-sectional view taken along the line AA ′ in FIG. 7, and shows a configuration after the pixel electrode PX1 is formed. That is, FIG. 15 shows a structure in which the gate insulating film GI in the first embodiment is a stacked film of the silicon nitride film GI2 and the silicon oxide film GI1.
[0043]
According to this embodiment, it is possible to improve the performance of the TFT by using silicon nitride having a higher dielectric constant than silicon oxide for the gate insulating film. In addition, the silicon oxide film GI1 plays a role of preventing the gate insulating film from being etched when etching the interlayer insulating film INT and a role of reducing the interface state between the polysilicon layer PSI and the gate insulating film. I have.
[0044]
(Example 3)
FIG. 16 shows a third embodiment of the present invention, which corresponds to a cross-sectional view taken along the line AA ′ in FIG. 7, and shows a configuration after the pixel electrode PX1 is formed. That is, FIG. 16 shows a structure in which the gate insulating film GI in the second embodiment is a laminated film of the anodic oxide film GI3 (the aluminum oxide film in this embodiment) of the gate electrode and the silicon oxide film GI1.
[0045]
According to this embodiment, the process can be simplified because the gate insulating film is formed by anodic oxidation. Further, since aluminum oxide having a high dielectric constant is used in combination as the gate insulating film, the performance of the TFT can be improved as compared with the case where the silicon oxide film is used alone.
[0046]
(Example 4)
A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 17 is a circuit block diagram of the image display device of the present invention. In this embodiment, the gate driver circuit 102 is configured by a TFT, and a configuration diagram of a bootstrap circuit which is a part of the gate driver circuit is shown in FIG. The plan layout diagram of the pixel 100 is the same as FIG. A cross-sectional view taken along line AA ′ in FIG. 7 is the same as FIG. A cross-sectional view taken along line BB 'in FIG. 7 is the same as FIG.
[0047]
FIG. 18 shows a plan layout diagram of the bootstrap circuit 106. FIG. 19 is a cross-sectional view taken along the line CC ′ in FIG. 18 and shows the configuration after the pixel electrode PX1 is formed. In the first embodiment, after the interlayer insulating film INT is formed, a contact region is opened by a well-known photo-etching process, and thereafter, the high-concentration n-type amorphous silicon layer HDA and the source / drain electrode SD1 are formed to form the structure shown in FIG. Get.
[0048]
According to the present embodiment, a part of the peripheral driving circuit for driving the pixel portion is formed on the same substrate as the pixel portion and is made of the same polysilicon TFT as that of the pixel portion. The number of connection terminals can be reduced, and a high-definition image can be displayed. Further, since the number of LSIs constituting the peripheral drive circuit can be reduced, the cost of the image display device can be reduced.
[0049]
(Example 5)
A fifth embodiment of the present invention will be described with reference to FIGS. The configuration diagram of the image display device in the present embodiment is the same as FIG. FIG. 20 is a plan layout diagram of the pixel 100. FIG. 21 is a plan layout diagram of a bootstrap circuit 106 which is a part of the gate driver circuit 102. FIG. 22 is a cross-sectional view taken along the line DD ′ in FIG. 20, and FIG. 23 is a cross-sectional view taken along the line EE ′ in FIG. 21, showing the configuration after the pixel electrode PX1 is formed.
[0050]
In the TFT constituting the gate driver circuit 102 shown in FIG. 23, after the interlayer insulating film INT is formed in the first embodiment, the interlayer insulating film above the gate electrode is removed by a well-known photo-etching process, and then the high-concentration n-type An amorphous silicon layer HDA and a source / drain electrode SD1 are formed. At this time, in order to improve the circuit performance, the overlap length OFF2 between the gate electrode G1 of the TFT constituting the circuit shown in FIG. 23 and the high-concentration impurity amorphous silicon layer HDA is determined by the TFT constituting the pixel shown in FIG. It is desirable that the overlap length OFF1 between the gate electrode G1 and the high-concentration impurity amorphous silicon layer HDA is shorter than the overlap length OFF1. That is, the relationship of OFF1 (the overlap length between G1 and HDA in the TFT of the pixel)> OFF2 (the overlap length between G1 and HDA in the TFT of the gate driver circuit) is desirable.
[0051]
FIG. 24 is a cross-sectional view of the gate driver circuit 102 taken along line FF ′ in FIG. 21 and shows the configuration after the pixel electrode PX1 is formed. A capacitance is formed by the gate electrode G1 and the source / drain electrode SD1.
[0052]
According to the present embodiment, as shown in FIG. 23, since the TFT constituting the gate driver circuit 102 does not have an offset region, the on-state current of the TFT can be increased, and the performance of the circuit can be improved.
[0053]
(Example 6)
A sixth embodiment of the present invention will be described with reference to FIGS. The configuration diagram of the image display device in the present embodiment is the same as FIG. However, the structure of the channel region of the TFT forming the pixel shown in FIG. 1 of the first embodiment is different in the present embodiment as will be described later with reference to FIG.
[0054]
FIG. 25 is a plan layout diagram of the pixel 100. FIG. 26 is a cross-sectional view taken along the line GG ′ in FIG. 25, and shows the configuration after the pixel electrode PX1 is formed. The method of manufacturing the TFT shown in FIG. 26 will be described with reference to the cross-sectional process diagrams shown in FIGS.
[0055]
First, as shown in FIG. 27, a buffer layer L1 and a gate electrode G1 are formed on a glass substrate SUB, similarly to FIG. 10 described in the first embodiment.
[0056]
Next, as shown in FIG. 28, a gate insulating film GI and an interlayer insulating film INT are formed by plasma CVD, a high-concentration n-type polysilicon layer HDN is formed by catalytic CVD, and source / drain electrodes SD1 are formed by sputtering. A five-layer metal film M1 of Ti-TiW-Al-TiW-Ti is formed. The difference from this embodiment in this step is that the high-concentration n-type amorphous silicon layer HDA is formed by the plasma CVD method in the first embodiment, but the high-concentration n-type polysilicon layer HDN is formed by the catalytic CVD method in this embodiment. did.
[0057]
Thereafter, as shown in FIG. 29, the channel region is patterned by a well-known photo-etching process, and the five-layer metal film is selectively removed. At this time, the five-layer metal film below the resist RES is also removed by side etching. This manufacturing process is almost the same as FIG. 12 of the first embodiment, but the amount of side etching of the five-layer metal film M1 is slightly shallower than that of the first embodiment as shown in FIG.
[0058]
Next, as shown in FIG. 30, the high-concentration n-type polysilicon layer HDN and the interlayer insulating film INT are etched by anisotropic etching (here, known dry etching).
[0059]
Next, as shown in FIG. 31, after removing the resist, a polysilicon layer is deposited to a thickness of 100 nm by the catalytic CVD method, and an island-shaped polysilicon layer PSI is formed by a known photoetching process. In the first embodiment, amorphous silicon is formed by plasma CVD, and then polysilicon is formed by laser annealing. However, since the polysilicon layer is directly formed by catalytic CVD, laser annealing is not necessary and the process is performed. Is simplified.
[0060]
Thereafter, a 500-nm-thick protective insulating film L2 made of silicon nitride is formed so as to cover the whole, and the pixel electrode PX1 and the source / drain electrode SD1 are contacted via a contact through hole provided in the protective insulating film L2. Thus, a TFT constituting a pixel having the structure shown in FIG. 26 is obtained.
[0061]
According to the present embodiment, as shown in FIG. 30, since the interlayer insulating film INT is processed by dry etching, variations in channel length can be reduced. Further, since the offset length can be controlled by the thickness of the interlayer insulating film, variations in the offset length can be reduced, and the uniformity of TFT performance can be improved. In this case, the interval T1 between the projection point on the gate insulating film GI at the end of the interlayer insulating film INT in contact with the high-concentration n-type polysilicon layer HDN and the end of the interlayer insulating film INT in contact with the gate insulating film GI is It is desirable that the thickness of the interlayer insulating film INT be equal to or less than T2 (T1> T2).
[0062]
(Example 7)
A seventh embodiment of the present invention will be described with reference to FIGS.
FIG. 32 is a configuration diagram of the image display device. In this embodiment, the gate driver circuit 102 is constituted by TFTs formed on the same substrate as the pixel portion, and a configuration diagram of a CMOS 107 which is a part of the gate driver circuit is shown in FIG.
[0063]
FIG. 33 is a plan layout diagram of the pixel 100 shown in FIG. A cross-sectional view taken along line HH ′ in FIG. 33 is similar to FIG.
[0064]
FIG. 34 is a plan layout diagram of the CMOS 107 in the gate driver circuit 102 of FIG.
[0065]
FIG. 35 is a cross-sectional view taken along the line JJ ′ in FIG. 34, and shows the configuration after the pixel electrode PX1 is formed. A method of manufacturing the TFT shown in FIG. 35 will be described with reference to the cross-sectional process diagrams shown in FIGS.
[0066]
First, as shown in FIG. 36, similarly to the sixth embodiment, a buffer layer L1 and a gate electrode G1 are formed on a glass substrate SUB, and a gate insulating film GI, an interlayer insulating film INT, and a high-concentration n-type polysilicon layer HDN are formed. , A five-layered metal film M1 (which becomes the source / drain electrode SD1) of Ti-TiW-Al-TiW-Ti is sequentially formed. Further, two types of channel regions (p-channel / n-channel) for CMOS are patterned by a well-known photo-etching process, and a five-layer metal film is side-etched, and then anisotropically-etched (known-dry etching). Then, the high-concentration n-type polysilicon layer HDN and the interlayer insulating film INT are etched.
[0067]
Thereafter, as shown in FIG. 37, a mask insulating film L4 is formed in a region excluding the p-channel TFT (the n-channel region on the right side in this drawing), and high-concentration is performed using the mask insulating film L4 and the source / drain electrode SD1 as a mask. The n-type polysilicon layer and the interlayer insulating film are removed.
[0068]
Next, as shown in FIG. 38, a high-concentration p-type polysilicon layer HDP is formed by a catalytic CVD method, and as shown in FIG. The high-concentration p-type polysilicon layer to be removed is removed.
[0069]
Thereafter, as shown in FIG. 40, the mask insulating film L4 is removed. Subsequently, as shown in FIG. 41, a polysilicon layer PSI is deposited to a thickness of 100 nm by a catalytic CVD method. Form a layer PSI. Thus, a CMOS having the structure shown in FIG. 35 is formed.
[0070]
In the present embodiment, since the circuit is configured using CMOS, the peripheral driver circuit can be reduced in size and power consumption.
[0071]
(Example 8)
FIG. 42 is a configuration diagram of an image display device according to an eighth embodiment of the present invention. FIG. 43 is a plan layout diagram of the pixel 100 in FIG. The storage capacitor 104 includes a common electrode C1 and a source / drain electrode SD1, and the liquid crystal capacitor 105 includes a pixel electrode PX1 and a source / drain electrode SD1. Further, the pixel electrode PX1, the common electrode C1, and the common line C0 are all formed in the same layer.
[0072]
According to the present embodiment, since the liquid crystal is driven by the lateral electric field between the pixel electrode PX1 formed on the TFT substrate and the source / drain electrode SD1, the color change due to the birefringence of the liquid crystal can be suppressed. The viewing angle of the display device can be increased.
[0073]
(Example 9)
The configuration of the image display device according to the ninth embodiment of the present invention is the same as that of FIG.
FIG. 44 shows a plan layout diagram of the pixel 100. The storage capacitor 104 includes a common electrode C1 and a pixel electrode PX1, and the liquid crystal capacitor 105 includes a pixel electrode PX1 and a counter electrode PX2.
[0074]
The pixel electrode PX1 formed on the TFT substrate and the counter electrode PX2 formed on the counter substrate are each patterned, and a protruding electrode is formed on the substrate. With this electrode, the liquid crystal molecule alignment direction when voltage is applied is obliquely controlled.
[0075]
According to the present embodiment, a protruding electrode is formed on a substrate, and the direction in which liquid crystal molecules are obliquely aligned when a voltage is applied is controlled so as to be plural directions in one pixel. It is possible to widen the viewing angle of the device.
[0076]
In the image display devices described in the first to ninth embodiments, the substrate SUB is not necessarily a glass substrate, but may be another insulating substrate such as plastic.
[0077]
As the buffer layer L1, a silicon nitride film or a stacked film of a silicon oxide film and a silicon nitride film may be used instead of the silicon oxide film. If a silicon nitride film is used as a buffer layer, it is possible to effectively prevent impurities in the glass substrate SUB from diffusing into the gate insulating film GI.
[0078]
The material of the gate electrode G1 is not limited to Al but may be a known electrode material such as Ti or Ta. The interlayer insulating film INT may be a silicon oxide film, a laminated film of a silicon oxide film and a silicon nitride film, or another known low dielectric constant material.
[0079]
In the image display device according to the second embodiment, the material of the gate insulating film GI2 is Al. 2 O 3 , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , ZrO 2 , LaAlO 3 , ZrTiO 4 , HfO 2 , SrZrO 3 , TiO 2 , SrTiO 3 , SrBi 2 Ta 2 O 9 , (Ba x Sr 1-x ) TiO 3 , Pb (Zr y Ti 1-y ) O 3 Or other well-known high dielectric constant materials.
[0080]
In the image display device according to the third embodiment, the material of the gate electrode G1 is a well-known electrode material whose oxide film is a high dielectric constant material such as Ti, Zr, Hf, Ta, Nb or an alloy thereof. Is also good. Further, the method of oxidation is not limited to anodic oxidation, but may be oxygen plasma treatment.
[0081]
In the image display devices described in the eighth and ninth embodiments, the sectional structure of the pixel TFT 103 may be any of the first to third embodiments and the sixth embodiment. Further, the cross-sectional structure of the TFT constituting the gate driver circuit 102 may be any of those described in the fourth, fifth, and seventh embodiments. As the holding electrode, a part of the previous gate line G0 can be used instead of the common electrode C1.
[0082]
The present invention can be applied not only to a display device using liquid crystal but also to an image display device using electroluminescence.
[0083]
【The invention's effect】
As described in detail above, according to the present invention, the capacitance at the intersection of the gate line and the signal line is reduced, and an image display device with low manufacturing cost is obtained. The intended purpose of realizing each device can be achieved.
[0084]
That is, the present invention provides an image display device in which the manufacturing cost can be reduced by using a bottom gate type TFT and the interlayer capacitance is reduced by forming an interlayer insulating film between a gate line and a signal line. it can.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a thin film transistor according to a first embodiment.
FIG. 2 is a sectional view showing an example of a manufacturing process of a conventional polysilicon thin film transistor.
FIG. 3 is a cross-sectional view showing an example of a manufacturing process of a conventional polysilicon thin film transistor.
FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a conventional polysilicon thin film transistor.
FIG. 5 is a cross-sectional view of a conventional amorphous silicon thin film transistor and an intersection of a gate line and a signal line.
FIG. 6 is a configuration diagram of a liquid crystal display device according to the present invention.
FIG. 7 is a plan layout view of a pixel in the liquid crystal display device according to the present invention.
FIG. 8 is a sectional view taken along the line AA ′ in FIG. 7;
FIG. 9 is a sectional view taken along the line BB ′ in FIG. 7;
FIG. 10 is a sectional view showing the manufacturing process of the first embodiment.
FIG. 11 is a sectional view showing the manufacturing process of the first embodiment.
FIG. 12 is a sectional view showing the manufacturing process of the first embodiment.
FIG. 13 is a sectional view showing the manufacturing process of the first embodiment.
FIG. 14 is a sectional view showing the manufacturing process of the first embodiment.
FIG. 15 is a cross-sectional view of a thin-film transistor of Example 2.
FIG. 16 is a cross-sectional view of a thin film transistor according to a third embodiment.
FIG. 17 is a configuration diagram of a liquid crystal display device according to a fourth embodiment and a fifth embodiment.
FIG. 18 is a plan layout diagram of a bootstrap circuit in the liquid crystal display device according to the fourth embodiment.
FIG. 19 is a cross-sectional view of a thin film transistor according to a fourth embodiment.
FIG. 20 is a plan layout view of a pixel in a liquid crystal display device of Example 5.
FIG. 21 is a plan layout diagram of a bootstrap circuit in the liquid crystal display device according to the fifth embodiment.
FIG. 22 is a cross-sectional view of a thin film transistor forming a pixel in a liquid crystal display device of Example 5.
FIG. 23 is a cross-sectional view of a thin film transistor included in a peripheral driver circuit in a liquid crystal display device of Embodiment 5.
FIG. 24 is a cross-sectional view of a capacitive element included in a peripheral driving circuit in a liquid crystal display device according to a fifth embodiment.
FIG. 25 is a plan layout view of a pixel in a liquid crystal display device of Example 6.
FIG. 26 is a cross-sectional view of a thin film transistor of Example 6.
FIG. 27 is a sectional view showing the manufacturing process of the sixth embodiment.
FIG. 28 is a sectional view showing the manufacturing process of the sixth embodiment.
FIG. 29 is a cross-sectional view showing the manufacturing process of the sixth embodiment.
FIG. 30 is a sectional view showing the manufacturing process of the sixth embodiment.
FIG. 31 is a cross-sectional view showing a manufacturing step of the sixth embodiment.
FIG. 32 is a configuration diagram of a liquid crystal display device according to a seventh embodiment.
FIG. 33 is a plan layout view of a pixel in a liquid crystal display device of Example 7;
FIG. 34 is a planar layout diagram of a CMOS in the liquid crystal display device of Example 7.
FIG. 35 is a cross-sectional view of a thin film transistor forming a CMOS in the liquid crystal display device of Example 7.
FIG. 36 is a sectional view showing the manufacturing process of the seventh embodiment.
FIG. 37 is a sectional view showing the manufacturing process of the seventh embodiment.
FIG. 38 is a sectional view showing the manufacturing process of the seventh embodiment.
FIG. 39 is a sectional view showing the manufacturing process of the seventh embodiment.
FIG. 40 is a sectional view showing the manufacturing process of the seventh embodiment.
FIG. 41 is a sectional view showing the manufacturing process of the seventh embodiment.
FIG. 42 is a configuration diagram of a liquid crystal display device according to an eighth embodiment.
FIG. 43 is a plan layout view of a pixel in a liquid crystal display device of Example 8.
FIG. 44 is a plan layout view of a pixel in the liquid crystal display device of Example 9;
[Explanation of symbols]
SUB: glass substrate, PSI: polysilicon film, ASI: amorphous silicon film, L1: buffer layer, L2: protective insulating film, L3: channel etching preventing film, L4: mask insulating film, G0: gate line, G1: gate electrode , SD0: signal line, SD1: source / drain electrode, C0: common line, C1: common electrode, GI: gate insulating film, GI1: silicon oxide film, GI2: silicon nitride film, GI3: anodic oxide film of gate electrode, INT: interlayer insulating film, HDA: high-concentration n-type amorphous silicon layer, HDN: high-concentration n-type polysilicon layer, LDN: low-concentration n-type polysilicon layer, HDP: high-concentration p-type polysilicon layer, M1: 5 layers Metal film, PX1: pixel electrode, PX2: counter electrode, RES: resist, CF: color filter, BM: black matrix, 1 0: pixel, 101: drain driver circuit, 102: gate driver circuit, 103: pixel TFT, 104: storage capacitor, 105: liquid crystal capacitor, 106: bootstrap circuit, 107: CMOS, 200: liquid crystal layer, 201: alignment film Reference numeral 202 denotes a protective insulating film, 203 denotes a polarizing plate, 204 denotes a backlight.

Claims (14)

基板上に複数の薄膜トランジスタを有する画像表示装置であって、前記基板上に、複数のゲート線と、前記ゲート線にマトリクス状に交差する複数の信号線とを有し、前記薄膜トランジスタはボトムゲート型であり、チャネル領域は基板側から、ゲート電極／ゲート絶縁膜／多結晶シリコン膜が順次積層された積層構造を有し、ソース電極及びドレイン電極部は基板側から、ゲート絶縁膜／層間絶縁膜／非単結晶シリコン膜／金属膜が順次積層された積層構造を有しており、前記多結晶シリコン膜は前記ゲート絶縁膜及び前記層間絶縁膜及び前記非単結晶シリコン膜にそれぞれ接して形成されており、前記信号線と前記ゲート線との交差部において、前記ゲート絶縁膜と前記層間絶縁膜との積層絶縁膜を有することを特徴とする画像表示装置。An image display device including a plurality of thin film transistors on a substrate, the image display device including a plurality of gate lines and a plurality of signal lines intersecting the gate lines in a matrix on the substrate, wherein the thin film transistor is a bottom gate type. The channel region has a laminated structure in which a gate electrode / gate insulating film / polycrystalline silicon film is sequentially laminated from the substrate side, and the source electrode and the drain electrode portion are a gate insulating film / interlayer insulating film from the substrate side. / A non-single-crystal silicon film / a metal film is sequentially laminated, and the polycrystalline silicon film is formed in contact with the gate insulating film, the interlayer insulating film, and the non-single-crystal silicon film, respectively. An image display device having a laminated insulating film of the gate insulating film and the interlayer insulating film at an intersection of the signal line and the gate line. 前記金属膜は、前記非単結晶シリコン膜に対し、自己整合的に縮小加工されていることを特徴とする請求項１に記載の画像表示装置。The image display device according to claim 1, wherein the metal film is reduced in a self-aligned manner with respect to the non-single-crystal silicon film. 前記ゲート電極上部の前記層間絶縁膜はテーパ状に加工されており、前記非単結晶シリコン膜と接する層間絶縁膜の端部のゲート絶縁膜上の投影点と、ゲート絶縁膜と接する層間絶縁膜の端部との間隔をＴ１とし、前記層間絶縁膜の膜厚をＴ２としたとき、これら両者の関係をＴ１＞Ｔ２としたことを特徴とする請求項１に記載の画像表示装置。The interlayer insulating film on the gate electrode is tapered, and a projection point on the gate insulating film at an end of the interlayer insulating film in contact with the non-single-crystal silicon film, and an interlayer insulating film in contact with the gate insulating film 2. The image display device according to claim 1, wherein the relationship between the two is T1> T2, where T1 is the distance from the end of the substrate and T2 is the thickness of the interlayer insulating film. 前記ゲート電極上部の前記層間絶縁膜はテーパ状に加工されており、前記非単結晶シリコン膜と接する層間絶縁膜の端部のゲート絶縁膜上の投影点と、ゲート絶縁膜と接する層間絶縁膜の端部との間隔をＴ１とし、前記層間絶縁膜の膜厚をＴ２としたとき、これら両者の関係をＴ１≦Ｔ２としたことを特徴とする請求項１に記載の画像表示装置。The interlayer insulating film on the gate electrode is tapered, a projection point on the gate insulating film at an end of the interlayer insulating film in contact with the non-single-crystal silicon film, and an interlayer insulating film in contact with the gate insulating film. 2. The image display device according to claim 1, wherein the relationship between the two is T1 ≦ T2, where T1 is the distance from the end of the substrate and T2 is the thickness of the interlayer insulating film. 前記ゲート絶縁膜は、高誘電率膜と酸化シリコン膜との積層膜であることを特徴とする請求項１に記載の画像表示装置。The image display device according to claim 1, wherein the gate insulating film is a laminated film of a high dielectric constant film and a silicon oxide film. 前記ゲート絶縁膜は前記ゲート電極の酸化膜と酸化シリコン膜との積層膜であることを特徴とする請求項１に記載の画像表示装置。The image display device according to claim 1, wherein the gate insulating film is a laminated film of an oxide film and a silicon oxide film of the gate electrode. 前記ゲート絶縁膜及び前記層間絶縁膜に接する多結晶シリコン膜の幅をＷ１とし、ゲート電極の幅をＷ２としたとき、これら両者の関係をＷ１＜Ｗ２としたことを特徴とする請求項１に記載の画像表示装置。2. The relation between the width of the polycrystalline silicon film in contact with the gate insulating film and the interlayer insulating film is W1, and the width of the gate electrode is W2, the relationship between the two is W1 <W2. The image display device as described in the above. 一対の絶縁性基板と、これらに挟まれた液晶層を有する液晶表示装置であって、前記液晶表示装置は複数の薄膜トランジスタを有しており、前記薄膜トランジスタは前記ソース電極及びドレイン電極と、絶縁膜を介して前記ソース電極及びドレイン電極上部に形成された画素電極を有しており、前記ソース電極及びドレイン電極と前記画素電極との間に電圧を印加することにより、基板に対し平行な横方向電界を発生させ、前記横方向電界により液晶の配向を制御することを特徴とする請求項１乃至７のいずれか一つに記載の画像表示装置。A liquid crystal display device having a pair of insulating substrates and a liquid crystal layer sandwiched therebetween, wherein the liquid crystal display device has a plurality of thin film transistors, and the thin film transistors have the source and drain electrodes and an insulating film. And a pixel electrode formed above the source electrode and the drain electrode through, and by applying a voltage between the source electrode and the drain electrode and the pixel electrode, a horizontal direction parallel to the substrate is provided. The image display device according to claim 1, wherein an electric field is generated, and alignment of the liquid crystal is controlled by the lateral electric field. 基板上に薄膜トランジスタで構成された複数のＣＭＯＳを有する画像表示装置であって、前記薄膜トランジスタはボトムゲート型であり、チャネル領域は基板側から、ゲート電極／ゲート絶縁膜／多結晶シリコン膜が順次積層された積層構造を有し、ソース電極及びドレイン電極部は基板側から、ゲート絶縁膜／層間絶縁膜／非単結晶シリコン膜／金属膜が順次積層された積層構造を有しており、ｎ型薄膜トランジスタは、前記非単結晶シリコン膜がｎ型導電性を有し、前記多結晶シリコン膜はゲート絶縁膜及び層間絶縁膜及びｎ型非単結晶シリコン膜に接して形成されており、ｐ型薄膜トランジスタは、前記層間絶縁膜の側面部及び前記金属膜の側面部に接してｐ型非単結晶シリコン膜が形成されており、前記多結晶シリコン膜はゲート絶縁膜及び前記ｐ型非単結晶シリコン膜に接して形成されていることを特徴とする画像表示装置。What is claimed is: 1. An image display device having a plurality of CMOSs formed of thin film transistors on a substrate, wherein the thin film transistors are of a bottom gate type, and a channel region is formed by sequentially stacking a gate electrode / gate insulating film / polycrystalline silicon film from the substrate side. The source and drain electrode portions have a stacked structure in which a gate insulating film / interlayer insulating film / non-single-crystal silicon film / metal film are sequentially stacked from the substrate side, and are n-type. In the thin film transistor, the non-single-crystal silicon film has n-type conductivity, and the polycrystalline silicon film is formed in contact with the gate insulating film, the interlayer insulating film, and the n-type non-single-crystal silicon film, and the p-type thin film transistor A p-type non-single-crystal silicon film is formed in contact with a side surface of the interlayer insulating film and a side surface of the metal film, and the polycrystalline silicon film has a gate insulation. The image display apparatus characterized by being formed in contact with the film and the p-type non-single crystal silicon film. 基板上に、ゲート電極を形成する工程と、前記ゲート電極上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に層間絶縁膜を形成する工程と、前記層間絶縁膜上に非単結晶シリコン膜を形成する工程と、前記非単結晶シリコン膜上に金属膜を形成する工程と、レジストをマスクにして前記金属膜を加工し、さらにサイドエッチングにより、レジストに対し前記金属膜を縮小加工し、ソース電極及びドレイン電極を形成する工程と、前記同レジストをマスクにして、前記非単結晶シリコン膜及び前記層間絶縁膜をエッチングする工程と、前記ゲート絶縁膜及び前記層間絶縁膜及び前記非単結晶シリコン膜に接して多結晶シリコン膜を形成する工程とを含むことを特徴とする画像表示装置の製造方法。Forming a gate electrode on the substrate, forming a gate insulating film on the gate electrode, forming an interlayer insulating film on the gate insulating film, and forming a non-single crystal on the interlayer insulating film Forming a silicon film, forming a metal film on the non-single-crystal silicon film, processing the metal film using a resist as a mask, and further reducing the metal film on the resist by side etching. Forming a source electrode and a drain electrode; etching the non-single-crystal silicon film and the interlayer insulating film using the resist as a mask; and forming the gate insulating film, the interlayer insulating film, and the Forming a polycrystalline silicon film in contact with the single crystal silicon film. 前記多結晶シリコン膜を形成する工程は、プラズマＣＶＤ法で成膜するアモルファスシリコン膜の形成工程と、前記アモルファスシリコン膜をアニールして多結晶化する工程とを含むことを特徴とする請求項１０に記載の画像表示装置の製造方法。11. The method according to claim 10, wherein the step of forming the polycrystalline silicon film includes a step of forming an amorphous silicon film formed by a plasma CVD method, and a step of annealing the amorphous silicon film to make it polycrystalline. 3. The method for manufacturing an image display device according to item 1. 前記多結晶シリコン膜を形成する工程を触媒ＣＶＤ法により形成する工程としたことを特徴とする請求項１０に記載の画像表示装置の製造方法。11. The method according to claim 10, wherein the step of forming the polycrystalline silicon film is a step of forming by a catalytic CVD method. 前記非単結晶シリコン膜を形成する工程を触媒ＣＶＤ法により形成する工程とし、多結晶シリコンを含む膜を形成することを特徴とする請求項１０に記載の画像表示装置の製造方法。11. The method according to claim 10, wherein the step of forming the non-single-crystal silicon film is a step of forming the film by a catalytic CVD method, and forming a film containing polycrystalline silicon. 前記非単結晶シリコン膜を形成する工程をプラズマＣＶＤ法により形成する工程とし、アモルファスシリコンを含む膜を形成することを特徴とする請求項１０に記載の画像表示装置の製造方法。The method according to claim 10, wherein the step of forming the non-single-crystal silicon film is a step of forming by a plasma CVD method, and a film containing amorphous silicon is formed.
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008015525A (en) * 2006-06-30 2008-01-24 Lg Phillips Lcd Co Ltd Array substrate for liquid crystal display device and method of fabricating the same
EP2216816A2 (en) * 2009-02-09 2010-08-11 Hitachi Displays, Ltd. Display device
JP2010256556A (en) * 2009-04-23 2010-11-11 Hitachi Displays Ltd Image display apparatus and method of manufacturing the same
KR20100127593A (en) * 2009-05-26 2010-12-06 엘지디스플레이 주식회사 Oxide thin film transistor and method of fabricating the same
CN102237412A (en) * 2010-04-22 2011-11-09 株式会社日立显示器 Image display device and manufacturing method thereof
US8114720B2 (en) 2008-12-25 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR20140013522A (en) * 2012-07-24 2014-02-05 엘지디스플레이 주식회사 Thin film transistor, liquid crystal display device and method of fabricating thereof
JP2015056549A (en) * 2013-09-12 2015-03-23 三菱電機株式会社 Thin film transistor and manufacturing method of the same
JP2015119199A (en) * 2009-10-16 2015-06-25 株式会社半導体エネルギー研究所 Semiconductor device
EP2991121A4 (en) * 2013-03-25 2017-02-08 Boe Technology Group Co. Ltd. Array substrate, method for manufacturing array substrate and display device
KR101792997B1 (en) * 2008-11-07 2017-11-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
JP2018049297A (en) * 2009-03-27 2018-03-29 株式会社半導体エネルギー研究所 Semiconductor device
JP2022104922A (en) * 2007-07-26 2022-07-12 株式会社半導体エネルギー研究所 Liquid crystal display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224258A (en) * 1987-03-12 1988-09-19 Mitsubishi Electric Corp Thin film transistor
JPH08236775A (en) * 1995-03-01 1996-09-13 Toshiba Corp Film transistor, and its manufacture
JPH08340122A (en) * 1996-06-07 1996-12-24 Semiconductor Energy Lab Co Ltd Thin film semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224258A (en) * 1987-03-12 1988-09-19 Mitsubishi Electric Corp Thin film transistor
JPH08236775A (en) * 1995-03-01 1996-09-13 Toshiba Corp Film transistor, and its manufacture
JPH08340122A (en) * 1996-06-07 1996-12-24 Semiconductor Energy Lab Co Ltd Thin film semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US8258022B2 (en) 2006-06-30 2012-09-04 Lg Display Co., Ltd. Array substrate for liquid crystal display device and method of fabricating the same
JP2008015525A (en) * 2006-06-30 2008-01-24 Lg Phillips Lcd Co Ltd Array substrate for liquid crystal display device and method of fabricating the same
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JP7166319B2 (en) 2008-11-07 2022-11-07 株式会社半導体エネルギー研究所 Display device
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US11158654B2 (en) 2008-12-25 2021-10-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
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US10720451B2 (en) 2008-12-25 2020-07-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
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KR101831162B1 (en) * 2008-12-25 2018-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and manufacturing method thereof
US9768280B2 (en) 2008-12-25 2017-09-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
EP2216816A3 (en) * 2009-02-09 2011-09-28 Hitachi Displays, Ltd. Display device
EP2216816A2 (en) * 2009-02-09 2010-08-11 Hitachi Displays, Ltd. Display device
KR101138624B1 (en) * 2009-02-09 2012-05-16 파나소닉 액정 디스플레이 주식회사 Display device
JP2010206154A (en) * 2009-02-09 2010-09-16 Hitachi Displays Ltd Display device
US8309960B2 (en) 2009-02-09 2012-11-13 Hitachi Displays, Ltd. Display device
US11127858B2 (en) 2009-03-27 2021-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10297693B1 (en) 2009-03-27 2019-05-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11916150B2 (en) 2009-03-27 2024-02-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10714630B2 (en) 2009-03-27 2020-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11575049B2 (en) 2009-03-27 2023-02-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2018049297A (en) * 2009-03-27 2018-03-29 株式会社半導体エネルギー研究所 Semiconductor device
JP2010256556A (en) * 2009-04-23 2010-11-11 Hitachi Displays Ltd Image display apparatus and method of manufacturing the same
KR20100127593A (en) * 2009-05-26 2010-12-06 엘지디스플레이 주식회사 Oxide thin film transistor and method of fabricating the same
KR101640812B1 (en) * 2009-05-26 2016-08-01 엘지디스플레이 주식회사 Method of fabricating oxide thin film transistor
US11837461B2 (en) 2009-10-16 2023-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10074747B2 (en) 2009-10-16 2018-09-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10777682B2 (en) 2009-10-16 2020-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2015119199A (en) * 2009-10-16 2015-06-25 株式会社半導体エネルギー研究所 Semiconductor device
US9666678B2 (en) 2009-10-16 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN102237412A (en) * 2010-04-22 2011-11-09 株式会社日立显示器 Image display device and manufacturing method thereof
US8436358B2 (en) 2010-04-22 2013-05-07 Hitachi Displays, Ltd. Image display device and manufacturing method thereof
JP2011228560A (en) * 2010-04-22 2011-11-10 Hitachi Displays Ltd Image display device and manufacturing method of the same
KR101980752B1 (en) * 2012-07-24 2019-08-28 엘지디스플레이 주식회사 Thin film transistor, liquid crystal display device and method of fabricating thereof
KR20140013522A (en) * 2012-07-24 2014-02-05 엘지디스플레이 주식회사 Thin film transistor, liquid crystal display device and method of fabricating thereof
EP2991121A4 (en) * 2013-03-25 2017-02-08 Boe Technology Group Co. Ltd. Array substrate, method for manufacturing array substrate and display device
JP2015056549A (en) * 2013-09-12 2015-03-23 三菱電機株式会社 Thin film transistor and manufacturing method of the same

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