KR101980752B1 - Thin film transistor, liquid crystal display device and method of fabricating thereof - Google Patents

Thin film transistor, liquid crystal display device and method of fabricating thereof Download PDF

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KR101980752B1
KR101980752B1 KR1020120080843A KR20120080843A KR101980752B1 KR 101980752 B1 KR101980752 B1 KR 101980752B1 KR 1020120080843 A KR1020120080843 A KR 1020120080843A KR 20120080843 A KR20120080843 A KR 20120080843A KR 101980752 B1 KR101980752 B1 KR 101980752B1
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electrode
drain electrode
source electrode
source
drain
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KR20140013522A (en
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문태형
송태준
이규황
육승현
이경하
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엘지디스플레이 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention relates to a thin film transistor manufacturing method that can simplify the manufacturing process, comprising the steps of providing a substrate; Forming a gate electrode on the substrate; Forming a gate insulating layer on the substrate on which the gate electrode is formed; Forming a source electrode and a drain electrode on the gate insulating layer; And forming a semiconductor layer on the gate insulating layer between the source electrode and the drain electrode.

Description

Thin film transistor, liquid crystal display device and manufacturing method thereof {THIN FILM TRANSISTOR, LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a thin film transistor having a simplified manufacturing process and improved efficiency and a method of manufacturing the same.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in the resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display device is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, is a method of driving the liquid crystal of the pixel part by using a thin film transistor as a switching device.

The liquid crystal display device is formed by a photo process using a photomask and a photoresist, and a method of manufacturing a conventional liquid crystal display device using the photo process will be described.

1A to 1G illustrate a method of manufacturing a conventional liquid crystal display device. Although the liquid crystal display is substantially composed of a plurality of pixels, only one pixel will be described below for convenience of description.

First, as shown in FIG. 1A, a metal is stacked on the first substrate 10 and etched by a first mask to form a gate electrode 21. Subsequently, as shown in FIG. 1B, a gate insulating layer 12 is formed on the first substrate 10 having the gate electrode 21 formed thereon, and a transparent oxide semiconductor material such as indium gallium zinc oxide (IGZO) is stacked thereon. The oxide semiconductor layer 22 is formed by etching with the second mask.

Thereafter, as shown in FIG. 1C, an inorganic insulating material is laminated on the first substrate 1 on which the oxide semiconductor layer 22 is formed, and then etched by a third mask to etch stopper on the oxide semiconductor layer 22. (etch stopper; 23). When the etch stopper 23 etches the metal by the etchant to form a source electrode and a drain electrode thereafter, the etching semiconductor 23 blocks the etchant so that a defect occurs as the oxide semiconductor layer 22 is etched by the etchant. It is to prevent.

Subsequently, as shown in FIG. 1D, a metal is deposited over the entire first substrate 10 and then etched by a fourth mask to form a source electrode on the oxide semiconductor layer 22 and on the gate insulating layer 12. 25 and the drain electrode 26 are formed. At this time, since the etch stopper 23 made of an inorganic insulating material is formed on the oxide semiconductor layer 22, the etching is stopped by the etch stopper 23 when the metal layer is etched by the etchant. It is possible to prevent the oxide semiconductor layer 22 from being etched.

Thereafter, as illustrated in FIG. 1E, an inorganic insulating material or an organic insulating material is stacked on the first substrate 10 to form a protective layer 14, and then etched by a fifth mask to form a drain electrode 26. The contact hole 15 exposing) is formed in the protective layer 14.

Subsequently, as illustrated in FIG. 1F, a transparent conductive material is stacked on the protective layer 14 and the contact hole 15, and is etched by a sixth mask to be electrically connected to the drain electrode 26. 18).

Thereafter, as shown in FIG. 1G, the black matrix 42, the color filter layer 44, and the common electrode 46 are formed on the second substrate 40, and then bonded to the first substrate 10 to form the first matrix 10. The liquid crystal layer 30 is formed between the first substrate 10 and the second substrate 40 to complete the liquid crystal display device.

The black matrix 42 prevents light from being transmitted to the image non-display area and deteriorates the image quality, and the color filter layer 44 is formed of R, G, and B color filter layers to realize actual color.

As described above, in the conventional liquid crystal display device manufacturing method, a first mask for forming a gate electrode, a second mask for forming a semiconductor layer, a third mask for forming an etch stopper, a fourth mask for forming a source electrode and a drain electrode, and forming a contact hole A total of six masks, such as a fifth mask for use and a sixth mask for forming pixel electrodes, are required.

In general, a photo process using a mask is performed by applying photoresist, developing, etching, stripping, and cleaning. That is, one photo process is composed of a plurality of complex processes, and thus, each time one photo process is added, a plurality of processes are added and an increase in cost occurs.

In the above-described conventional liquid crystal display device manufacturing method, since six mask processes are required, the manufacturing process becomes very complicated, and as a result, expensive manufacturing cost is required. In addition, since the conventional liquid crystal display device manufacturing method requires six mask processes, a large amount of chemicals, for example, a developer, an etchant, and a stripping agent, are required. The use of such a large amount of chemicals is a major contaminant in the environment. It was causing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object thereof is to provide a method for manufacturing a thin film transistor and a liquid crystal display device which can simplify the manufacturing process and reduce manufacturing costs.

In order to achieve the above object, a thin film transistor according to the present invention comprises a gate electrode formed on a substrate; A gate insulating layer formed on the gate electrode; A source electrode and a drain electrode formed on the gate insulating layer; And a semiconductor layer formed between the gate insulating layer between the source electrode and the drain electrode and on the source electrode drain electrode.

The semiconductor layer includes an oxide semiconductor layer. The source electrode and the drain electrode are formed on the gate insulating layer and formed on the first source electrode and the first drain electrode made of ITO or MoTi, the first source electrode and the first drain electrode, and the second source electrode and the first electrode made of Cu. The first source electrode and the first drain electrode have a larger area than the second source electrode and the second drain electrode, and are partially exposed to the outside. A semiconductor layer is formed on the exposed first source electrode and the first drain electrode to be in ohmic contact with the first source electrode and the first drain electrode.

In addition, the method of manufacturing a thin film transistor includes providing a substrate; Forming a gate electrode on the substrate; Forming a gate insulating layer on the substrate on which the gate electrode is formed; Forming a source electrode and a drain electrode on the gate insulating layer; And forming a semiconductor layer on the gate insulating layer between the source electrode and the drain electrode.

The forming of the source electrode and the drain electrode may include forming a conductive layer made of ITO or MoTi and a metal layer made of Cu on the gate insulating layer; Forming a photoresist layer on the metal layer; Forming a first photoresist pattern having a different thickness from each other by using a halftone mask; Etching the conductive layer and the metal layer together using the first photoresist pattern; Acing the first photoresist pattern to form a second photoresist pattern exposing a portion of the metal layer; And etching the exposed metal layer using the second photoresist pattern to expose the first source electrode and the first drain electrode, and the second source electrode and the second drain formed on the first source electrode and the first drain electrode. Forming an electrode.

In the present invention, a first mask for forming a gate electrode, a second mask for forming a source electrode and a drain electrode, a third mask for forming an oxide semiconductor layer, a fourth mask for forming a contact hole of a protective layer, a fifth mask for forming a pixel electrode, and the like. Only five masks are required in total, and the mask for forming an etch stopper is not necessary, so that one mask process is reduced compared to the conventional one, thereby simplifying the overall process and reducing manufacturing costs.

In addition, since the etch stopper is not required, the process margin can be minimized to minimize the length of the channel, thereby minimizing the size of the thin film transistor, and the overlap region between the source electrode, the drain electrode, and the gate electrode It is possible to prevent the increase of the parasitic capacity due to the increase.

1A to 1G illustrate a conventional method for manufacturing a liquid crystal display device.
2 is a cross-sectional view showing a structure of a liquid crystal display device according to an embodiment of the present invention.
3A to 3I illustrate a method of manufacturing a liquid crystal display device according to the present invention.
4 is a view showing a method of manufacturing a liquid crystal display device according to another embodiment of the present invention.
5 is a view showing a method of manufacturing a liquid crystal display device according to another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The present invention simplifies the manufacturing process and reduces the manufacturing cost by eliminating the etch stopper process. The etch stopper is to prevent the lower semiconductor layer from being etched by the etchant and becoming defective when the metal layer is etched when the source electrode and the drain electrode are formed. In the present invention, when the metal layers for forming the source electrode and the drain electrode are etched, a thin film transistor is formed to have a structure in which the etchant does not affect the semiconductor layer, thereby simplifying the manufacturing process by removing the etch stopper from the structure of the thin film transistor.

That is, in the present invention, the semiconductor layer is formed after the source electrode and the drain electrode are formed so that the semiconductor layer is not affected by the source electrode and the drain electrode forming process.

In the present invention, by removing the etch stopper from the structure of the thin film transistor, not only the effect of simplifying the manufacturing process and reducing the manufacturing cost but also reducing the efficiency of the thin film transistor and reducing the parasitic capacity can be obtained.

If an etch stopper is formed, the process margin must be taken into account for the mask process. Therefore, when the actual thin film transistor is designed, the length of the channel of the semiconductor layer is increased by the process margin, and as a result, the size of the thin film transistor is increased and the efficiency of the thin film transistor such as the switching speed of the thin film transistor is decreased. do. In addition, the overlap region between the source electrode, the drain electrode, and the gate electrode is increased, thereby increasing the parasitic capacitance.

However, when the etch stopper is removed as in the present invention, it is not necessary to consider a separate process margin for forming the etch stopper, so that the size increases or the efficiency decreases with the increase in the channel length of the semiconductor layer, the source electrode and the drain. The parasitic capacitance caused by the increase in the overlap region between the electrode and the gate electrode can be prevented from increasing.

2 is a view showing a method of manufacturing a liquid crystal display device according to an embodiment of the present invention. Substantially, in the liquid crystal display device, a plurality of pixels defined by a plurality of gate lines and data lines arranged in a vertical direction are formed, but only one pixel is illustrated in the drawings for convenience of description. In addition, although a twisted nematic (TN) mode liquid crystal display device is disclosed in the drawings, the present invention is not limited to a TN mode liquid crystal display device, but an IPS (In Plane Switching) mode liquid crystal display device or a VA (Vertical Alignment) mode liquid crystal display device. It may be applied to an element or the like.

In addition, the structure of the thin film transistor illustrated in FIG. 2 is not limited to the thin film transistor applied to the liquid crystal display device, but may be applied to the structure of the thin film transistor applied to various display devices such as an organic light emitting display device or an electrophoretic display device. will be.

As shown in FIG. 2, in the liquid crystal display according to the present invention, a thin film transistor is formed in each pixel of the first substrate 110 made of a transparent material such as glass.

The thin film transistor includes a gate electrode 121 formed on the first substrate 110, a gate insulating layer 112 formed on the gate electrode 121, and first and second source electrodes formed on the gate insulating layer 112. Gate insulating layers 125a and 125b and the first and second drain electrodes 126a and 126b and between the first and second source electrodes 125a and 125b and the first and second drain electrodes 126a and 126b. An oxide semiconductor layer 122 is formed on an upper portion and a portion of the first source electrode 125a and the first drain electrode 126a.

The gate insulating layer 112 is formed of an inorganic insulating material such as SiO 2 or SiN 2 . The source electrode and the drain electrode are each formed of a double layer, and the first source electrode 125a and the first drain electrode 126a are formed of an oxide conductive material such as indium tin oxide (ITO) or a molybdenum compound such as MoTi. The second source electrode 125b and the second drain electrode 126b are made of a metal having good conductivity, such as copper (Cu).

In this case, the second source electrode 125b and the second drain electrode 126b are formed to have a smaller size than the first source electrode 125a and the first drain electrode 126a so that the first source electrode 125a and the first drain electrode 126b are smaller. The second source electrode 125b and the second drain electrode 126b are disposed on a portion of the drain electrode 126a, that is, strictly speaking, a portion of the first source electrode 125a and the first drain electrode 126a facing each other. It is not formed and is exposed to the outside.

The oxide semiconductor layer 122 is made of an oxide semiconductor material such as IGZO or ZTO (Zinc Tin Oixde), and the top and the gate insulating layer 112 between the source electrodes 125a and 125b and the drain electrodes 126a and 126b. Formed on a portion of the first source electrode 125a and the first drain electrode 126a to form a channel.

On the first substrate 110 on which the thin film transistor is formed, a protective layer 114 made of an inorganic insulating material such as SiO 2 or SiN 2 , an organic insulating material such as photoacryl or BCB (Benzo Cyclo Butene) is formed, and the protective layer is formed on the first substrate 110. A pixel electrode 118 made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) is formed on the 114, and the thin film transistor is formed through the contact hole 115 formed in the protective layer 114. It is electrically connected to the two drain electrodes 126b.

On the second substrate 140 made of a transparent material such as glass, a black matrix 142 and a color filter layer 144 made of metal or metal oxide such as Cr or CrO 2 are formed.

The black matrix 142 is to prevent light from being transmitted to the image non-display area and to degrade the image quality. The black matrix 142 is disposed in the thin film transistor forming area, the gate line and the data line forming area. The color filter layer 144 is formed of R, G, and B color filter layers to implement actual colors.

Although not shown in the figure, an overcoat layer may be formed on the color filter layer 144 to protect the color filter layer 144 and to improve flatness. The common electrode 146 made of ITO or IZO is formed on the color filter layer 144 or the overcoat layer.

The liquid crystal layer 130 is formed between the first substrate 110 and the second substrate 140 and the first substrate 110 and the second substrate 140 are sealed by a sealant (not shown). The liquid crystal display device is completed.

As described above, in the present invention, a portion of the oxide semiconductor layer 122 is formed on the first source electrode 125a and the first drain electrode 126a. In the conventional oxide thin film transistor, an oxide semiconductor layer 122 is formed below the source electrode and the drain electrode to form the source electrode and the drain electrode after the oxide semiconductor layer is formed. Therefore, in the conventional oxide thin film transistor, since the oxide semiconductor layer is formed and the source electrode and the drain electrode are formed, the etching liquid used in the formation of the source electrode and the drain electrode acts on the already formed oxide semiconductor layer, thereby damaging the oxide semiconductor layer. This happens. Conventionally, an etch stopper is required to prevent the oxide semiconductor layer from being damaged.

On the other hand, in the present invention, since the oxide semiconductor layer 122 is formed after the source electrodes 125a and 125b and the drain electrodes 126a and 126b are formed, the source electrodes 125a and 125b and the drain electrodes 126a and 126b. Since the etching liquid for forming the C) does not act on the oxide semiconductor layer 122, the oxide semiconductor layer 122 is not damaged, and thus a separate etch stopper is not required.

Meanwhile, in the present invention, the source electrode and the drain electrode are each formed of a double layer, wherein the lower first source electrode 125a and the first drain electrode 126a are formed on the upper second source electrode 125b and the second electrode. A portion of the first source electrode 125a and the first drain electrode 126a is exposed to the outside by forming a larger area than the drain electrode 126b, and a portion of the oxide semiconductor layer 122 is exposed to the first source. It is formed on the electrode 125a and the first drain electrode 126a.

As such, forming the oxide semiconductor layer 122 on the exposed first source electrode 125a and the first drain electrode 126a by exposing the first source electrode 125a and the first drain electrode 126a is an oxide. This is to form an ohmic contact between the semiconductor layer 122 and the first source electrode 125a and the first drain electrode 126a.

As mentioned above, in the present invention, the second source electrode 125b and the second drain electrode 126b are formed of copper having high electrical conductivity to improve characteristics of the thin film transistor, and the copper is an oxide such as IGZO or ZTO. In contact with the semiconductor layer, an ohmic contact cannot be formed, and thus a signal cannot move through the channel.

In order to solve such a problem, in the present invention, an oxide semiconductor layer such as IGZO or ZTO, an oxide conductive material such as ITO having good ohmic contact characteristics, or a molybdenum compound such as MoTi is used for the first source electrode 125a and the first drain. An oxide semiconductor layer is brought into contact with the first source electrode 125a and the first drain electrode 126a. At this time, the width x of the first source electrode 125a and the first drain electrode 126a exposed to the outside is formed to be 2 <x <10µm, thereby securing a sufficient ohmic contact area and at the same time the size of the thin film transistor. It is desirable to prevent the increase.

As such, since the second source electrode 125b and the second drain electrode 126b having good electrical mobility are formed on the first source electrode 125a and the first drain electrode 126a, the conductivity and the oxide semiconductor are good. It is possible to form source and drain electrodes having good ohmic contact characteristics with the layer 122.

Hereinafter, a method of manufacturing a liquid crystal display device having the above structure will be described in detail with reference to the accompanying drawings.

3A to 3I are views illustrating a method of manufacturing a liquid crystal display device according to the present invention.

First, as shown in FIG. 3A, a metal such as Al, AlNd, Cu, Mo, Ta, Au, or the like may be sputtered over the entire first substrate 110 made of a transparent material such as glass or plastic. After stacking, the gate electrode 121 is formed by etching using the first mask. In this case, although not shown in the drawing, the gate electrode 121 and the gate line are formed at the same time.

Although not shown in detail in the drawing, in the photo process using the first mask, a photoresist layer is laminated and developed on a metal layer to form a photoresist pattern, and then an etching solution is applied while a part of the metal layer is blocked by the photoresist pattern. As a result, the gate electrode 121 is formed.

Subsequently, as shown in FIG. 3B, a gate insulating layer 112 made of an inorganic insulating material is formed on the entire first substrate 110 by a plasma enhanced chemical vapor deposition (PECVD) method, and sputtering thereon. After the conductive layer 151, such as ITO or MoTi, is formed by a method of forming a metal layer 152 made of a metal having a good conductivity of about 500 GPa or less and a good conductivity such as copper to a thickness of about 2000 GPa or more, the metal layer 152 The photoresist layer 154 is formed thereon.

In this case, various inorganic insulating materials such as SiO 2 and SiN 2 may be used as the gate insulating layer 112, but considering the contact characteristics with the oxide semiconductor layer formed thereafter, the gate insulating layer 112 may be formed of SiO 2 . It is preferable to form.

Thereafter, as shown in FIG. 3C, a halftone mask (not shown) including a light blocking region, a light transmitting region, and a semi-transmissive region partially transmitting light is disposed on the photoresist layer 154. Subsequently, the first photoresist pattern 154a is formed by irradiating light such as ultraviolet rays and applying a developer to act as an etching solution. At this time, since a difference occurs in the amount of light irradiated to the photoresist layer 154 by the halftone mask, the first photoresist pattern 154a is formed of two regions having different thicknesses.

Subsequently, as shown in FIG. 3D, when the etching solution is applied while the conductive layer 151 and the metal layer 152 are blocked with the first photoresist pattern 154a, the conductive layer 151 and the metal layer 152 are actuated. The first source electrode 125a and the first drain electrode 126a are formed at the same time, and the metal layers 152a and 152b having the same area are formed on the first source electrode 125a and the first drain electrode 126a, respectively. Is formed.

Thereafter, as illustrated in FIG. 3E, the first photoresist pattern 154a is ashed to remove photoresist having a thin thickness to expose some regions of the metal layers 152a and 152b. After the second photoresist pattern 154b is formed, the metal layers 152a and 152b are etched with the second photoresist pattern 154b blocked in a portion of the metal layers 152a and 152b. As illustrated, a second source electrode 125b and a second drain electrode 126b are formed to expose a portion of the first source electrode 125a and the first drain electrode 126a. In this case, the exposed regions of the first source electrode 125a and the first drain electrode 126a may be formed to have a width x of about 2 <x <10 μm.

After that, as shown in FIG. 3G, the oxide semiconductor is stacked and etched to a thickness of about 300-700 Å, preferably about 500 Å by sputtering over the entire first substrate 110 to form a first source electrode ( An oxide semiconductor layer 122 is formed on the gate insulating layer 112 between the first drain electrode 126a and the exposed region of the first source electrode 125a and the first drain electrode 126a.

At this time, the oxide semiconductor may be an oxidizing material having a bandgap that can transmit visible light. For example, the oxide semiconductor layer 122 has a characteristic of blocking a light in a wavelength range shorter than visible light and transmitting light in a visible light region by using an oxide-based material with a band gap of about 3 eV or more. As such an oxide semiconductor, an oxide containing Zn, In, Ga, or a mixture thereof, for example, IGZO or ZTO may be used.

Subsequently, as shown in FIG. 3H, an inorganic insulating material such as SiO 2 or SiN 2 or an organic insulating material such as photoacryl or BCB (Benzo Cyclo Butene) is laminated on the entire first substrate 110. After forming the 114, the contact hole 115 is formed on the second drain electrode 126b of the thin film transistor using a fourth mask to expose the second drain electrode 126b.

Subsequently, a transparent conductive material such as ITO or IZO is laminated in the protective layer 114 and the contact hole 115 by sputtering, and then etched using a fifth mask to etch the contact hole on the protective layer 114. A pixel electrode 118 electrically connected to the second drain electrode 126b is formed through 115.

Subsequently, as shown in FIG. 3G, the black matrix 142 made of Cr or CrOx and the color filter layer 146 are formed on the transparent second substrate 140 such as glass or plastic, and then formed of ITO or IZO thereon. The transparent common electrode 146 is formed. In this case, an overcoat layer may be formed on the color filter layer 146. Subsequently, a sealant (not shown) is applied to an outer region of at least one of the first substrate 110 and the second substrate 140, and then pressure is applied to the first substrate 110 and the second substrate. The liquid crystal display device is completed by bonding the 140 and injecting the liquid crystal between the first substrate 110 and the second substrate 140 to form the liquid crystal layer 130.

As described above, in the present invention, the oxide semiconductor layer 122 is formed after the source electrodes 125a and 125b and the drain electrodes 126a and 126b are formed. Therefore, since the etchant used to etch the source electrodes 125a and 125b and the drain electrodes 126a and 126b cannot affect the oxide semiconductor layer 122 at all, the etchant reaches the oxide semiconductor layer 122. As a result, there is no need to form a conventional etch stopper for preventing a portion of the oxide semiconductor layer 122 from being etched.

Accordingly, in the present invention, a first mask for forming a gate electrode, a second mask for forming a source electrode and a drain electrode, a third mask for forming an oxide semiconductor layer, a fourth mask for forming a contact hole of a protective layer, and a fifth for forming a pixel electrode Only five masks, such as a mask, are needed in total, and the mask for forming an etch stopper is unnecessary. As described above, in the present invention, since one mask process is reduced as compared with the related art, the overall process is simplified and the manufacturing cost can be reduced.

In addition, in the present invention, the source electrode and the drain electrode are formed of a conductive material having good ohmic contact characteristics between a metal having good conductivity and an oxide semiconductor, thereby preventing signal delay and forming ohmic contact.

On the other hand, in the above description of the structure and manufacturing method of the liquid crystal display device according to the present invention, a liquid crystal display device having a specific structure has been described as an example, but the present invention is not limited to such a structure.

The most important aspect of the present invention is that the oxide semiconductor layer 122 is formed after the process of forming the source electrodes 125a and 125b and the drain electrodes 126a and 126b so that a part of the oxide semiconductor layer 122 is formed by the source electrode 125a, 125b) and drain electrodes 126a and 126b. Therefore, the thin film transistor having such a structure may be applied to a liquid crystal display device having any structure. In other words, the common electrode and the pixel electrode may be applied to an IPS mode liquid crystal display device or a VA mode liquid crystal display device formed on the first substrate, respectively. The present invention may also be applied to other flat panel display devices using thin film transistors as switching devices, such as organic light emitting display devices and electrophoretic display devices.

In addition, although the above-mentioned description specifically mentions an oxide semiconductor layer as a semiconductor layer, this invention is not limited only to such an oxide semiconductor layer, but is applied also to an amorphous silicon layer (a-Si layer), a crystalline silicon layer, and an organic semiconductor layer. Could be.

4 is a diagram illustrating a structure of a liquid crystal display device according to another exemplary embodiment of the present invention. As shown in FIG. 4, since the structure of this embodiment is similar to that of the liquid crystal display shown in FIG. 2, the description of the same structure will be omitted and only the other structure will be described.

As shown in FIG. 4, the thin film transistor of this embodiment includes a gate insulating layer formed over the gate electrode 221 formed on the first substrate 210 and the entire first substrate 210 on which the gate electrode 221 is formed. 212, the source electrode 225 and the drain electrode 226 formed at a predetermined distance from the gate insulating layer 212, and the gate insulating layer between the source electrode 225 and the drain electrode 226. And an oxide semiconductor layer 222 formed on the top and the source electrode 225 and the drain electrode 226. The oxide semiconductor layer 222 is formed in a portion of the upper portion of the source electrode 225 and the drain electrode 226, and the contact hole formed in the protective layer 214 is a drain of the region where the oxide semiconductor layer 222 is not formed. The electrode 226 is exposed, and the pixel electrode 218 is connected to the exposed drain electrode 226 through a contact hole.

In the liquid crystal display device having such a structure, the source electrode 225 and the drain electrode 226 are made of a metal capable of ohmic contact with the oxide semiconductor such as Mo. That is, in the liquid crystal display of the embodiment shown in FIG. 2, an oxide conductive material or a molybdenum compound having good ohmic contact characteristics is formed as an ohmic contact layer in contact with the oxide semiconductor layer, and a metal such as copper having good conductivity is formed thereon. On the other hand, Mo has good conductivity and good ohmic contact characteristics, so that it is not necessary to form a double layer.

In the liquid crystal display of this embodiment, since the source electrode 225 and the drain electrode 226 are formed of one layer, it is not necessary to etch and expose a part of the upper layer among the double layers, and thus the liquid crystal display of the embodiment shown in FIG. Unlike the device, the source electrode 225 and the drain electrode 226 can be formed by etching a metal such as Mo by a general photomask without using an expensive halftone mask.

Of course, in such a structure, the ohmic contact characteristics of Mo and the oxide semiconductor may be worse than the ohmic contact characteristics of ITO or MoTi and the oxide semiconductor. However, in this structure, the upper portion of the source electrode 225 and the drain electrode 226, if necessary. Since the oxide semiconductor layer can be formed in almost the entire region (except, of course, the region in contact with the pixel electrode 218 of the drain electrode 226), the source electrode (compared to the liquid crystal display device having the structure shown in FIG. The contact area between the 225 and the drain electrode 226 and the oxide semiconductor layer 222 can be increased to achieve a desired ohmic contact efficiency.

5 is a diagram illustrating a structure of a liquid crystal display device according to still another embodiment of the present invention. Also in this embodiment, the same structure as that of the liquid crystal display shown in FIG. 2 will be omitted, and only the other structure will be described.

As shown in FIG. 5, the thin film transistor formed in the liquid crystal display device according to the present exemplary embodiment has a gate electrode 321 formed on the first substrate 310 and an entire first substrate 310 on which the gate electrode 321 is formed. The gate insulating layer 312 formed over the source electrode 325 and the drain electrode 326 formed at a predetermined distance from the gate insulating layer 312, and the source electrode 325 and the drain electrode 326. The oxide semiconductor layer 322 is formed on the gate insulating layer 312 in between. A passivation layer 314 is formed on the thin film transistor, and a pixel electrode 318 is formed on the passivation layer 314 to be connected to the drain electrode 326 through a contact hole.

In the structure of this embodiment, the oxide semiconductor layer 322 is formed only on the gate insulating layer 312 between the source electrode 325 and the drain electrode 326. In this case, the source electrode 325 and the drain electrode 326 are made of Mo having good conductivity and good ohmic contact characteristics, and the contact between the oxide semiconductor layer 322 and the source electrode 325 and the drain electrode 326 is a source. Through the side of the electrode 325 and the drain electrode 326. Therefore, in the liquid crystal display device having the structure shown in FIG. 4, the source electrode and the drain electrode have a thickness of about 2000 microseconds, but in this embodiment, the source electrode 325 and the drain electrode 326 to secure a sufficient ohmic contact area. It will be desirable to form a thickness of at least 2000 kPa, for example at least 3000 kPa.

In the liquid crystal display of this structure, since the source electrode 325 and the drain electrode 326 are formed of one layer, it is not necessary to etch and expose a part of the upper layer among the double layers, and thus the liquid crystal display of the embodiment shown in FIG. Unlike the device, the source electrode 325 and the drain electrode 326 can be formed by etching a metal such as Mo with a general photomask without using an expensive halftone mask.

In the present invention, the structure and method of the thin film transistor and the liquid crystal display device are described with a specific structure and method, but the present invention is not limited to such a specific structure or method, but any structure to which the present invention can be applied by applying the basic concept. I will include the way.

110,140: substrate 112: gate insulating layer
114: protective layer 115: contact hole
118: pixel electrode 121: gate electrode
122: oxide semiconductor layer 125a, 125b: source electrode
126a, 126b: drain electrode

Claims (25)

A gate electrode disposed on the substrate;
A gate insulating layer disposed on the gate electrode;
A source electrode and a drain electrode disposed on the gate insulating layer; And
An oxide semiconductor layer disposed on the gate insulating layer between the source electrode and the drain electrode;
The source electrode and the drain electrode
A first source electrode and a first drain electrode disposed on the gate insulating layer;
A second source electrode and a second drain electrode disposed on the first source electrode and the first drain electrode;
The oxide semiconductor layer is in contact with an upper surface of each of the first source electrode and the first drain electrode, and non-contacted with an upper surface of each of the second source electrode and the second drain electrode,
The oxide semiconductor layer is disposed in an area between the source and drain electrodes to expose side and top surfaces of each of the second source electrode and the second drain electrode,
The first source electrode and the first drain electrode is made of ITO or MoTi,
The second source electrode and the second drain electrode is made of Cu,
The first source electrode and the first drain electrode are disposed to have a larger area than the second source electrode and the second drain electrode, and a portion of the first source electrode and the first drain electrode is exposed to the outside, and the exposed first source electrode And the oxide semiconductor layer formed on the first drain electrode and being in ohmic contact with the first source electrode and the first drain electrode. delete delete The thin film transistor of claim 1, wherein a width x of the exposed areas of the first source electrode and the first drain electrode is 2 μm <x <10 μm. delete delete Providing a substrate;
Forming a gate electrode on the substrate;
Forming a gate insulating layer on the substrate on which the gate electrode is formed;
Forming a source electrode and a drain electrode on the gate insulating layer;
Forming an oxide semiconductor layer on the gate insulating layer between the source electrode and the drain electrode;
The source electrode and the drain electrode
A first source electrode and a first drain electrode disposed on the gate insulating layer;
A second source electrode and a second drain electrode disposed on the first source electrode and the first drain electrode;
The oxide semiconductor layer is in contact with an upper surface of each of the first source electrode and the first drain electrode, and non-contacted with an upper surface of each of the second source electrode and the second drain electrode,
The oxide semiconductor layer is disposed in an area between the source and drain electrodes to expose side and top surfaces of each of the second source electrode and the second drain electrode,
The first source electrode and the first drain electrode is made of ITO or MoTi,
The second source electrode and the second drain electrode is made of Cu,
The first source electrode and the first drain electrode are disposed to have a larger area than the second source electrode and the second drain electrode, and a portion of the first source electrode and the first drain electrode is exposed to the outside, and the exposed first source electrode And forming the oxide semiconductor layer on the first drain electrode to be ohmic contact with the first source electrode and the first drain electrode. The method of claim 7, wherein forming the source electrode and the drain electrode,
Forming a conductive layer made of ITO or MoTi and a metal layer made of Cu on the gate insulating layer;
Forming a photoresist layer on the metal layer;
Forming a first photoresist pattern having a different thickness from each other by using a halftone mask;
Etching the conductive layer and the metal layer together using the first photoresist pattern;
Acing the first photoresist pattern to form a second photoresist pattern exposing a portion of the metal layer; And
The first source electrode and the first drain electrode and the second source electrode and the second drain electrode formed on the first source electrode and the first drain electrode are exposed by etching the exposed metal layer using the second photoresist pattern. Thin film transistor manufacturing method comprising the step of forming a. delete delete delete delete delete A first substrate and a second substrate;
A liquid crystal layer disposed between the first substrate and the second substrate;
A gate electrode disposed on the first substrate, a gate insulating layer disposed on the gate electrode, a source electrode and a drain electrode disposed on the gate insulating layer, and an oxide semiconductor layer disposed on the gate insulating layer between the source electrode and the drain electrode. A configured thin film transistor;
A pixel electrode connected to the thin film transistor; And
And a common electrode forming an electric field with the pixel electrode.
The source electrode and the drain electrode
A first source electrode and a first drain electrode disposed on the gate insulating layer;
A second source electrode and a second drain electrode disposed on the first source electrode and the first drain electrode;
The oxide semiconductor layer is in contact with an upper surface of each of the first source electrode and the first drain electrode, and non-contacted with an upper surface of each of the second source electrode and the second drain electrode,
The oxide semiconductor layer is disposed in an area between the source and drain electrodes to expose side and top surfaces of each of the second source electrode and the second drain electrode,
The first source electrode and the first drain electrode is made of ITO or MoTi,
The second source electrode and the second drain electrode is made of Cu,
The first source electrode and the first drain electrode are disposed to have a larger area than the second source electrode and the second drain electrode, and a portion of the first source electrode and the first drain electrode is exposed to the outside, and the exposed first source electrode And an oxide semiconductor layer formed on the first drain electrode to be in ohmic contact with the first source electrode and the first drain electrode. delete delete delete delete Providing a first substrate and a second substrate;
Forming a gate electrode on the first substrate;
Forming a gate insulating layer on the first substrate on which the gate electrode is formed;
Forming a source electrode and a drain electrode on the gate insulating layer;
Forming an oxide semiconductor layer on the gate insulating layer between the source electrode and the drain electrode;
Forming a protective layer on the first substrate on which the oxide semiconductor layer is formed;
Forming a pixel electrode connected to the drain electrode on the protective layer; And
Bonding the first substrate and the second substrate on which the pixel electrode is formed;
The source electrode and the drain electrode
A first source electrode and a first drain electrode disposed on the gate insulating layer;
A second source electrode and a second drain electrode disposed on the first source electrode and the first drain electrode;
The oxide semiconductor layer is in contact with an upper surface of each of the first source electrode and the first drain electrode, and non-contacted with an upper surface of each of the second source electrode and the second drain electrode,
The oxide semiconductor layer is disposed in an area between the source and drain electrodes to expose side and top surfaces of each of the second source electrode and the second drain electrode,
The first source electrode and the first drain electrode is made of ITO or MoTi,
The second source electrode and the second drain electrode is made of Cu,
The first source electrode and the first drain electrode are disposed to have a larger area than the second source electrode and the second drain electrode, and a portion of the first source electrode and the first drain electrode is exposed to the outside, and the exposed first source The oxide semiconductor layer is formed on the electrode and the first drain electrode and the ohmic contact with the first source electrode and the first drain electrode. The method of claim 19,
Forming the source electrode and the drain electrode,
Forming a conductive layer made of ITO or MoTi and a metal layer made of Cu on the gate insulating layer;
Forming a photoresist layer on the metal layer;
Forming a first photoresist pattern having a different thickness from each other by using a halftone mask;
Etching the conductive layer and the metal layer together using the first photoresist pattern;
Acing the first photoresist pattern to form a second photoresist pattern exposing a portion of the metal layer; And
The first source electrode and the first drain electrode, and the second source electrode and the second drain electrode formed on the first source electrode and the first drain electrode are exposed by etching the exposed metal layer using the second photoresist pattern. A liquid crystal display device manufacturing method comprising the step of forming an electrode. delete delete delete delete delete
KR1020120080843A 2012-07-24 2012-07-24 Thin film transistor, liquid crystal display device and method of fabricating thereof KR101980752B1 (en)

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