JPH09146119A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a display grade by changing the threshold characteristic of a p-SiTFT in a pixel part and driving circuit part. SOLUTION: The channel region 11nd of the pixel part is undoped and is formed as the channel region 11p of a shift register part. The voltage between the gate and drain during a non-selection period is negative in the pixel part and, therefore, an off current is shut off and the on-current for high mobility is increased. The dealing with higher fineness and larger screen is possible. Since the threshold increases in the shift register part, the off-current is eliminated and a malfunction is prevented.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor
The present invention relates to a liquid crystal display (LCD) equipped with (TFT: thin film transistor), and particularly, a channel layer is made of polycrystalline silicon, that is, poly-.
A poly- that realizes a drive circuit integrated type in which a drive circuit unit is integrally formed on a substrate by using Si.
Regarding SiTFT.

[0002]

2. Description of the Related Art LCDs have advantages such as small size, thin shape and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, an active matrix type using a thin film transistor, that is, a TFT as a switching element can theoretically perform static driving with a duty ratio of 100% in a multiplexed manner, and can be used for a large-screen, high-definition moving image display. It is used.

An active matrix LCD has a substrate in which TFTs are connected to display electrodes arranged in a matrix (TFT substrate) and a substrate having a common electrode (counter substrate).
Are bonded together with a liquid crystal interposed therebetween. The opposing portion between the display electrode and the common electrode is a pixel capacitance using a liquid crystal as a dielectric layer, and a voltage selected by the TFT is applied. The liquid crystal has electro-optical anisotropy and modulates light according to the intensity of the electric field formed by the pixel capacitance.

In recent years, a drive circuit integrated type LCD has been developed in which a matrix pixel portion and a peripheral drive circuit portion are formed on the same substrate by using polycrystalline silicon (p-Si) as a channel layer of a TFT. In general, p-S
i has a higher mobility than amorphous silicon (a-Si), and miniaturization by a gate self-aligned structure and high speed by reduction of parasitic capacitance are achieved.
By forming a complementary structure of the p-ch TFT and the p-ch TFT, a high speed drive circuit can be configured. In this way, by integrally forming the drive circuit portion and the matrix pixel portion,
The manufacturing cost is reduced and the LCD module is downsized.

FIG. 16 shows the structure of such an LCD.
The part surrounded by the dotted line in the central part is the matrix pixel part, and the gate line (G
1 to Gm) and drain lines for pixel signals (D1 to Dm)
n) are arranged to intersect. A TFT, which is a switching element, and a display electrode (not shown) connected to the TFT are formed at each intersection. Gate drivers (G1 to Gm) for selecting gate lines (G1 to Gm) are provided on the left and right of the display.
D) is arranged, and a drain driver that samples and holds a video signal above and below the pixel portion and applies a pixel signal voltage to each drain line (D1 to Dn) in synchronization with the scanning of the gate driver (GD). -(DD) is arranged. The drain driver (DD) mainly comprises a shift register circuit, a sampling circuit and a holding capacitor, and the gate driver (GD) mainly comprises a shift register.

FIGS. 17, 18 and 19 show the structure of a liquid crystal display device using such a p-Si TFT. 17 is a plan view of the unit pixel portion, FIG. 18 is a sectional view taken along the line BB, and FIG. 19 is an n-type p-SiT of the drive circuit portion.
It is sectional drawing of FT. An island-shaped p-Si (101) is patterned on a substrate (100) such as glass, and in the pixel portion, an auxiliary capacitance for holding charges is integrated with the island layer of the p-Si (101). The first auxiliary capacitance electrode (1
01C) is formed. SiO 2 is formed on the entire surface covering the p-Si (101) and the first auxiliary capacitance electrode (101C).
A gate insulating film (102) such as 2 is covered. Doped poly-Si is formed on the gate insulating film (102).
And a gate electrode (10 composed of a polycide layer of silicide)
3G) and an integrated gate line (103L) are formed therein. A stopper (104) is formed on the gate electrode and its line (103) to prevent the implantation of n-type impurities in the manufacturing process. Further, sidewall spacers (105) made of an insulator are formed on the sidewalls of the gate electrodes and the lines (103). Further, in the pixel portion, as shown in FIG. 18, in the island layer of p-Si (101), the gate electrode (103G) and the spacer (105) are formed.
With self-alignment using, the channel area (10
1P) and a lightly doped n-type LD region (101L) formed on both sides thereof at a low concentration, and on the outer side thereof, a heavily doped n-type source region (101S) and drain region. (101D) is formed. The channel region (101P) is p-type doped in order to obtain enhancement type characteristics. On the other hand, as shown in FIG. 19, in the drive circuit portion, the LD region is not provided and the gate electrode (103
The source and drain regions (101S, 101D) are formed on both sides of the p-type channel region (101P) by the self-aligned structure using G).

As shown in FIG. 18, a structure in which a low-concentration LD: lightly doped (101L) region (101L) is interposed between the source and drain regions (101S, 101D) and the channel region (101P) is an LDD. (Lightly do
ped drain), which suppresses leakage current in the pixel section and acts to increase the voltage holding ratio. The first
A second auxiliary capacitance electrode (103C) made of the same layer as the gate electrode and the line (103) is formed on the gate insulating film (102) corresponding to the auxiliary capacitance electrode (101C). Is formed. A first interlayer insulating film (106) such as SiNx is coated on the entire surface covering the gate electrode (103G), the line (103L) and the second auxiliary capacitance electrode (103C), and the first interlayer insulation film is formed. A drain electrode (108) and a source electrode (107) made of A1 or the like are provided on the film (106), and a first opening is formed in the gate insulating film (102) and the first interlayer insulating film (106). And the second contact hole (CT
4, CT5) and drain / source regions (10
1D, 101S). A second interlayer insulating film (109) is formed on the entire surface covering the drain electrode (108) and the source electrode (107). As shown in FIG. 18, in the pixel portion, a third contact hole (CT6) is further opened in the second interlayer insulating film (109) on the source electrode (107), and the second interlayer insulating film (CT6) is opened. A display electrode (11) made of ITO is formed on the insulating film (109).
0) is formed and is connected to the source electrode (107) through the third contact hole (CT6).

[0008]

Conventionally, as shown in FIGS. 17 and 18, even in the pixel portion, as shown in FIG.
Channel area (101P) similar to the drive unit shown in
Was p-type doped. This is because the driving circuit section needs to raise the threshold value for complementary operation, and thus the same structure is adopted also in the pixel section. However, in such a channel-doped TFT, since the channel layer is a p-type doped layer, the effective mobility is reduced in the n-ch TFT.

On the other hand, in the pixel section, it is not necessary to raise the threshold, unlike the driving section. In addition, as the size and the definition of the device progress, the improvement of charging characteristics is desired. That is, when the device is miniaturized, the channel width of the TFT is reduced and the mutual conductance is lowered, but in addition, when the mobility is low, the mutual conductance is further reduced. Further, as the definition becomes higher and the number of pixels increases, the selection period for one line becomes shorter, so that it is necessary to improve the charging characteristics.

Further, in both the drive circuit section and the pixel section,
In the case of a channel region composed of an intrinsic layer, that is, a layer having a band structure having the same Fermi level as the non-doped layer by being undoped or doped with an equal amount of n-type impurities and p-type impurities, the following problems Happens. That is, as shown in FIG. 20, the transfer characteristic has a normal characteristic curve (II
From I), the threshold value may shift in the lowering direction as shown by the characteristic curve (IV) due to impurities in the polysilicon film. At this time, in the shift register section,
During standby, for example, the gate-drain voltage is 0V
Then, when the source voltage is at a high level, a sub-threshold current (Ia) is generated. According to the measurement, the swing showing the sub-threshold characteristic, that is, the gate voltage required to raise the source / drain current by one digit is about 0.2 to 0.3 V / dec. Therefore, when the voltage-current characteristics are shifted as shown in FIG. 20, even when the gate voltage slightly changes to (Va), the sub-threshold current (I
This caused a drastic increase in b), resulting in a leakage current during standby, which also caused a malfunction.

[0011]

The present invention has been made to solve this problem. First, a pixel portion in which display pixels are arranged in a matrix on a substrate, a shift register circuit, and a sampling circuit. And a drive circuit section for driving the display pixel, the display pixel and the drive circuit section being formed of a thin film transistor using polycrystalline silicon as a channel layer. The thin film transistor constituting the above-mentioned thin film transistor is formed of island-shaped polycrystalline silicon including a channel region containing a first conductivity type impurity and source and drain regions containing a second conductivity type impurity on both sides of the channel region. A layer and a gate electrode arranged to face the channel region with an insulating film interposed therebetween,
The thin film transistor forming the pixel portion and the sampling circuit includes a channel region formed in an island shape and having impurities as an intrinsic layer, and a source region having a high concentration of a second conductivity type impurity on both sides of the channel region. And a polycrystalline silicon layer including a drain region,
The gate electrode is arranged to face the channel region with an insulating film interposed therebetween.

By forming the channel layer of the thin film transistor forming the pixel portion and the sampling circuit by a layer having intrinsic characteristics, that is, a layer having the same Fermi level as the non-doped layer, the threshold value between the gate and the drain is around 0V. Since the operation is controlled by the low voltage, the power consumption is reduced. Further, since the mobility of the channel region does not decrease, the charging rate of the display voltage does not decrease even if the ON period of the transistor is shortened due to miniaturization and high definition of the transistor. On the other hand, in the shift register circuit, since the threshold value is raised by the channel doping of the thin film transistor,
Sub-threshold current does not flow even during standby, and accurate complementary operation is performed.

Further, in particular, the thin film transistor forming the pixel portion has a structure in which the LD region containing the second conductivity type impurity at a low concentration is interposed between the channel region and the source region and the drain region. This prevents the problem that the OFF current increases in the thin film transistor in which the channel region does not contain impurities,
The voltage holding ratio is improved and the contrast ratio is improved.

[0014]

1 is a sectional view of each part of a TFT substrate which constitutes a liquid crystal display device according to a first embodiment of the present invention. 1A is a cross-sectional view of the pixel portion, and FIG.
(B) is a cross-sectional view of the shift register portion, and both are n
-Ch TFT is shown. In addition, (c) of FIG.
It is a sectional view of a chTFT. The sampling unit
The TFT has a structure similar to that of FIG.
2 is a plan view of the unit pixel portion, and FIG.
FIG. 3 is a sectional view taken along the line AA of FIG.

On a substrate (10) such as glass, p-Si
(11) is formed in an island shape, and Si is formed on the entire surface covering this.
A gate insulating film (12) of O2 is formed. On the gate insulating film (12), the gate line (13L) and the gate electrode (1L) are formed by polycide made of a laminated body of doped poly-Si and silicide such as tungsten.
3G) is formed, and the gate electrode (13G) is p-Si.
(11) It is arranged above the island layer. In the pixel portion (sampling portion) (a), an area directly under the gate electrode (13G) in the p-Si (11) is a non-doped layer, and in the shift register portion (b), it is p-type lightly doped. , And channel regions (11nd, 11pc), respectively. The p-ch portion (c) is a non-doped channel region (11nd). Further, in the pixel part (a), LD (lightly dope) n-type lightly doped on both sides of the channel region (11nd) is self-aligned with the gate electrode (13G).
d) The n-type heavily doped source and drain regions (11S, 11D) are formed outside the region (11L) and the LD region (11L), and LDD (ligh
tly doped drain) structure. In the shift register part (b) and the p-ch part (c), n-type and p-type high-concentration doping was performed on both sides of the channel region (11pc, 11nd) in a self-aligned relationship with the gate electrode (13G). Source and drain regions (1
1S, 11D) are formed. Also, the pixel portion (a)
Then, the first auxiliary capacitance electrode (11C) is formed of the p-Si layer integrated with the source region (11S) and is covered with the gate insulating film (12). A second auxiliary capacitance electrode (13C) made of polycide of the same material as that of the gate electrode (13G) is formed on the first auxiliary capacitance electrode (11C) with the gate insulating film (12) interposed therebetween, and holds a charge. Forming the auxiliary capacitance of. On the gate electrode (13G) and the first auxiliary capacitance electrode (13C), an injection stopper (1
4) is formed in the same pattern. A spacer (15) such as SiO2 is formed on the side walls of the gate line and electrode, the auxiliary capacitance electrode (13) and the injection stopper (14).
Are formed. A first interlayer insulating film (16) made of SiO2 or the like is formed on the entire surface covering these,
A drain electrode (18) and a source electrode (17) made of Al or the like are formed on the inter-layer insulating film (16), and the gate insulating film (12) and the first inter-layer insulating film (16) are respectively formed.
Through the contact holes (CT1, CT2) formed therein, the drain region (11D) and the source region (11
S). A second interlayer insulating film (19) made of a flattening film such as an SOG film is formed on the entire surface covering the drain electrode (18) and the source electrode (17). Further, in the pixel portion (a), the second interlayer insulating film (1
9) A display electrode (20) made of ITO (indium tin oxide) is formed on the same, and connected to the source electrode (17) through a contact hole (CT3) formed in the second interlayer insulating film (18). Has been done.

The transfer characteristics of these TFTs are shown in FIG. FIG. 3 shows the relationship between the gate voltage Vg and the drain-source current Is near the threshold voltage. In the TFT of the pixel portion shown in FIG. 1A, the channel region (11nd)
Is formed of a non-doped poly-Si layer. Therefore, as shown in the graph (I) in FIG. 3, the transfer characteristic shows a characteristic that there is a threshold value near Vg = 0. Further, in the TFT of the shift register portion shown in FIG. 1B, the channel region (11 pc) is
Since it is formed of poly-Si that is p-type doped at a low concentration and the voltage required for forming the inversion layer is shown in FIG.
As shown in the graph (II) of (1), the threshold value becomes higher than that of the graph (I) in the form shifted to the right of the graph (I).

On the other hand, FIGS. 4A and 4B respectively show the electrode voltages of the pixel section TFT shown in FIG. 1A and the shift register TFT shown in FIG. 1B. The voltage of each electrode is shown. Vg is a gate voltage and Vd is a drain voltage. As can be seen from FIG. 4A, of the voltages applied to the electrodes of the pixel portion TFT shown in FIG. 1A, the drain voltage Vd is inverted between positive and negative, and every horizontal period, It is an analog signal voltage whose level changes according to the display gradation. During the non-selection period, that is, the TFT is OF
In the period F, the gate voltage Vg is negative and the gate-drain voltage Vgd is set negative. In normal driving, the gate-drain voltage Vgd is at least -2V
There is a degree, and when the drain voltage Vd is positive, it becomes as high as -15V. Also, in the sampling unit that samples the drain voltage from the video signal, the operation of the TFT is driven by the same electrode voltage as this. Therefore, the TFT of the pixel portion and the TF of the sampling portion shown in FIG.
As shown in the graph (I) of FIG. 3, T preferably has a characteristic that Vg = 0V and has a threshold value. That is, the channel area (11
nd) is a non-doped layer, the OFF current does not increase due to the p-type carriers even when the gate-drain voltage Vgd becomes negative, and the channel region (11nd) is non-doped. Since the frequency is high and the charging capability is improved, even if one horizontal scanning period is shortened due to miniaturization of transistor size, high definition, and increase in the number of pixels, excellent display can be performed. Further, since the threshold value of the gate-drain voltage Vgd is reduced, the drive voltage level can be lowered as a whole, and the power consumption is reduced. Further, while the channel width of the TFT of the pixel portion is 2 μm, the TF of the sampling portion is
The channel width of T is about 600 μm, and the threshold is greatly increased by channel doping. That is, the threshold value varies between the pixel section and the sampling section. Therefore, since the threshold value control is facilitated by not performing the channel doping in the sampling unit, the design cost is reduced and the yield is improved.

Further, as shown in FIG. 4B, the TFT of the shift register portion of FIG. 1B has a gate voltage Vg.
The drain voltage Vd is a digital operation in which the high level and the low level are the same voltage. Therefore, since the gate-drain voltage Vgd becomes 0 V during OFF,
In order to cut off the current, the threshold value is preferably higher than 0V. That is, when the gate voltage Vg is at a low level in standby, the sub-threshold current is prevented and the leak current is suppressed by setting the gate-drain voltage Vgd to be less than or equal to the threshold value with a slight margin. Therefore, malfunction is prevented. It

That is, in the present invention, in the pixel section and the sampling section, the drain voltage is the analog signal voltage, and attention is paid to the fact that the gate-drain voltage is made negative to interrupt the conduction, and the threshold value is set by the channel doping. In addition, even if the gate-drain voltage becomes negatively large, the p-type conduction is eliminated and the O
The FF current is suppressed. Further, since the mobility at the time of ON is improved, it is possible to cope with high definition and large screen. Furthermore, the point that the OFF current cannot be cut off by the pn junction barrier is compensated by suppressing the OFF current by the LDD structure. At the same time, in the shift register section that performs a digital operation, channel doping is performed and the threshold value is increased to increase the margin for the shift of the signal voltage level, prevent malfunction, and improve reliability.

Next, a method of manufacturing the liquid crystal display device shown in FIG. 1 will be described. 5 to 15 are process cross-sectional views showing the manufacturing method. 1A is a TFT of a pixel portion corresponding to FIG. 1A, FIG. 2B is an n-ch TFT of a shift register portion corresponding to FIG. 2B, and FIG. It is a p-ch TFT corresponding to (c) of FIG. The TFT of the sampling section is manufactured by the same method as in (a).

First, in FIG. 5, a CVD process using silane SiH 4 as a material gas is performed on a glass substrate (10).
Then, amorphous silicon (a-Si) is laminated.
This a-Si is polycrystallized by excimer laser annealing at 400 ° C. to obtain polysilicon (p-Si) (11). This is a reactive ion etch, that is, RIE (re
Etching is performed by active ion etching to form the island layer of the TFT portion and the first auxiliary capacitance electrode (11C).

Next, referring to FIG. 6, the pixel portion (a) and p
After the -ch portion (c) is covered with the resist (R), the p-Si (11) layer of the shift register portion (b) is p-typed by performing ion implantation of boron (B) which is a p-type impurity.
Dope the mold lightly. After stripping the resist, as shown in FIG. 7, SiO2 is laminated to a thickness of 1000 L by low pressure CVD at 440 [deg.] C. to form a gate insulating film (12). Then, a resist (R) is coated on all the TFT portions, and n-type impurities such as phosphorus (P) are ion-implanted to reduce the resistance of the first auxiliary capacitance electrode (11C).

Next, as shown in FIG.
By high-temperature CVD at 580 ° C with helium as a material gas
After stacking —Si and reducing the resistance by ion implantation of phosphorus, tungsten silicide (WSi) is sputtered. Successively, SiO2 serving as an injection stopper (14) is laminated by atmospheric pressure CVD at 410 ° C. Then, the SiO2 and the poly-side layers of poly-Si and WSi are etched in the same pattern by RIE, and the gate electrode (13G) and the gate line (13L) for connecting the gate electrode (13L) to each other in the pixel portion, the second auxiliary. The capacitor electrode (13C) and these gate electrodes (1
3G) and its line and the second auxiliary capacitance electrode (13C)
Form an injection stopper (14) coated on top.

As shown in FIG. 9, again, the normal pressure C at 410 ° C.
By depositing SiO2 by VD and etching it by RIE, sidewall spacers (15) are formed on the gate electrode (13G) and the injection stopper (14) thereon. Next, as shown in FIG.
After forming the resist (R) covering (c), the first ion implantation of n-type impurities such as phosphorus (P) is performed at a low dose amount (3 to 5 × 10 ↑ 13 / cm ↑ 2), With the gate electrode (13G) as a mask, the source and drain regions (11
The regions to be S, 11D) and the LD region (11L) are lightly doped (n-). At this time, in the pixel part (a), the undoped channel region (11nd) is provided immediately below the gate electrode (13G), and the n-c part of the shift register part (b) is used.
In the hTFT, it remains as a p-type doped channel region (11 pc). The spacer (1
5) is to provide a margin for lateral diffusion due to annealing after phosphorus ion implantation in this step,
It has a function of reducing the impurity concentration at the end of the channel region, relaxing the drain electric field, and improving the breakdown voltage.

Subsequently, as shown in FIG. 11, the pixel portion (a)
Is covered with a resist (R1) having a size larger than that of the gate electrode (13G), and the second ion implantation of phosphorus (P) is performed with the resist (R1) as a mask at a high dose (3 × 10 ↑ 15 / cm ↑).
Perform in 2). As a result, the resist (R
1) The LD region (11L) is formed immediately under the LD region (n-) with a low concentration, and the LD region is formed.
Outside the region (11L), a source region (11S) and a drain region (11D) made of a heavily doped n + layer are formed. In the shift register part (b), there is no LD region, and a source region (11S) and a drain region (11D) made of highly doped n + layers are formed on both sides of the channel region (11pc).

After removing the resist, as shown in FIG.
N-chT of pixel section (a) and shift register section (b)
A resist (R) covering the FT is formed, boron (B) which is a p-type impurity is ion-implanted, and a source region (1) of the p-chTFT (c) is formed by the p-type high concentration layer (p +).
1S) and the drain region (11D) are formed. At this time, the channel region (11nd) is formed immediately under the gate electrode (13G) while being kept undoped. Also,
The implantation stopper (14) prevents the resistance from increasing due to counter-doping of boron into the gate electrode and its line which are n-type doped and have a low resistance.

By lamp annealing or excimer laser annealing, p-Si doped regions (11 cp, 1
1L, 11S, 11D), and then, as shown in FIG.
Å After forming and annealing at 600 ℃, further 300 ℃
SiO2 is deposited to a thickness of 3000 Å by plasma CVD to form a first interlayer insulating film (16). After that, for the purpose of dangling bonds termination in silicon, H at 450 ℃
2 After annealing, contact holes (C) are formed in the gate insulating film (12) and the first interlayer insulating film (16) on the drain and source regions (11D, 11S) by RIE.
T1, CT2) are formed.

Then, as shown in FIG. 14, Ti / AlS
i was deposited by sputtering to a thickness of 7,000 Å, and this was patterned by RIE to form a drain electrode (17) and a source electrode (18), which were respectively formed through the contact holes (CT1, CT2) to form the drain and It is connected to the source region (11D, 11S). again,
After the H plasma treatment at 390 ° C. for the dangling bonds termination in silicon, as shown in FIG.
After stacking SiO2 to a thickness of 2000Å by VD, the SOG film, that is, the SiO2 film formed by spin coating and baking is coated and flattened, and then 410
The second interlayer insulating film (19) is completed by laminating SiO2 to a thickness of 1000Å by CVD at ℃. And R
The second on the source electrode (18) of the pixel portion (a) by IE
Hole (CT3) in the interlayer insulating film (19) of
To form

Finally, an ITO film is formed by sputtering, and this is patterned by RIE to form a display electrode (20), which is connected to the source electrode (18) to complete the TFT substrate shown in FIG.

[0030]

As is apparent from the above description, according to the present invention, in a liquid crystal display device in which a driving circuit section is integrally formed on a substrate by a polycrystalline silicon thin film transistor like a pixel section, a shift register section of the driving circuit section is provided. The structure is such that the channel doping is performed on the pixel section and the sampling section of the pixel section and the driving circuit section is not channel-doped.
This increases the threshold value in the shift register section, provides a conduction / non-conduction control margin for complementary operation, prevents malfunctions, and improves reliability. In addition, the pixel section and the sampling section are turned off by p-type conductivity. Since the current is prevented, the contrast ratio is improved, and the ON resistance is lowered to improve the charging efficiency, a display device suitable for high definition and large screen can be obtained. In addition, since the threshold value is low, low voltage driving is possible and power consumption is reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a TFT of each part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a plan view of a unit pixel portion of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 3 is a transfer characteristic characteristic of the TFT of each part of the liquid crystal display device according to the embodiment of the present invention.

FIG. 4 is a voltage waveform diagram of a TFT in each part of the liquid crystal display device according to the embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing the method of manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 6 is a process cross-sectional view showing the method of manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 7 is a process cross-sectional view showing the method of manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 9 is a process cross-sectional view showing the method of manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 10 is a process cross-sectional view showing the method of manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 11 is a process cross-sectional view showing the method of manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method for manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 15 is a process sectional view illustrating the method for manufacturing the liquid crystal display device according to the embodiment of the present invention.

FIG. 16 is a configuration diagram of a liquid crystal display device.

FIG. 17 is a plan view of a unit pixel portion of a liquid crystal display device.

FIG. 18 is a cross-sectional view taken along the line BB of FIG.

FIG. 19 is a cross-sectional view of a drive circuit unit.

FIG. 20 is a TF explaining a problem of a conventional liquid crystal display device.
It is a transfer characteristic of T.

[Explanation of symbols]

 10 substrate 11 p-Si 12 gate insulating film 13 gate electrode wiring 14 injection stopper 15 spacer 16 first interlayer insulating film 17 drain electrode 18 source electrode 19 second interlayer insulating film 20 display electrode CT1, CT2, CT3 contact hole R Resist

Claims (2)

[Claims] 1. A pixel portion in which display pixels are arranged in a matrix and a drive circuit portion including a shift register circuit and a sampling circuit for driving the display pixels are formed on a substrate. In the liquid crystal display device, wherein the driving circuit portion is formed of a thin film transistor using polycrystalline silicon as a channel layer, the thin film transistor forming the shift register circuit is formed in an island shape and includes a channel region containing impurities of the first conductivity type. And a polycrystalline silicon layer including a source region and a drain region containing a second conductivity type impurity on both sides of the channel region, and a gate electrode arranged to face the channel region with an insulating film interposed therebetween. The thin film transistors forming the pixel portion and the sampling circuit are formed in an island shape and are impure. A channel region formed of intrinsic layer, and a polycrystalline silicon layer containing a source region and a drain region containing a high concentration of the second conductivity type impurity into both sides of the channel region,
A liquid crystal display device, comprising: a gate electrode arranged to face the channel region with an insulating film interposed therebetween. 2. The thin film transistor forming the pixel portion is an LD containing a low concentration of the second conductivity type impurity between a channel region and a source region and a drain region.
The liquid crystal display device according to claim 1, wherein a region is interposed.