JPH08250742A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08250742A JPH08250742A JP5404195A JP5404195A JPH08250742A JP H08250742 A JPH08250742 A JP H08250742A JP 5404195 A JP5404195 A JP 5404195A JP 5404195 A JP5404195 A JP 5404195A JP H08250742 A JPH08250742 A JP H08250742A
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- Prior art keywords
- tft
- insulating film
- gate insulating
- type
- substrate
- Prior art date
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- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多結晶半導体薄膜電界効
果トランジスタを備えた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a polycrystalline semiconductor thin film field effect transistor.
【０００２】[0002]
【従来の技術】近年、多結晶薄膜電界効果トランジスタ
（以下、ｐ−ＳｉＴＦＴと略記）は、液晶表示装置、密
着センサ等に実用化されるようになり、さらに開発が活
発に進められている。2. Description of the Related Art In recent years, a polycrystalline thin film field effect transistor (hereinafter abbreviated as p-SiTFT) has been put to practical use in a liquid crystal display device, a contact sensor, etc., and further actively developed.
【０００３】また、特に液晶表示装置においては、その
画像表示の画素部分のスイッチング用ＴＦＴと、同一基
板の画像表示周辺上に画素を駆動するために周辺駆動回
路系（いわゆるＬＣＤドライバー；液晶駆動回路）とを
ＴＦＴにより作り込んだ構成の駆動回路一体型液晶表示
装置が開発されてきている。上述のｐ−ＳｉＴＦＴは、
特にこの分野に好適の技術として注目されている。Further, particularly in a liquid crystal display device, a peripheral driving circuit system (so-called LCD driver; liquid crystal driving circuit) for driving a pixel on a switching TFT of a pixel portion of the image display and an image display periphery of the same substrate. ) And a drive circuit integrated liquid crystal display device having a structure in which they are formed by a TFT have been developed. The p-Si TFT described above is
In particular, it is drawing attention as a technique suitable for this field.
【０００４】ところで、このｐ−ＳｉＴＦＴを駆動回路
に用いるに際しての課題の１つに、しきい値電圧の制御
がある。これは、しきい値電圧が極端に高い場合駆動電
圧を上げる必要が生じ、また、しきい値電圧が極端に低
い場合消費電力が大きくなってしまうためである。この
ようなしきい値電圧をもつＴＦＴでは、駆動回路を十分
に駆動させることができない。By the way, one of the problems in using the p-Si TFT in a driving circuit is controlling the threshold voltage. This is because when the threshold voltage is extremely high, it is necessary to increase the drive voltage, and when the threshold voltage is extremely low, power consumption increases. With a TFT having such a threshold voltage, the driving circuit cannot be driven sufficiently.
【０００５】このようなｐ−ＳｉＴＦＴのしきい値電圧
制御の対策としては、既に知られた技術として、チャネ
ルドーピング法がある。これは、ＴＦＴのチャネル領域
にキャリアとなり得る不純物を注入することにより、し
きい値電圧を制御しようとするものである。例えば、ｎ
型ＴＦＴでは、チャネル領域にリンを注入することによ
りしきい値電圧を正方向に、ボロンを注入することによ
りしきい値電圧を負方向にシフトすることができる。As a measure for controlling the threshold voltage of such a p-Si TFT, there is a channel doping method as a known technique. This is intended to control the threshold voltage by injecting impurities that can serve as carriers into the channel region of the TFT. For example, n
In the type TFT, the threshold voltage can be shifted in the positive direction by injecting phosphorus into the channel region, and can be shifted in the negative direction by injecting boron.
【０００６】しかしながら、チャネルドープによるしき
い値制御では、キャリアが移動するチャネル領域に不純
物が注入されているので、キャリアを拡散してしまい移
動度が低下するという問題がある。However, in the threshold control by channel doping, since the impurities are injected into the channel region where the carriers move, there is a problem that the carriers are diffused and the mobility is lowered.
【０００７】[0007]
【発明が解決しようとする課題】上述のように、従来の
ｐ−ＳｉＴＦＴでは所望のしきい値電圧にしなければ、
駆動回路を充分有効に駆動されないという問題があっ
た。As described above, in the conventional p-Si TFT, if the desired threshold voltage is not achieved,
There is a problem that the drive circuit cannot be driven effectively.
【０００８】また、しきい値を制御したチャネルドープ
ｐ−ＳｉＴＦＴでは、しきい値制御を行っていないＴＦ
Ｔに比べて、移動度が低下するという問題があった。Further, in the channel-doped p-Si TFT whose threshold value is controlled, the TF in which the threshold value is not controlled is used.
There is a problem that the mobility is lower than that of T.
【０００９】本発明は、上記問題を考慮してなされ、ｐ
−ＳｉＴＦＴの移動度を低下させることなく、しきい値
電圧の制御を行う半導体装置を提供することにある。The present invention has been made in consideration of the above problems, and p
-To provide a semiconductor device that controls the threshold voltage without reducing the mobility of the SiTFT.
【００１０】[0010]
【課題を解決するための手段】本発明は、同一絶縁基板
上に、ゲート絶縁膜膜厚が異なる２種類以上の多結晶半
導体薄膜電界効果トランジスタを具備していることを特
徴とする半導体装置を得るものである。According to the present invention, there is provided a semiconductor device comprising two or more types of polycrystalline semiconductor thin film field effect transistors having different gate insulating film thicknesses on the same insulating substrate. I will get it.
【００１１】[0011]
【作用】本発明の半導体装置は、液晶表示装置のアクテ
ィアブマトリクス基板に用いると好適である。The semiconductor device of the present invention is suitable for use in an active matrix substrate of a liquid crystal display device.
【００１２】本発明は液晶層を挟持する一対の基板の一
方を構成するアクティアブマトリクス基板上に、ゲート
絶縁膜膜厚が異なる例えばポリシリコンの半導体薄膜電
界効果トランジスタ（ＴＦＴ）を、スイッチングＴＦＴ
と駆動用のＴＦＴに用いる。すなわち、駆動用回路は、
例えば図４に示すようなＣ−ＭＯＳ回路２０の組み合わ
せであり、画素ごとにマトリクス配列したスイッチング
ＴＦＴと同じ基板に、ＴＦＴによる回路を形成する。According to the present invention, a semiconductor thin film field effect transistor (TFT) of, for example, polysilicon having a different gate insulating film thickness is provided on a switching matrix TFT on an active matrix substrate which constitutes one of a pair of substrates sandwiching a liquid crystal layer.
And used for driving TFT. That is, the drive circuit is
For example, it is a combination of C-MOS circuits 20 as shown in FIG. 4, and a circuit of TFTs is formed on the same substrate as the switching TFTs arranged in a matrix for each pixel.
【００１３】このＣ−ＭＯＳ回路の特性を制御するた
め、Ｃ−ＭＯＳを構成するｎ型、ｐ型ＴＦＴにおいてゲ
ート絶縁膜膜厚を異ならせて、しきい値を制御する。さ
らに、片方のＴＦＴの酸化膜を積層構造にすることによ
り、膜の界面数を変えて、固定電荷密度を異ならせる
と、ＴＦＴのしきい値電圧は固定電荷密度に依存するこ
とから、各々のＴＦＴの固定電荷密度を制御することに
よりＴＦＴのしきい値をさらに容易に制御することが可
能になる。In order to control the characteristics of this C-MOS circuit, the threshold value is controlled by making the gate insulating film thickness different in the n-type and p-type TFTs forming the C-MOS. Furthermore, if the fixed charge density is changed by changing the number of interfaces of the films by making the oxide film of one TFT into a laminated structure, the threshold voltage of the TFT depends on the fixed charge density. By controlling the fixed charge density of the TFT, the threshold value of the TFT can be controlled more easily.
【００１４】[0014]
【実施例】以下、実施例を示し、本発明を詳細に説明す
る。The present invention will be described in detail below with reference to examples.
【００１５】図１乃至図４は本発明の一実施例を液晶表
示装置に適用したもので、図１において、ガラス板でで
きた透明な絶縁性の観察側基板１１の一面にＩＴＯ（イ
ンジウム錫酸化物）の導電膜でできた透明共通電極１３
が被着され、この観察側基板１１に対して所定の間隙で
対向するガラス基板の透明な絶縁性の対向基板１２の対
向面に各画素ごとにマトリクス配列されたＩＴＯの画素
電極１４と各画素電極に接続されたスイッチングＴＦＴ
１５、配線層１６が配置される。この配線層として図４
に示すように、ゲート線１８、データ線１９および図示
しない蓄積容量線がある。これら基板１１、１２の間隙
には液晶層１７が基板間に挟持されるように充填封入さ
れる。1 to 4 show an embodiment of the present invention applied to a liquid crystal display device. In FIG. 1, ITO (indium tin) is formed on one surface of a transparent insulating observing side substrate 11 made of a glass plate. Transparent common electrode 13 made of conductive film of oxide)
And a pixel electrode 14 of ITO arranged in a matrix for each pixel and each pixel on the opposing surface of the transparent insulating counter substrate 12 of the glass substrate facing the observation side substrate 11 with a predetermined gap. Switching TFT connected to the electrode
15 and the wiring layer 16 are arranged. This wiring layer is shown in FIG.
As shown in, there are a gate line 18, a data line 19 and a storage capacitance line (not shown). A liquid crystal layer 17 is filled and sealed in the gap between the substrates 11 and 12 so as to be sandwiched between the substrates.
【００１６】液晶駆動時は、透明共通電極１３は接地さ
れ、画素電極１４に各付属するスイッチングＴＦＴ１５
を介して選択的に電圧が印加される。When the liquid crystal is driven, the transparent common electrode 13 is grounded, and the switching TFTs 15 attached to the pixel electrodes 14 are provided.
A voltage is selectively applied via.
【００１７】図４は駆動回路の一部としてゲート線１８
の始端に接続されたＣＭＯＳ回路２０および各画素のス
イッチングＴＦＴ１５、１５…をマトリクス配列のゲー
ト線１８、データ線１９とともに示している。FIG. 4 shows a gate line 18 as a part of the driving circuit.
The CMOS circuit 20 and the switching TFTs 15, 15 ... Of each pixel connected to the start end of the are shown together with the gate line 18 and the data line 19 in a matrix arrangement.
【００１８】ＣＭＯＳ回路２０はｎ型ｐ−ＳｉＴＦＴ２
１とｐ型ｐ−ＳｉＴＦＴ２２とからなるバッファ回路を
形成しており、また、スイッチングＴＦＴ１５はｎ型ｐ
−ＳｉＴＦＴからなる。ここで符号１７1 は各画素領域
の液晶層であり、符号２３は蓄積容量線を含む各画素ご
との容量を示す。スイッチングＴＦＴ１５のスイッチン
グにより、画素単位で液晶層の液晶分子配列が制御さ
れ、透過する光に対して光スイッチまたは光バルブとし
て働く。The CMOS circuit 20 is an n-type p-SiTFT2.
1 and a p-type p-Si TFT 22 form a buffer circuit, and the switching TFT 15 is an n-type p-Si TFT 22.
-It consists of SiTFT. Here, reference numeral 171 is a liquid crystal layer in each pixel region, and reference numeral 23 is a capacitance for each pixel including a storage capacitance line. The switching of the switching TFT 15 controls the alignment of the liquid crystal molecules in the liquid crystal layer on a pixel-by-pixel basis, and acts as an optical switch or a light valve for the transmitted light.
【００１９】図２および図３は図１および図４に示す液
晶表示装置のアクティブマトリクス基板すなわち対向基
板１２上に形成されるｐ−ＳｉＴＦＴ構造を示してい
る。なお、図に付した符号を図５で説明する各部分に対
応して合わせている。各ｐ−ＳｉＴＦＴにおいて、基板
１２上でｎ型ｐ−ＳｉＴＦＴ２１とｐ型ｐ−ＳｉＴＦＴ
２２が相互接続されてＣＭＯＳ回路を形成しており、さ
らに、スイッチングＴＦＴとしてｎ型ｐ−ＳｉＴＦＴ１
５が同一基板１２上においてＩＴＯ画素電極１４に接続
されている。2 and 3 show a p-SiTFT structure formed on the active matrix substrate, that is, the counter substrate 12 of the liquid crystal display device shown in FIGS. Note that the reference numerals attached to the drawings are matched to correspond to the respective parts described in FIG. In each p-SiTFT, the n-type p-SiTFT 21 and the p-type p-SiTFT are formed on the substrate 12.
22 are interconnected to form a CMOS circuit, and an n-type p-SiTFT1 is used as a switching TFT.
5 are connected to the ITO pixel electrode 14 on the same substrate 12.
【００２０】ｎ型ｐ−ＳｉＴＦＴ２１はゲート絶縁膜が
第１のゲート絶縁膜３３と第２のゲート絶縁膜３４から
なり、一方、ｐ型ｐ−ＳｉＴＦＴ２２はゲート絶縁膜が
第２のゲート絶縁膜３４のみからなる。ｎ型ｐ−ＳｉＴ
ＦＴ１５、２２のゲート絶縁膜は膜３３と３４の膜厚の
加算となるので、ｐ型ｐ−ＳｉＴＦＴ２１のそれよりも
厚い。すなわち、ｎ型とｐ型とでゲート絶縁膜の膜厚を
異ならせて、ＴＦＴのしきい値電圧を独立に制御し、ス
イッチングＴＦＴ、ＣＭＯＳ回路として組み合わせたと
きに良好な回路特性を設計することができる。The n-type p-Si TFT 21 has a gate insulating film composed of a first gate insulating film 33 and a second gate insulating film 34, while the p-type p-Si TFT 22 has a second gate insulating film 34. Consists of only. n-type p-SiT
The gate insulating film of the FTs 15 and 22 is the sum of the film thicknesses of the films 33 and 34, and thus is thicker than that of the p-type p-Si TFT 21. That is, the thickness of the gate insulating film is made different between the n-type and the p-type, the threshold voltage of the TFT is independently controlled, and good circuit characteristics are designed when combined as a switching TFT and a CMOS circuit. You can
【００２１】さらに、２層のゲート絶縁膜の積層によ
り、膜間の界面を増加させる結果、固定電荷密度を容易
に異ならせることができ、さらに一層、ＴＦＴのしきい
値電圧の設定幅を大きく制御可能である。Further, by stacking two layers of gate insulating films, the interface between the films is increased, so that the fixed charge densities can be easily made different, and the setting range of the threshold voltage of the TFT is further increased. It is controllable.
【００２２】さらに、図３に示すように複数層のゲート
絶縁膜の形成の利点の一つは、ｉ型ポリシリコン膜にド
ープする不純物量を電極、ゲート絶縁膜厚の変化で制御
してＴＦＴの特性を改善できることである。図はＬＤＤ
（Lightly Doped Drain ）構造のｎ型ＴＦＴを示してお
り、第１のゲート絶縁膜３３、第２のゲート絶縁膜３４
およびゲート電極膜３５の積層構造をマスクとして、後
述するように、例えばｎ型不純物であるリンをイオン注
入すると、ゲート電極膜３５下は注入がなく、ｉのチャ
ンネル領域となり、第１と第２のゲート絶縁膜下はｎ-
領域となり、第２の絶縁膜３４のみの部分はｎ+ 領域と
なる。すなわち、ゲート電極３５の幅よりも外側にｎ-
領域が存在するＴＦＴとなり、電圧特性が改善される。Further, as shown in FIG. 3, one of the advantages of forming a multi-layered gate insulating film is that the amount of impurities to be doped into the i-type polysilicon film is controlled by changing the thickness of the electrode and the gate insulating film. That is, the characteristics of can be improved. The figure shows LDD
It shows an n-type TFT having a (Lightly Doped Drain) structure, and includes a first gate insulating film 33 and a second gate insulating film 34.
As described later, when phosphorus, which is an n-type impurity, is ion-implanted using the stacked structure of the gate electrode film 35 as a mask, there is no implantation below the gate electrode film 35, and the i-channel region is formed. under the gate insulating film the n -
The second insulating film 34 serves as an n + region. That is, n − outside the width of the gate electrode 35.
The TFT has a region, and the voltage characteristic is improved.
【００２３】さらに、ゲート絶縁膜の各層の膜厚の調節
によりｎ- 領域の部分をｉ領域のままに残すオフセット
構造とすることができるなど、ｐ−ＳｉＴＦＴの特性制
御をさらに容易にする。Further, by adjusting the film thickness of each layer of the gate insulating film, an offset structure in which the n − region is left as it is can be left as it is, thereby facilitating the characteristic control of the p-Si TFT.
【００２４】図５は、本実施例に係る液晶表示装置用ア
クティブマトリクス基板の製造プロセスを示す。FIG. 5 shows a manufacturing process of an active matrix substrate for a liquid crystal display device according to this embodiment.
【００２５】工程（ａ）：例えばガラス基板等の透光性
基板１２上にプラズマＣＶＤ法により、ＳｉＯ2 等から
なるバッファ層３１を形成する。更に、プラズマＣＶＤ
法などにより５００Ａ（オングストローム）のアモルフ
ァスシリコン膜を被着し、エキシマレーザアニール法に
よりポリシリコン（ｐ−Ｓｉ）とした後に、フォトリソ
グラフィーおよび、エッチングによりｐ−Ｓｉパターン
３２を形成する。Step (a): A buffer layer 31 made of SiO 2 or the like is formed on the transparent substrate 12 such as a glass substrate by plasma CVD. Furthermore, plasma CVD
A 500 A (angstrom) amorphous silicon film is deposited by a method such as a method, and polysilicon (p-Si) is formed by an excimer laser annealing method, and then a p-Si pattern 32 is formed by photolithography and etching.
【００２６】工程（ｂ）：次いで、プラズマＣＶＤ（Ｐ
ＥＣＶＤ）法等によりＳｉＯ2 からなる第１のゲート絶
縁膜３３を３００Ａ〜４００Ａ厚に形成する。Step (b): Next, plasma CVD (P
A first gate insulating film 33 made of SiO 2 is formed to a thickness of 300 A to 400 A by the ECVD method or the like.
【００２７】工程（ｃ）：フォトリソグラフィーおよ
び、エッチングによりゲート電極膜３３のパターンを形
成する。このとき、画素部ＴＦＴ１５において第１の絶
縁膜のパターン３３はＬＤＤ(Lightly Doped Drain）あ
るいは、オフセット構造をとるためのマスクとなってい
る。Step (c): The pattern of the gate electrode film 33 is formed by photolithography and etching. At this time, in the pixel portion TFT 15, the pattern 33 of the first insulating film serves as a mask for taking an LDD (Lightly Doped Drain) or an offset structure.
【００２８】本実施例では、ＬＤＤ構造を製造するプロ
セスを以下に述べる。In this example, the process for manufacturing the LDD structure is described below.
【００２９】工程（ｄ）：ＥＣＲプラズマＣＶＤ法によ
り、例えばＳｉＯ2 からなる第２のゲート絶縁膜３４を
７００Ａ被着する。このとき、ｎ型ＴＦＴ１５、２１と
ｐ型ＴＦＴ２２では、ゲート絶縁膜膜厚、およびゲート
絶縁膜とｐ−Ｓｉとの界面数が異なっている。すなわ
ち、ｐ型ＴＦＴ２２では第２のゲート絶縁膜３４のみで
あり、ｎ型ＴＦＴ１５、２１ではこれに第１のゲート絶
縁膜３３が付加される。Step (d): A second gate insulating film 34 made of, for example, SiO 2 is deposited by 700 A by ECR plasma CVD method. At this time, the n-type TFTs 15 and 21 and the p-type TFT 22 differ in the thickness of the gate insulating film and the number of interfaces between the gate insulating film and p-Si. That is, the p-type TFT 22 has only the second gate insulating film 34, and the n-type TFTs 15 and 21 have the first gate insulating film 33 added thereto.
【００３０】工程（ｅ）：この第２のゲート絶縁膜３４
上にスパッタリング法により、Ｃｒ、ＭｏＴａ等の金属
膜を被着し、リソグラフィーおよびエッチングにより、
パターニングしてゲート電極３５を形成する。Step (e): This second gate insulating film 34
A metal film of Cr, MoTa or the like is deposited on the top by a sputtering method, and by lithography and etching,
Patterning is performed to form the gate electrode 35.
【００３１】工程（ｆ）：その後、ｐ型ＴＦＴ２２だ
け、レジスト、感光性ポリイミド等で保護膜３６を形成
し、ｎ型ＴＦＴ１５、２１にゲート電極３５をマスクと
して自己整合的にリンを注入して、ｎ型ＴＦＴのソース
・ドレイン部を形成する。このとき、スイッチングＴＦ
Ｔ１５のソース・ドレイン部は図３に示すように、リン
の高濃度注入（ｎ+ ）領域と低濃度注入（ｎ- ）領域が
自動的に形成される。Step (f): After that, a protective film 36 is formed only on the p-type TFT 22 with a resist, a photosensitive polyimide or the like, and phosphorus is injected into the n-type TFTs 15 and 21 in a self-aligned manner using the gate electrode 35 as a mask. , Source / drain portions of the n-type TFT are formed. At this time, switching TF
In the source / drain portion of T15, as shown in FIG. 3, a high concentration implantation (n + ) region and a low concentration implantation (n − ) region of phosphorus are automatically formed.
【００３２】工程（ｇ）：マスクをエッチングし、今度
はｐ型ＴＦＴ２２だけ、レジスト、感光性ポリイミド等
で保護膜３７を形成し、ｐ型ＴＦＴにゲート電極をマス
クとして自己整合的にリンを注入して、ｐ型ＴＦＴのソ
ース・ドレイン部（ｐ+ 領域）を形成する。Step (g): The mask is etched, only the p-type TFT 22 is formed with a protective film 37 of resist, photosensitive polyimide, etc., and phosphorus is self-alignedly injected into the p-type TFT using the gate electrode as a mask. Then, the source / drain portions (p + regions) of the p-type TFT are formed.
【００３３】工程（ｈ）：その後、マスクをエッチング
して、ＰＥＣＶＤ法によりＳｉＯ2を層間絶縁膜３８と
して被着し、レーザアニーリング法により、ソース・ド
レインの活性化を行う。Step (h): After that, the mask is etched, SiO 2 is deposited as an interlayer insulating film 38 by the PECVD method, and the source / drain is activated by the laser annealing method.
【００３４】工程（ｉ）：フォトリソグラフィーおよ
び、エッチングによりコンタクトホールを開孔し、スパ
ッタリング法等によりＡｌ等金属膜を被着後、フォトリ
ソグラフィーおよび、エッチングによりソース・ドレイ
ン電極３９を形成し、その後、ＩＴＯ膜１４を被着し、
画素電極のパターンとしてアクティブマトリクス基板が
完成する。Step (i): A contact hole is opened by photolithography and etching, a metal film such as Al is deposited by a sputtering method, etc., and then source / drain electrodes 39 are formed by photolithography and etching, and thereafter. , Deposit the ITO film 14,
An active matrix substrate is completed as a pattern of pixel electrodes.
【００３５】なお、本発明は、上述の実施例に限られる
ことなく、例えば、第２のゲート絶縁膜をＳｉＮｘとす
るように、第１のゲート絶縁膜と第２のゲート絶縁膜の
ゲート絶縁膜の材質を変えても良い。また、ｐ型、ｎ型
ＴＦＴのゲート絶縁膜膜厚を変えるのみならず、液晶表
示画素部ＴＦＴと駆動部ＴＦＴのゲート絶縁膜膜厚を変
えることにより駆動部ＴＦＴと画素部ＴＦＴのしきい値
電圧を異ならすことにも用いることができる。また、画
素部ＴＦＴにおいて、プラズマの加速電圧、ゲート絶縁
膜膜厚を変えることにより、オフセット型ＴＦＴも作製
することができる。The present invention is not limited to the above-described embodiment, but the gate insulation of the first gate insulation film and the second gate insulation film is made so that the second gate insulation film is SiNx, for example. The material of the film may be changed. In addition to changing the gate insulating film thickness of the p-type and n-type TFTs, by changing the gate insulating film thickness of the liquid crystal display pixel unit TFT and the driving unit TFT, the threshold value of the driving unit TFT and the pixel unit TFT It can also be used to vary the voltage. Further, in the pixel portion TFT, an offset type TFT can be manufactured by changing the plasma accelerating voltage and the gate insulating film thickness.
【００３６】[0036]
【発明の効果】以上の述べたように、本発明の構造の半
導体装置では、ゲート絶縁膜を積層数の違いにより、ゲ
ート絶縁膜膜厚を異にするため、固定電荷密度が異なる
ＴＦＴを製造することができ、移動度を低下させること
なくＴＦＴのしきい値を制御することが可能になる。As described above, in the semiconductor device having the structure of the present invention, since the thickness of the gate insulating film is different depending on the number of stacked gate insulating films, a TFT having a different fixed charge density is manufactured. Therefore, the threshold value of the TFT can be controlled without lowering the mobility.
【図１】本発明の一実施例の液晶表示装置の概略断面
図。FIG. 1 is a schematic cross-sectional view of a liquid crystal display device according to an embodiment of the present invention.
【図２】図１のＴＦＴの要部を示す断面図。FIG. 2 is a sectional view showing a main part of the TFT of FIG.
【図３】図２のさらに要部を拡大して示す断面図。FIG. 3 is a cross-sectional view showing an enlarged main part of FIG.
【図４】本発明の一実施例のアクティブマトリクス基板
に形成する回路を示す回路略図。FIG. 4 is a schematic circuit diagram showing a circuit formed on an active matrix substrate according to an embodiment of the present invention.
【図５】本発明の実施例の製造工程を説明する断面図。FIG. 5 is a cross-sectional view illustrating the manufacturing process of the embodiment of the present invention.
１１、１２…基板 １３…透明共通基板 １４…画素電極 １５…スイッチングＴＦＴ １６…配線層 １７…液晶層 ２０…ＣＭＯＳ回路 ２１…ｎ型ｐ−ＳｉＴＦＴ ２２…ｐ型ｐ−ＳｉＴＦＴ ３３…第１のゲート絶縁膜 ３４…第２のゲート絶縁膜 ３５…ゲート電極 ３９…ソース・ドレイン電極 11, 12 ... Substrate 13 ... Transparent common substrate 14 ... Pixel electrode 15 ... Switching TFT 16 ... Wiring layer 17 ... Liquid crystal layer 20 ... CMOS circuit 21 ... N-type p-SiTFT 22 ... P-type p-SiTFT 33 ... First gate Insulating film 34 ... Second gate insulating film 35 ... Gate electrode 39 ... Source / drain electrode
Claims (1)
異なる２種類以上の多結晶半導体薄膜電界効果トランジ
スタを具備していることを特徴とする半導体装置。1. A semiconductor device comprising, on the same insulating substrate, two or more types of polycrystalline semiconductor thin film field effect transistors having different gate insulating film thicknesses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5404195A JPH08250742A (en) | 1995-03-14 | 1995-03-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5404195A JPH08250742A (en) | 1995-03-14 | 1995-03-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08250742A true JPH08250742A (en) | 1996-09-27 |
Family
ID=12959521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5404195A Pending JPH08250742A (en) | 1995-03-14 | 1995-03-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08250742A (en) |
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