JP2005079283A - Thin film semiconductor device and its manufacturing method, electro-optical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film semiconductor device that is capable of reducing an off-leak current, increasing an on-state current, and improving a breakdown voltage, a dynamic characteristic of current to voltage or the like, and reliability as a device, by reducing an electric field strength adjacent to a source/drain end of a channel area; and to provide its manufacturing method, an electro-optical device, and an electronic apparatus. <P>SOLUTION: A double gate TFT with an LDD structure is provided with a lower gate electrode 33, a lower gate insulating film 34, a semiconductor thin film 35, an upper gate insulating film 36 of first and second insulating layers 36a and 36b, an upper gate electrode 37, and an interlayer insulating film 38. The semiconductor thin film 35 is provided with a channel area 35a, a low-concentration source area 35b, a low-concentration drain area 35c, a high-concentration source area 35d, and a high-concentration drain area 35e; and an opening 39 is formed in a part corresponding to the central part of the channel area 35a of the first insulating layer 36a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film semiconductor device and a manufacturing method thereof, an electro-optical device, and an electronic apparatus, and more particularly to a technique capable of controlling an on-current and an off-leak current of a thin film semiconductor device having an LDD (Lightly Doped Drain) structure. Is.

As electro-optical devices such as liquid crystal devices, electroluminescence (EL) devices, plasma displays, etc., each dot is provided with a TFT, which is a thin film semiconductor device, in order to drive a large number of dots arranged in a matrix. An active matrix type electro-optical device is known.
In addition, as a TFT used in such applications, a lower insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and an upper insulating film are sequentially stacked on a transparent substrate, and the lower insulating film is interposed in the channel region. There is known a double gate TFT having a structure in which a lower gate electrode is disposed oppositely and an upper gate electrode is disposed oppositely via an upper insulating film (see, for example, Patent Documents 1 to 3).

In this double gate TFT, a patterned lower gate electrode, a lower insulating film, a semiconductor thin film having a channel region and source / drain regions, and an upper insulating film are sequentially laminated on a transparent substrate, and a resist film is formed on the upper insulating film. The resist film is patterned by exposing from the back side of the transparent substrate using the lower insulating film as a mask, and then an upper gate electrode is formed on the exposed / removed portion of the resist film. Yes.
In this double gate TFT, the lower gate electrode and the upper gate electrode have the same size, thereby reducing the parasitic capacitance between the gate and the source / drain.

  On the other hand, as another TFT used in such applications, a lower insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and an upper insulating film are sequentially stacked on a transparent substrate, and the upper insulating film is formed on the channel region. An LDD structure in which a gate electrode is opposed to each other, and a high concentration region and a relatively low concentration region (LDD region) having a relatively high impurity concentration are formed in the source region and the drain region, respectively. TFT is known (for example, see Patent Document 4).

In this LDD structure TFT, a lower insulating film, a patterned semiconductor thin film, and an upper insulating film are sequentially laminated on a transparent substrate, and a gate electrode is formed on the upper insulating film and in a portion corresponding to the channel region of the semiconductor thin film. And forming a low concentration source region and drain region and a channel region into which no impurity ions are implanted by implanting low concentration impurity ions into the semiconductor thin film using the gate electrode as a mask. Forming a high-concentration source region and drain region by implanting high-concentration impurity ions into the low-concentration source region and drain region using the insulating film as a mask. Thereafter, an interlayer insulating film is formed on the entire surface.
In this TFT having an LDD structure, a low concentration source region and a high concentration source region are formed on one side of the channel region, and a low concentration drain region and a high concentration drain region are formed on the other side. It has excellent dynamic characteristics such as current-voltage characteristics.
JP 58-115850 A JP-A-63-246874 Japanese Patent Laid-Open No. 08-241997 Japanese Patent Laid-Open No. 06-250212

By the way, in the above-described double gate TFT, the thickness of the upper insulating film is uniform. Therefore, in the channel region, it is caused by the electric field strength in the vicinity of the source region and the drain region, that is, in the vicinity of the source / drain edges. There was a problem that off-leakage current was large.
As described above, when the off-leakage current is large, the power consumption is increased, the resistance to voltage is lowered, and the reliability may be lowered.
Further, although the above-mentioned LDD structure TFT has excellent dynamic characteristics such as withstand voltage and current-voltage characteristics, there is a problem that a large on-current cannot be obtained.
When a large on-current cannot be obtained, it is difficult to increase the dynamic characteristics of the TFT, and therefore, it is difficult to drive at a high speed.

  The present invention has been made in view of the above circumstances, and it is possible to reduce off-leakage current by relaxing the electric field strength in the periphery of the channel region, that is, in the vicinity of the source / drain ends. Power can be reduced, voltage tolerance can be improved, large on-current can be obtained, dynamic characteristics such as withstand voltage, current-voltage characteristics, and device reliability can be improved. An object of the present invention is to provide a thin film semiconductor device that can be manufactured, a manufacturing method thereof, an electro-optical device, and an electronic apparatus.

  As a result of diligent research, the inventors of the present invention have made the insulating film formed in the upper layer of the semiconductor thin film thin in the portion corresponding to the central portion of the channel region of the semiconductor thin film and thicken the portion corresponding to the peripheral portion of the channel region. Thus, the electric field strength in the peripheral portion of the channel region, that is, in the vicinity of the source / drain end can be relaxed, and therefore the off-leakage current can be reduced, resulting in the reduction in power consumption and The inventors have found that resistance and reliability can be improved and have reached the present invention.

  That is, in the thin film semiconductor device of the present invention, a first insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and a second insulating film are sequentially stacked, and the first insulating film is formed in the channel region. The first gate electrode is disposed oppositely via the second insulating film, the second gate electrode is disposed oppositely via the second insulating film, and the source region and the drain region each have a relatively low impurity concentration. In the thin film semiconductor device in which a high concentration region and a low concentration region having a relatively low impurity concentration are formed, the second insulating film has a thickness corresponding to a central portion of the channel region. The region is thinner than the thickness of the portion corresponding to the vicinity of each of the source region and the drain region.

  In this thin film semiconductor device, the second insulating film is formed such that the thickness of the portion corresponding to the central portion of the channel region is smaller than the thickness of the portion corresponding to the vicinity of the source / drain end. When a voltage is applied to the channel region by the first and second gate electrodes, the electric field strength in the vicinity of the source / drain ends is relaxed, so that off-leakage current can be reduced. In addition, withstand voltage characteristics such as resistance to gate voltage or resistance to drain voltage are improved, and reliability can be improved.

  In the thin film semiconductor device, the second insulating film includes a first insulating layer formed on the semiconductor thin film and a second insulating layer formed on the first insulating layer. If an opening having the same size as the first gate electrode is formed at a position corresponding to the channel region of the first insulating layer, the electric field strength in the vicinity of the source / drain end is As a result, the off-leakage current can be reduced and the on-current of the channel region can be increased.

  In the thin film semiconductor device, the second insulating film includes a first insulating layer formed on the semiconductor thin film and a second insulating layer formed on the first insulating layer. If an opening narrower than the first gate electrode is formed at a position corresponding to the channel region of the first insulating layer, the electric field strength in the vicinity of the source / drain end is reduced, The off-leakage current can be greatly reduced and the on-current of the channel region can be increased.

  In the thin film semiconductor device, the second insulating film includes a first insulating layer formed on the semiconductor thin film and a second insulating layer formed on the first insulating layer. If an opening wider than the first gate electrode is formed at a position corresponding to the channel region of the first insulating layer, the electric field strength in the vicinity of the source / drain end is reduced, The off-leak current can be reduced and the on-current of the channel region can be greatly increased.

  In the method for manufacturing a thin film semiconductor device of the present invention, a first insulating film, a semiconductor thin film having a channel region, a source region and a drain region, and a second insulating film composed of first and second insulating layers are sequentially stacked, A first gate electrode is disposed opposite to the channel region via the first insulating film, and a second gate electrode is disposed opposite to the channel region via the second insulating film. A method of manufacturing a thin film semiconductor device in which a high-concentration region having a relatively high impurity concentration and a low-concentration region having a relatively low impurity concentration are formed in each region. Forming a first gate electrode having conductivity, a step of sequentially laminating a first insulating film and a semiconductor thin film on the translucent substrate including the first gate electrode, Positive photoregis Applying the photoresist, exposing the photoresist from the back side of the translucent substrate using the first gate electrode as a mask, patterning the photoresist into a predetermined shape, and using the patterned photoresist as a mask, the semiconductor A step of injecting a low-concentration impurity into the thin film, a step of forming a first insulating layer on the first insulating film including the patterned photoresist and the semiconductor thin film, and the patterned photo by a lift-off method. Removing the resist and the first insulating layer on the photoresist, and opening the portion corresponding to the center of the channel region of the semiconductor thin film of the first insulating layer; and the remaining first Forming a second insulating layer on the semiconductor thin film including the insulating layer; and forming a second gate wider than the first gate electrode on the second insulating layer. Forming an electrode, a second mask gate electrode, and having a implanting high concentration impurities into the semiconductor thin film.

In this method of manufacturing a thin film semiconductor device, a positive photoresist is applied on the semiconductor thin film, and then the photoresist is exposed from the back side of the translucent substrate using the first gate electrode as a mask to form a predetermined shape. Then, a low-concentration impurity is implanted into the semiconductor thin film using the patterned photoresist as a mask, and a first insulating layer is formed on the first insulating film including the patterned photoresist and the semiconductor thin film. Next, the patterned photoresist and the first insulating layer on the photoresist are removed by a lift-off method, and a portion corresponding to the central portion of the channel region of the semiconductor thin film of the first insulating layer Then, a second insulating layer is formed on the semiconductor thin film including the remaining first insulating layer.
In this case, if the exposure conditions of the positive photoresist, for example, the light intensity and the exposure time are changed, the cured region of the positive photoresist changes, and the size of the patterning portion of the positive photoresist also changes.

For example, when the light intensity and the exposure time are appropriate, the positive photoresist is exposed except for the region corresponding to the first gate electrode. Therefore, the cured region of the positive photoresist is The size is the same as that of the first gate electrode. Therefore, when the positive photoresist and the first insulating layer on the positive photoresist are removed by a lift-off method, the opening of the first insulating layer has the same size as the first gate electrode. .
When at least one of the light intensity and the exposure time is increased, the amount of light that wraps around the back side of the mask increases due to overexposure, and the hardened region of the positive photoresist becomes narrower than the first gate electrode. Therefore, when the positive photoresist and the first insulating layer on the positive photoresist are removed by a lift-off method, the opening of the first insulating layer is narrower than the first gate electrode. .
Further, when at least one of the light intensity and the exposure time is reduced, the exposure is insufficient, so that the amount of light in the peripheral portion of the mask is reduced and the hardened region of the positive photoresist becomes wider than the first gate electrode. Therefore, when the positive photoresist and the first insulating layer on the positive photoresist are removed by a lift-off method, the opening of the first insulating layer is wider than the first gate electrode. .

As described above, the thickness of the portion corresponding to the central portion of the channel region of the semiconductor thin film has the second insulating film composed of the first and second insulating layers thinner than the thickness corresponding to the vicinity of the source / drain end. A thin film semiconductor device can be manufactured.
The size of the opening of the first insulating layer can be adjusted by changing the exposure condition of the positive photoresist.
Therefore, the electric field strength in the vicinity of the source / drain ends can be relaxed, the off-leak current can be reduced, and a thin film semiconductor device capable of greatly increasing the on-current of the channel region can be easily manufactured.

  According to another method of manufacturing a thin film semiconductor device of the present invention, a first insulating film, a semiconductor thin film having a channel region, a source region and a drain region, and a second insulating film composed of a first insulating layer and a second insulating layer are sequentially stacked. A first gate electrode is disposed opposite to the channel region via the first insulating film, and a second gate electrode is disposed opposite to the channel region via the second insulating film; And a drain region in which a high concentration region with a relatively high impurity concentration and a low concentration region with a relatively low impurity concentration are formed, respectively, on a translucent substrate Forming a first light-shielding gate electrode; sequentially laminating a first insulating film and a semiconductor thin film on the light-transmitting substrate including the first gate electrode; and the semiconductor thin film. On top of the positive photo Applying a strike, exposing the photoresist from the back side of the translucent substrate using the first gate electrode as a mask, patterning the photoresist into a predetermined shape, and applying the patterned photoresist and semiconductor thin film Forming a first insulating layer on the first insulating film including the step of implanting low-concentration impurities into the semiconductor thin film using the patterned photoresist and the first insulating layer as a mask; Removing the patterned photoresist and the first insulating layer on the photoresist by a method, and forming a portion of the first insulating layer corresponding to the central portion of the channel region of the semiconductor thin film as an opening Forming a second insulating layer on the semiconductor thin film including the remaining first insulating layer; and forming the first gate electrode on the second insulating layer. Forming a wider second gate electrode, a second mask gate electrode, and having a implanting high concentration impurities into the semiconductor thin film.

In this method of manufacturing a thin film semiconductor device, a positive photoresist is applied on the semiconductor thin film, and then the photoresist is exposed from the back side of the translucent substrate using the first gate electrode as a mask to form a predetermined shape. Then, a first insulating layer is formed on the first insulating film including the patterned photoresist and the semiconductor thin film, and the patterned photoresist and the first insulating layer are used as a mask. A low concentration impurity is implanted into the semiconductor thin film, and then the patterned photoresist and the first insulating layer on the photoresist are removed by a lift-off method, and the channel of the semiconductor thin film in the first insulating layer is removed. A portion corresponding to the central portion of the region is used as an opening, and then a second insulating layer is formed on the semiconductor thin film including the remaining first insulating layer. To form.
Also in this case, just like the above-described manufacturing method of the thin film semiconductor device of the present invention, if the exposure conditions of the positive photoresist, for example, the light intensity and the exposure time are changed, the cured region of the positive photoresist changes, The size of the patterning portion of the positive photoresist also changes.

Also in this manufacturing method, the thickness of the portion corresponding to the central portion of the channel region of the semiconductor thin film is more than the thickness of the portion corresponding to the vicinity of the source / drain ends, just like the manufacturing method of the thin film semiconductor device of the present invention described above. A thin film semiconductor device having a second insulating film made of thin first and second insulating layers can be manufactured.
The size of the opening of the first insulating layer can be adjusted by changing the exposure condition of the positive photoresist.
Therefore, the electric field strength in the vicinity of the source / drain ends can be relaxed, the off-leak current can be reduced, and a thin film semiconductor device capable of greatly increasing the on-current of the channel region can be easily manufactured.

  According to still another method of manufacturing a thin film semiconductor device of the present invention, a first insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and a second insulating film are sequentially stacked. The first gate electrode is disposed opposite to the first insulating film, and the second gate electrode is disposed opposite to the second insulating film. The source region and the drain region each have an impurity concentration. A method of manufacturing a thin film semiconductor device in which a high concentration region having a relatively high concentration and a low concentration region having a relatively low impurity concentration are formed, wherein the first gate having a light shielding property is formed on a light transmitting substrate A step of forming an electrode; a step of sequentially laminating a first insulating film and a semiconductor thin film on the translucent substrate including the first gate electrode; and applying a positive photoresist on the semiconductor thin film. Process, Exposing the positive photoresist from the back side of the translucent substrate using the first gate electrode as a mask and patterning the positive photoresist, and patterning the semiconductor thin film using the patterned positive photoresist as a mask A step of implanting low-concentration impurities, a step of forming a second insulating film on the first insulating film including the patterned photoresist and semiconductor thin film, and a negative type on the second insulating film A step of applying a photoresist, a step of exposing the negative photoresist from the back side of the translucent substrate using the first gate electrode as a mask, and patterning the negative photoresist, and a pattern of the patterned negative photo Using the resist as a mask, the second insulating film is selectively removed to correspond to the central portion of the channel region of the semiconductor thin film of the second insulating film Forming the thickness of the portion to be thinner than other portions, removing the negative photoresist, and forming a second gate electrode wider than the first gate electrode on the second insulating film And a step of implanting high-concentration impurities into the semiconductor thin film using the second gate electrode as a mask.

In this method of manufacturing a thin film semiconductor device, a positive photoresist is applied onto a semiconductor thin film, and then the positive photoresist is exposed from the back surface side of the translucent substrate using the first gate electrode as a mask. Then, a low-concentration impurity is implanted into the semiconductor thin film using the patterned positive photoresist as a mask, and then on the first insulating film including the patterned photoresist and the semiconductor thin film. A second insulating film is formed, a negative photoresist is applied on the second insulating film, and the negative photoresist is exposed from the rear surface side of the translucent substrate using the first gate electrode as a mask. Then, the second insulating film is selectively removed using the patterned negative photoresist as a mask. , The thickness of the portion corresponding to the central portion of the channel region of the semiconductor thin film of the second insulating film is thinner than the thickness of other than this portion.
In this case, if the exposure conditions of the negative photoresist, for example, the light intensity and the exposure time are changed, the cured region of the negative photoresist changes, and the size of the patterning portion of the negative photoresist also changes.

For example, when the light intensity and the exposure time are appropriate, the negative photoresist is exposed except for the region corresponding to the first gate electrode. Is the same size as the first gate electrode. Therefore, when this negative photoresist is used as a mask, the region of the second insulating film to be selectively removed has the same size as the first gate electrode.
When at least one of the light intensity and the exposure time is increased, the amount of light that wraps around the back side of the mask increases due to overexposure, and the uncured region of the negative photoresist becomes narrower than the first gate electrode. Therefore, the non-cured region of the negative photoresist that becomes the opening of the mask is narrower than the first gate electrode. Therefore, when this negative photoresist is used as a mask, the region of the second insulating film to be selectively removed is narrower than that of the first gate electrode.
Further, when at least one of the light intensity and the exposure time is reduced, the amount of light in the peripheral portion on the back side of the mask is reduced due to insufficient exposure, and the uncured region of the negative photoresist is wider than the first gate electrode. Become. Therefore, the non-cured region of the negative photoresist that becomes the opening of the mask is wider than the first gate electrode. Therefore, when this negative photoresist is used as a mask, the region of the second insulating film to be selectively removed is wider than the first gate electrode.

As described above, a thin film semiconductor device having the second insulating film in which the thickness of the portion corresponding to the central portion of the channel region of the semiconductor thin film is thinner than the thickness of the portion corresponding to the vicinity of the source / drain ends can be manufactured.
The size of the thin portion on the plane can be adjusted by changing the exposure conditions of the negative photoresist.
Therefore, the electric field strength in the vicinity of the source / drain ends can be relaxed, the off-leakage current can be reduced, and a thin film semiconductor device with improved breakdown voltage and reliability can be easily manufactured.

The electro-optical device of the present invention includes the thin film semiconductor device of the present invention.
In the electro-optical device according to the present invention, the provision of the thin film semiconductor device according to the present invention improves the voltage resistance of the thin film semiconductor device and the reliability as a device. An optical device can be provided. Further, by providing a thin film semiconductor device with a small off-leakage current as in the present invention, an electro-optical device with low power consumption can be provided.

An electronic apparatus according to the present invention includes the electro-optical device according to the present invention.
In the electronic apparatus of the present invention, by providing the electro-optical device of the present invention, the pressure resistance and reliability of the electro-optical device are improved. Therefore, an electronic apparatus having improved pressure resistance and reliability is provided. Can do. Furthermore, an electro-optical device with low power consumption can be provided.

Embodiments according to the present invention will be described in detail. Each example will be described with reference to the drawings. In each figure, the scale of each layer and each member is made different so that each layer and each member can be recognized on the drawing. is there.
Each of the examples shows embodiments of the present invention, and the present invention is not limited to these embodiments, and can be arbitrarily changed within the scope of the technical idea of the present invention. .

The structure of the electro-optical device according to the first embodiment of the present invention will be described with reference to FIGS. In this embodiment, an active matrix transmissive liquid crystal device (electro-optical device) using a double gate TFT (thin film semiconductor device) having an LDD structure as a switching element will be described as an example.
FIG. 1 is an equivalent circuit diagram of switching elements, signal lines and the like in a plurality of dots arranged in a matrix constituting the image display area of the liquid crystal device of this embodiment, and FIG. 2 is a diagram showing data lines, scanning lines, pixel electrodes and the like. 3 is an enlarged plan view showing one dot of the formed TFT array substrate, FIG. 3 is a cross-sectional view showing the structure of the liquid crystal device of this embodiment, and is a cross-sectional view taken along the line AA ′ of FIG. 4 is a cross-sectional view showing a double gate TFT having an LDD structure. Note that FIG. 3 illustrates the case where the upper side in the drawing is the light incident side and the lower side in the drawing is the viewing side (observer side). Moreover, in each figure, in order to make each layer and each member the size which can be recognized on drawing, the scale is varied for every layer and each member.

  In the liquid crystal device of the present embodiment, as shown in FIG. 1, a plurality of dots arranged in a matrix that forms an image display area are pixel electrodes 9 and switching elements for controlling the pixel electrodes 9. A double gate TFT (thin film semiconductor device) 30 having an LDD structure is formed, and a data line 6 a to which an image signal is supplied is electrically connected to the source of the TFT 30. Image signals S1, S2,..., Sn to be written to the data line 6a are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 6a.

  Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the plurality of scanning lines 3a in a pulse-sequential manner at a predetermined timing. Further, the pixel electrode 9 is electrically connected to the drain of the TFT 30, and by turning on the TFT 30 as a switching element for a certain period, the image signals S1, S2,. Write at the timing.

  A predetermined level of image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9 is held for a certain period with the common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the retained image signal from leaking, a storage capacitor 60 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode.

  As shown in FIG. 3, the liquid crystal device of this embodiment is arranged so as to face each other with a liquid crystal layer 50 interposed therebetween, a TFT array substrate 10 on which the TFT 30 and the pixel electrode 9 are formed, and a counter substrate on which the common electrode 21 is formed. 20 and is schematically configured.

Hereinafter, the planar structure of the TFT array substrate 10 will be described with reference to FIG.
A plurality of rectangular pixel electrodes 9 are provided in a matrix on the TFT array substrate 10, and data lines 6 a, scanning lines 3 a, and capacitor lines 3 b are provided along the vertical and horizontal boundaries of each pixel electrode 9. ing. In the present embodiment, each pixel electrode 9 and a region where the data line 6a, the scanning line 3a, etc. arranged so as to surround each pixel electrode 9 are formed are one dot.

  The data line 6 a is electrically connected to the source region 35 x of the semiconductor thin film 35 made of polycrystalline silicon constituting the TFT 30 through the contact hole 13, and the pixel electrode 9 is connected to the drain region of the semiconductor thin film 35. It is electrically connected to 35y through the contact hole 15, the source line 6b, and the contact hole 14. Further, a part of the scanning line 3 a is widened so as to face the channel region 35 a of the semiconductor thin film 35, and the widened part of the scanning line 3 a functions as the lower gate electrode 33 and the upper gate electrode 37. Hereinafter, in the scanning line 3a, a portion functioning as a gate electrode is simply referred to as a “gate electrode” and is denoted by reference numeral 3c. Further, the semiconductor thin film 35 constituting the TFT 30 extends to a portion facing the capacitor line 3b, and a storage capacitor (storage capacitor element) having the extended portion 35f as a lower electrode and the capacitor line 3b as an upper electrode. 60 is formed.

Next, the cross-sectional structure of the liquid crystal device of this embodiment will be described with reference to FIG.
The TFT array substrate 10 is mainly composed of a substrate body (translucent substrate) 10A made of a translucent material such as glass, a pixel electrode 9, a TFT 30, and an alignment film 12 formed on the surface of the liquid crystal layer 50 side. The counter substrate 20 is mainly composed of a substrate body 20A made of a translucent material such as glass, a common electrode 21 and an alignment film 22 formed on the surface of the liquid crystal layer 50 side.

Specifically, in the TFT array substrate 10, a lower gate insulating film (first insulating film) 34 that also serves as a base protective film made of an insulating material such as a silicon oxide film is formed immediately above the substrate body 10A. Further, a pixel electrode 9 made of a transparent conductive thin film such as indium tin oxide (ITO) is provided on the surface of the substrate body 10A on the liquid crystal layer 50 side, and each pixel electrode 9 is placed at a position adjacent to each pixel electrode 9. A pixel switching TFT 30 for switching control is provided.
In this embodiment, since the transmissive liquid crystal device is taken as an example, the pixel electrode 9 is made of a transparent conductive thin film such as ITO. In the reflective liquid crystal device, the pixel electrode 9 is made of a metal thin film such as Al, The reflective transflective liquid crystal device has a laminated structure of a transparent conductive thin film such as ITO and a metal thin film such as Al.

  This pixel switching TFT 30 is an n-channel or p-channel LDD double-gate TFT (Thin-Film Transistor) (thin film semiconductor device), as shown in FIG. (Translucent substrate) A lower gate electrode (first gate) made of a conductive film having a predetermined light-shielding property such as aluminum, tantalum, molybdenum, titanium, chromium, or an alloy containing these metals as a component on 10A. Electrode) 33, lower gate insulating film (first insulating film) 34 made of silicon oxide, silicon nitride, etc., island-like semiconductor thin film 35 made of polycrystalline silicon, upper gate insulating film made of silicon oxide, silicon nitride, etc. (Second insulating film) 36, and has light shielding properties such as aluminum, tantalum, molybdenum, titanium, chromium, or an alloy containing these metals as components. Upper gate electrode (second gate electrode) 37 made of a conductive film of constant pattern, silicon oxide, an interlayer insulating film 38 made of silicon nitride or the like is laminated.

The semiconductor thin film 35 includes a channel region 35a and a source region 35x and a drain region 35y formed on both sides of the channel region 35a.
The source region 35x includes a low concentration source region 35b having a relatively low impurity concentration on the channel region 35a side, and a high concentration source region 35d having a relatively high impurity concentration formed adjacent to the low concentration source region 35b. And. The drain region 35y includes a low concentration drain region 35c having a relatively low impurity concentration on the channel region 35a side, and a high concentration drain region having a relatively high impurity concentration formed adjacent to the low concentration drain region 35c. 35e.

  A scanning line 3 a (gate electrode 3 c) is formed on the upper gate insulating film 37, and in this embodiment, the side surface of the gate electrode 3 c is substantially perpendicular to the surface of the upper gate insulating film 36. Further, in the semiconductor thin film 35, a region facing the lower gate electrode 33 via the lower gate insulating film 34 and a region facing the upper gate electrode 37 via the upper gate insulating film 37 are divided into the lower gate electrode 33 and the upper gate electrode 33. A channel region 35 a is formed in which a channel is formed by an electric field from each of the gate electrodes 37.

A lower gate electrode 33 is disposed opposite to the channel region 35a via a lower gate insulating film 34, and an upper gate electrode 37 is disposed opposite to the channel region 35a via an upper gate insulating film 36.
The upper gate insulating film 36 has a two-layer structure of a first insulating layer 36a and a second insulating layer 36b, and the first insulating layer 6a has an opening 39 in a portion corresponding to the central portion of the channel region 35a. Thus, the thickness of the portion of the upper gate insulating film 36 corresponding to the central portion of the channel region 35a is close to the source / drain ends of the channel region 35a, that is, in the vicinity of the low concentration source region 35b and the low concentration drain region 35c. It becomes thinner than the thickness of the corresponding part.

  An interlayer insulating film 38 made of a silicon oxide film or the like is formed on the substrate body 10A on which the scanning line 3a (gate electrode 3c) is formed. On the interlayer insulating film 38, the data line 6a and the source A line 6b is formed. The data line 6 a is electrically connected to the high concentration source region 35 d of the semiconductor thin film 35 through the contact hole 13 formed in the interlayer insulating film 38, and the source line 6 b is a contact formed in the interlayer insulating film 38. The hole 14 is electrically connected to the high concentration drain region 35 e of the semiconductor thin film 35.

A second interlayer insulating film 5 made of a silicon nitride film or the like is formed on the interlayer insulating film 38 on which the data line 6a and the source line 6b are formed. A pixel electrode is formed on the second interlayer insulating film 5. 9 is formed. The pixel electrode 9 is electrically connected to the source line 6 b through a contact hole 15 formed in the second interlayer insulating film 5.
Further, the scanning line 3a and the extending portion 35f (lower electrode) from the high concentration drain region 35e of the semiconductor thin film 35 are connected to the scanning line 3a via an insulating film (dielectric film) integrally formed with the upper gate insulating film 37. The capacitor line 3b formed in the same layer is disposed as an upper electrode so as to face each other, and a storage capacitor 60 is formed by the extended portion 35f and the capacitor line 3b.
An alignment film 12 for controlling the alignment of liquid crystal molecules in the liquid crystal layer 50 is formed on the outermost surface of the TFT array substrate 10 on the liquid crystal layer 50 side.

  On the other hand, in the counter substrate 20, light incident on the liquid crystal device is incident on at least the channel region 35a, the low concentration source region 35b, and the low concentration drain region 35c of the semiconductor thin film 35 on the surface of the substrate body 20A on the liquid crystal layer 50 side. A light shielding film 23 is formed to prevent this. A common electrode 21 made of ITO or the like is formed on almost the entire surface of the substrate body 20A on which the light shielding film 23 is formed, and the liquid crystal molecules in the liquid crystal layer 50 are formed on the liquid crystal layer 50 side. An alignment film 22 for controlling the arrangement is formed.

  In the TFT 30, the thickness of the upper gate insulating film 36 near the center portion of the channel region 35 a is thinner than the thickness of the channel region 35 a near the source / drain ends, so that the lower gate electrode 33 and the upper gate electrode 37 When a voltage is applied to the channel region 35a, the electric field is concentrated from the upper gate electrode 37 through the thin portion of the upper gate insulating film 36 near the center of the channel region 35a, and from the lower gate electrode 33 to the lower gate. It concentrates near the center of the channel region 35a via the insulating film 34. As a result, the electric field intensity in the peripheral portion of the channel region 35a, that is, in the vicinity of the source / drain ends, is relaxed.

As described above, according to the double gate TFT 30, the electric field strength in the vicinity of the source / drain end of the channel region 35a is relaxed, so that the off-leak current can be reduced, and further, the breakdown voltage and the reliability are improved. Can be made.
In addition, withstand voltage characteristics such as resistance to gate voltage or drain voltage can be improved, and reliability can be improved.
Further, since the lower gate electrode 33 and the upper gate electrode 37 are disposed opposite to each other below the channel region 35a, the channel structure can be a double channel structure having channels on the upper and lower sides. The current density per area can be increased, and the on-current can be increased.
In addition, since the LDD structure is employed, it is possible to improve withstand voltage properties such as resistance to gate voltage or resistance to drain voltage, and reliability can be improved.

FIG. 5 is a cross-sectional view showing an n-channel LDD structure double gate TFT (Thin-Film Transistor) (thin film semiconductor device) according to a second embodiment of the present invention.
This double gate TFT is different from the double gate TFT of the first embodiment in that, in the double gate TFT of the first embodiment, an opening 39 is simply formed at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a. In contrast, in the double gate TFT according to the second embodiment, an opening 71 having the same size as the lower gate electrode 33 is formed at a position corresponding to the center of the channel region 35a of the first insulating layer 36a. The other components are the same as those of the double gate TFT according to the first embodiment.

In this double gate TFT, the opening 71 having the same size as that of the lower gate electrode 33 is formed at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a. Therefore, the lower gate electrode 33 and the upper gate electrode 37 are formed. When a voltage is applied to the channel region 35a by the above, the electric field is concentrated from the upper gate electrode 37 to the vicinity of the center of the channel region 35a through the opening 71 of the first insulating layer 36a, and from the lower gate electrode 33 to the lower gate insulation. The film 34 is concentrated in the vicinity of the central portion of the channel region 35a.
As a result, the electric field strength in the vicinity of the source / drain end, which is the peripheral portion of the channel region 35a, is relaxed.

  Further, the lower gate electrode 33 is disposed below the channel region 35a and the upper gate electrode 37 is disposed above the channel region 35a, so that the channel structure becomes a double channel structure having channels on the upper and lower surfaces of the semiconductor thin film 35, respectively. As a result, the current density per unit area is increased, and the on-current is greatly increased.

Next, a method for manufacturing the double gate TFT will be described with reference to FIGS.
First, as shown in FIG. 6A, a substrate body 10A having translucency made of a glass substrate or the like whose surface is cleaned by ultrasonic cleaning or the like is prepared, and the entire surface of the substrate body 10A is formed by sputtering or the like. A conductive film 72 having a thickness of 10 to 500 nm having a light shielding property made of a metal such as aluminum, tantalum, molybdenum, titanium, or chromium, or an alloy containing any of these metals as a main component is formed. The film 72 is patterned by photolithography to form a light-shielding lower gate electrode 33 that is patterned into a predetermined shape. If the pattern edge of the lower gate electrode 33 is tapered to have a tapered shape, the coverage of the thin film on the lower gate electrode 33 is improved when a thin film is formed in a subsequent process.

Next, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) or the like is formed on the substrate main body 10A including the lower gate electrode 33 by a plasma CVD method or the like under a condition where the substrate temperature becomes 100 to 600 ° C. A lower gate insulating film 34 having a thickness of 10 to 50 nm is formed.
The raw material used in this film forming process includes a mixed gas of monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O), a mixed gas of disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ), tetra A mixed gas of ethoxysilane (TEOS: Si (OC ₂ H ₅ ) ₄ ) and oxygen (O ₂ ) is preferable.

Next, as shown in FIG. 6B, the lower gate insulating film 34 is made of amorphous silicon (a-Si) under the condition that the substrate temperature is 100 to 600 ° C. by plasma CVD or the like. An amorphous semiconductor thin film 73 having a thickness of 10 to 100 nm is formed.
Monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), and the like are suitable as raw materials used in this film forming process.
Next, the amorphous semiconductor thin film 73 is polycrystallized by irradiating it with laser light or the like to obtain a polycrystalline semiconductor thin film 74 made of polycrystalline silicon. In addition, a solid phase growth method in which the amorphous semiconductor thin film 73 is polycrystallized by annealing at about 400 to 700 ° C. may be used.
Next, the polycrystalline semiconductor thin film 74 is patterned by a photolithography method to form an island-shaped semiconductor thin film 35.

Next, as shown in FIG. 6C, a positive photoresist 76 is applied on the lower gate insulating film 34 including the semiconductor thin film 35, and the back surface side (lower portion) of the substrate body 10A using the lower gate electrode 33 as a mask. This photoresist 76 is exposed by irradiating light L from the opposite side of the gate electrode 33.
Next, the photoresist 76 is developed, and patterning of a predetermined shape is performed on the photoresist 76. As a result, as shown in FIG. 6D, the photoresist 76 is removed except for the island-shaped photoresist 76 a having the same size as the lower gate electrode 33.

Here, in order to form an island-shaped photoresist having the same size as that of the lower gate electrode 33 on the photoresist 76, the light intensity and exposure time of the light L are applied so that the photoresist 76 is appropriately exposed. Need to be controlled appropriately. As a result, the photoresist 76 is exposed except for the region corresponding to the lower gate electrode 33, and the cured region of the photoresist 76 has the same size as the lower gate electrode 33.
By developing the photoresist 76, an island-like photoresist 76a having the same size as the lower gate electrode 33 is formed on the photoresist 76.

Next, as shown in FIG. 6E, with the island-shaped photoresist 76a as a mask, the semiconductor thin film 35 has a low concentration at a dose of about 0.1 × 10 ¹³ to 10 × 10 ¹³ / cm ² from above. Impurity ions (phosphorus (P) ions or boron (B) ions) 77 are implanted.
By this low-concentration impurity ion 77 implantation, a portion of the semiconductor thin film 35 that is not covered with the photoresist 76a forms a low-concentration source region 35b and drain region 35c in a self-aligned manner with respect to the upper gate electrode 33. The portion covered with the photoresist 76a becomes the channel region 35a because the impurity ions 77 are not implanted.

Next, as shown in FIG. 7F, on the lower gate insulating film 34 including the island-like photoresist 76a and the semiconductor thin film 35, the substrate temperature is set to 100 to 600 ° C. by plasma CVD or the like. Then, a first insulating layer 36a having a thickness of 20 to 1000 nm made of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or the like is formed.
The raw material used in this film forming process is exactly the same as that of the lower gate insulating film 34.
As a result, the first insulating layer 36a is formed on the island-shaped photoresist 76a and on the semiconductor thin film 35 and the lower gate insulating film 34 except for the island-shaped photoresist 76a.

Next, the island-like photoresist 76a and the first insulating layer 36a on the island-like photoresist 76 are removed by a lift-off method.
As a result, as shown in FIG. 7G, the first insulating layer 36a having the opening 71 having the same shape as that of the island-shaped photoresist 76a is formed on the semiconductor thin film 35 and the lower gate insulating film 34. The Rukoto.
Next, as shown in FIG. 7H, silicon oxide (SiO ₂ ) is formed on the first insulating layer 36a including the semiconductor thin film 35 under a condition that the substrate temperature is 100 to 600 ° C. by plasma CVD or the like. A second insulating layer 36b made of silicon nitride (Si ₃ N ₄ ) or the like and having a thickness of 20 to 1000 nm is formed.
The raw material used in this film forming process is exactly the same as that of the lower gate insulating film 34. The first insulating layer 36a and the second insulating layer 36b constitute an upper gate insulating film 36.

  Next, as shown in FIG. 7 (i), a metal such as aluminum, tantalum, molybdenum, titanium, or chromium, or an alloy containing any of these metals as a main component is formed on the entire surface of the second insulating layer 36b by sputtering or the like. A conductive film 79 having a thickness of 10 to 500 nm is formed, and then the conductive film 79 is patterned by a photolithography method. The upper gate electrode 37 is wider than the upper gate electrode 37 and narrower than the semiconductor thin film 35. And

Next, high-concentration impurity ions (phosphorus (P) ions or boron (B) with a dose of about 0.1 × 10 ¹⁵ to 10 × 10 ¹⁵ / cm ² from above are formed on the semiconductor thin film 35 using the upper gate electrode 37 as a mask. ) Ion) 81 is implanted.
By this high concentration impurity ion 81 implantation, a portion of the semiconductor thin film 35 that is not covered with the upper gate electrode 37 is formed with a high concentration source region 35d and drain region 35e in a self-aligned manner with respect to the upper gate electrode 37. The The portion covered with the upper gate electrode 37 is not implanted with the high-concentration impurity ions 81, so that the low-concentration source region 35b, drain region 35c, and channel region 35a remain.

Next, as shown in FIG. 7J, silicon oxide (SiO ₂ ) is formed on the second insulating layer 36b including the upper gate electrode 37 under a condition that the substrate temperature is 100 to 600 ° C. by plasma CVD or the like. ), An interlayer insulating film 38 having a thickness of 100 to 1000 nm made of silicon nitride (Si ₃ N ₄ ) or the like is formed. The raw material used in this film forming process is exactly the same as that of the lower gate insulating film 34, the first insulating layer 36a, and the second insulating layer 36b.
Next, a photoresist (not shown) having a predetermined shape is formed on the interlayer insulating film 38, and the upper gate insulating film 36 and the interlayer insulating film 38 are dry-etched using the photoresist as a mask, and the upper gate insulating film 36 and A contact hole 13 reaching the high concentration source region 35d and a contact hole 14 reaching the high concentration drain region 35e are formed in the interlayer insulating film 38, respectively.

Next, a conductive film made of a metal such as aluminum, tantalum, molybdenum, titanium, or chromium, or an alloy containing at least one of these metals is formed on the entire surface of the interlayer insulating film 38 by a sputtering method or the like. This conductive film is patterned by photolithography to form a source electrode 6a and a drain electrode 6b.
As described above, a double-gate TFT having an n-channel or p-channel LDD structure can be manufactured.

  As described above, according to the double gate TFT having the LDD structure, the opening 71 having the same size as the lower gate electrode 33 is formed at the position corresponding to the center of the channel region 35a of the first insulating layer 36a. Therefore, when a voltage is applied to the channel region 35a by the lower gate electrode 33 and the upper gate electrode 37, the electric field is generated from the upper gate electrode 37 to the vicinity of the center of the channel region 35a through the opening 71 of the first insulating layer 36a. It concentrates and concentrates from the lower gate electrode 33 to the vicinity of the center of the channel region 35a through the lower gate insulating film 34, and the electric field strength in the vicinity of the source / drain ends of the channel region 35a is relaxed. Therefore, off-leakage current can be reduced, and further, pressure resistance and reliability can be improved.

Further, since the lower gate electrode 2 and the upper gate electrode 6 are disposed opposite to each other below the channel region 4a, the channel structure can be a double channel structure having channels on the upper and lower sides, respectively. Therefore, the current can be concentrated at the center of the channel region 4a, and the on-current can be increased.
In addition, since the LDD structure is employed, it is possible to improve withstand voltage properties such as resistance to gate voltage or resistance to drain voltage, and reliability can be improved.

  Further, according to this method for manufacturing a double gate TFT, a positive photoresist 76 is applied on the lower gate insulating film 34 including the semiconductor thin film 35, and light is applied from the back side of the substrate body 10A using the lower gate electrode 33 as a mask. L is irradiated, and the photoresist 76 is exposed to form an island-shaped photoresist 76a. A first insulating layer 36a is formed on the entire surface including the photoresist 76a, and the island-shaped photoresist 76a is formed by a lift-off method. Since the first insulating layer 36a on the island-shaped photoresist 76 is removed, an opening 71 having the same size as that of the lower gate electrode 33 is formed at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a. Can be formed, the off-leakage current can be reduced, the on-current can be increased, and the withstand voltage and reliability can be improved. The double gate TFT having an LDD structure that can, can be manufactured easily and at low cost.

FIG. 8 is a process diagram showing a method of manufacturing an n-channel type LDD structure double gate TFT according to the third embodiment of the present invention. By this manufacturing method, the n-channel LDD structure double gate according to the second embodiment described above. A TFT is obtained.
A method for manufacturing the double gate TFT will be described with reference to FIG.
This manufacturing method is exactly the same as that of the second embodiment until the island-shaped photoresist 76a having the same size as the lower gate electrode 33 is formed on the semiconductor thin film 35.

Thereafter, as shown in FIG. 8A, on the lower gate insulating film 34 including the island-like photoresist 76a and the semiconductor thin film 35, the substrate temperature is set to 100 to 600 ° C. by plasma CVD or the like. Then, a first insulating layer 36a having a thickness of 20 to 1000 nm made of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or the like is formed.
The raw material used in this film forming process is exactly the same as that of the lower gate insulating film 34.
As a result, the first insulating layer 36a is formed on the island-shaped photoresist 76a and on the semiconductor thin film 35 and the lower gate insulating film 34 except for the island-shaped photoresist 76a.

Next, as shown in FIG. 8B, the island-shaped photoresist 76a and the first insulating layer 36a are used as a mask, and the semiconductor thin film 35 has a thickness of about 0.1 × 10 ¹³ to 10 × 10 ¹³ / cm ² from above. A low concentration impurity ion (phosphorus (P) ion or boron (B) ion) 77 is implanted at a dose.
By this low concentration impurity ion 77 implantation, portions of the semiconductor thin film 35 that are covered only by the first insulating layer 36 a have low concentration source regions 35 b and drain regions 35 c in a self-aligned manner with respect to the upper gate electrode 33. The portion formed and covered with the photoresist 76a and the first insulating layer 36a becomes the channel region 35a because the impurity ions 77 are not implanted.

After the step of removing the island-like photoresist 76a and the first insulating layer 36a on the island-like photoresist 76 by the lift-off method, the manufacturing method of the double gate TFT of the second embodiment is exactly the same.
Also in this double gate TFT manufacturing method, the off-leakage current can be reduced, the on-current can be increased, and the withstand voltage and the reliability can be improved, just like the double gate TFT manufacturing method of the second embodiment. A double-gate TFT that can be manufactured can be easily manufactured at low cost.

FIG. 9 is a cross-sectional view showing an n-channel or p-channel LDD double-gate TFT (Thin-Film Transistor) (thin film semiconductor device) according to a fourth embodiment of the present invention.
This double gate TFT is different from the double gate TFT of the second embodiment in that, in the double gate TFT of the second embodiment, the lower gate electrode 33 and the position corresponding to the central portion of the channel region 35a of the first insulating layer 36a. Whereas the opening 71 having the same size is formed, in the double gate TFT of the fourth embodiment, the width is narrower than that of the lower gate electrode 33 at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a. The opening 91 is formed, and other components are the same as those of the TFT of the second embodiment.

  In this double gate TFT, an opening 91 having a width smaller than that of the lower gate electrode 33 is formed at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a, so that the lower gate electrode 33 and the upper gate electrode 37 are formed. When a voltage is applied to the channel region 35a by the above, the electric field is concentrated from the upper gate electrode 37 to the vicinity of the center of the channel region 35a through the opening 91 of the first insulating layer 36a, and from the lower gate electrode 33 to the lower gate insulation. The film 34 is concentrated in the vicinity of the central portion of the channel region 35a.

As a result, the electric field strength in the vicinity of the source / drain ends of the channel region 35a is relaxed, the off-leakage current is greatly reduced, and the pressure resistance and reliability are further improved.
Further, the lower gate electrode 33 is disposed below the channel region 35a, and the upper gate electrode 37 is disposed above the channel region 35a, so that the channel structure has a double channel structure having channels on the upper and lower sides, and current density per unit area is obtained. Increases and the on-current increases.

The manufacturing method of this double gate TFT is exactly the same as that of the second embodiment except for the exposure condition of the positive photoresist 76.
As for the exposure conditions, in Example 2 described above, appropriate exposure conditions that do not cause overexposure or underexposure are selected, whereas in this embodiment, “overexposure” that increases at least one of light intensity and exposure time is set. select. In the case of overexposure, as shown in FIG. 10, the amount of light L that wraps around the back side of the lower gate electrode 33 serving as a mask increases, and the cured region 92 of the positive photoresist 76 becomes narrower than the width of the lower gate electrode 33. . Therefore, the cured region 92 of the photoresist 76 that becomes the island-shaped positive photoresist 76 a becomes narrower than the width of the lower gate electrode 33.

  Therefore, by making the photoresist 76 overexposed, an island-shaped positive photoresist having a width smaller than that of the lower gate electrode 33 can be formed, and the first insulation is formed using the island-shaped positive photoresist. An opening 91 having a width smaller than that of the lower gate electrode 33 can be formed at a position corresponding to the central portion of the channel region 35a of the layer 36a.

  According to this double gate TFT, since the opening 91 having a width smaller than that of the lower gate electrode 33 is formed at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a, off-leakage current can be reduced. The on-current can be greatly increased, and the pressure resistance and reliability can be further improved.

FIG. 11 is a sectional view showing an n-channel or p-channel LDD structure double gate TFT (Thin-Film Transistor) (thin film semiconductor device) of Example 5 of the present invention.
This double gate TFT is different from the double gate TFT of the second embodiment in that, in the double gate TFT of the second embodiment, the lower gate electrode 33 and the position corresponding to the central portion of the channel region 35a of the first insulating layer 36a. Whereas the opening 71 having the same size is formed, the double gate TFT of the fifth embodiment is wider than the lower gate electrode 33 at a position corresponding to the center of the channel region 35a of the first insulating layer 36a. The opening 101 is formed, and the other components are the same as those of the TFT of the second embodiment.

In this double gate TFT, the electric field strength in the vicinity of the source / drain end of the channel region 35a is relaxed, the off-leakage current is greatly reduced, and the breakdown voltage and reliability are further improved.
Further, the lower gate electrode 33 is disposed below the channel region 35a, and the upper gate electrode 37 is disposed above the channel region 35a, so that the channel structure has a double channel structure having channels on the upper and lower sides, and current density per unit area is obtained. Increases and the on-current increases.

The manufacturing method of this double gate TFT is exactly the same as that of the second embodiment except for the exposure condition of the positive photoresist 76.
As for the exposure conditions, in Example 2 described above, appropriate exposure conditions that do not cause overexposure or underexposure are selected, whereas in this embodiment, “underexposure” that reduces at least one of light intensity and exposure time is reduced. select. In the case of underexposure, as shown in FIG. 12, the light L does not enter the back side of the lower gate electrode 33 serving as a mask, and the hardened region 92 of the positive photoresist 76 becomes wider than the width of the lower gate electrode 33. Therefore, the cured region 92 of the photoresist 76 that becomes the island-shaped positive photoresist 76 a is wider than the width of the lower gate electrode 33.

Therefore, by developing the underexposed photoresist 76, the uncured region of the photoresist 76 is removed, so that an island-like positive photoresist wider than the lower gate electrode 33 is formed. Become.
Also, regardless of the exposure conditions, by increasing the development processing time after exposure, or by increasing the temperature of the developing solution during development, the island shape is wider than the lower gate electrode 33. A positive type photoresist is formed. Any method may be used in the present invention.

  According to the double gate TFT, since the opening 101 having a width wider than that of the lower gate electrode 33 is formed at a position corresponding to the center of the channel region 35a of the first insulating layer 36a, the off-leakage current can be further reduced. In addition, the on-current can be increased, and the pressure resistance and reliability can be further improved.

FIG. 13 is a cross-sectional view showing an n-channel or p-channel LDD structure double gate TFT (Thin-Film Transistor) (thin film semiconductor device) according to Embodiment 6 of the present invention.
This double gate TFT differs from the double gate TFT of the first embodiment in that the upper gate insulating film 36 has a two-layer structure of first and second insulating layers 36a, 36b in the double gate TFT of the first embodiment. Whereas the opening 39 is formed at a position corresponding to the central portion of the channel region 35a of the first insulating layer 36a, the upper gate insulating film (second insulating film) is a single layer in the double gate TFT of the sixth embodiment. The upper gate insulating film 111 is structured such that the thickness of the central portion 111a corresponding to the central portion of the channel region 35a is smaller than the thickness of the peripheral portion 111b corresponding to the vicinity of the source / drain ends of the channel region 35a. The other components are the same as those of the double gate TFT of the first embodiment.

In this double gate TFT, the thickness of the upper gate insulating film 111 is set so that the thickness of the central portion 111a corresponding to the central portion of the channel region 35a is larger than the thickness of the peripheral portion 111b corresponding to the vicinity of the source / drain ends of the channel region 35a. Since the thickness is reduced, the off-leakage current is reduced, and the pressure resistance and reliability are further improved.
In addition, the channel structure is a double channel structure having channels on the upper and lower sides, the current density per unit area is increased, and the on-current is increased.

Next, a method for manufacturing the double gate TFT will be described with reference to FIGS.
In this manufacturing method, low concentration impurity ions 77 are implanted into the semiconductor thin film 35, and the low concentration source region 35b and the low concentration drain region 35c are formed on both sides of the channel region 35a. It is the same.
Thereafter, as shown in FIG. 14A, silicon oxide (SiO ₂ ) is formed on the lower gate insulating film 34 including the semiconductor thin film 35 under a condition that the substrate temperature is 100 to 600 ° C. by plasma CVD or the like. Then, an upper gate insulating film 111 having a thickness of 10 to 50 nm made of silicon nitride (Si ₃ N ₄ ) or the like is formed.

Next, as shown in FIG. 14B, a negative photoresist 112 is applied on the upper gate insulating film 111, and the back surface side of the substrate body 10A (opposite side to the lower gate electrode 33) using the lower gate electrode 33 as a mask. ) Is irradiated with light L, and the photoresist 112 is exposed.
Next, the photoresist 112 is developed. As a result, an opening 113 having the same size as the lower gate electrode 33 is formed in the photoresist 112 as shown in FIG.

Here, in order to form the opening 113 having the same size as that of the lower gate electrode 33 in the photoresist 112, the light intensity of the light L and the exposure time so that appropriate exposure is performed as in the second embodiment. Need to be controlled appropriately. As a result, the photoresist 112 is exposed except for the region corresponding to the lower gate electrode 33, and the uncured region of the photoresist 112 has the same size as the lower gate electrode 33.
By developing the photoresist 112, an opening 113 having the same size as the lower gate electrode 33 is formed in the photoresist 112.

Next, as shown in FIG. 15D, anisotropic etching such as dry etching is performed on the upper gate insulating film 111 using the photoresist 112 as a mask, and an opening 113 of the photoresist 112 is formed in the upper gate insulating film 111. And a concave portion 114 having the same shape in plan view.
Next, by removing the photoresist 112, as shown in FIG. 15E, the upper gate insulating film 111 in which the recess 114 is formed has a thickness of the central portion 111a corresponding to the central portion of the channel region 35a. However, the upper gate insulating film 111 is thinner than the thickness of the peripheral portion 111b corresponding to the vicinity of the low concentration source region 35b and the low concentration drain region 35c of the channel region 35a.

Since the process of forming the upper gate electrode 37 having a predetermined shape on the upper gate insulating film 111 is exactly the same as that of the second embodiment, the description thereof is omitted.
As described above, the thickness of the upper gate insulating film 111 having a single layer structure is set such that the thickness of the portion corresponding to the central portion of the channel region 35a is smaller than the thickness of the portion corresponding to the vicinity of the source / drain ends of the channel region 35a. An n-channel type LDD structure double-gate TFT can be manufactured.

  As described above, according to this double-gate TFT, the thickness of the upper gate insulating film 111 having a single layer structure is set such that the thickness of the central portion 111a corresponding to the central portion of the channel region 35a is equal to the source region of the channel region 35a. Since the thickness is smaller than the thickness of the peripheral portion 111b corresponding to the vicinity of the drain end, the same effect as that of the double gate TFT of the first embodiment can be obtained.

  Further, according to the method for manufacturing the double gate TFT, the thick upper gate insulating film 111 is formed on the lower gate insulating film 34 including the semiconductor thin film 35, and the opening 113 having the same size as the lower gate electrode 33 is formed. The upper gate insulating film 111 is subjected to anisotropic etching such as dry etching using the negative photoresist 112 formed with a mask as a mask, and the upper gate insulating film 111 has a recess having the same shape as the opening 113 of the photoresist 112 in plan view. Since 114 is formed, the upper gate insulating film 111 can be formed in one step, the process is simplified, and the manufacturing cost can be reduced.

[Electronics]
Next, specific examples of the electronic apparatus having the electro-optical device including the double gate TFT having the LDD structure according to the first to sixth embodiments of the present invention will be described.
FIG. 16 is a perspective view showing an example of a mobile phone. In FIG. 16, reference numeral 500 denotes a mobile phone body, and reference numeral 501 denotes a liquid crystal display unit of a liquid crystal device (electro-optical device) provided with the double gate TFT.
The electronic device shown in FIG. 16 has a liquid crystal device including the double gate TFT of the LDD structure of the above embodiment, and thus has excellent performance.

It is an equivalent circuit diagram which shows the equivalent circuit of the image display area | region of the liquid crystal device of Example 1 of this invention. It is an enlarged plan view which shows the principal part of the TFT array substrate of the liquid crystal device of Example 1 of this invention. It is sectional drawing which shows the cross-section of the liquid crystal device of Example 1 of this invention. It is sectional drawing which shows the double gate TFT of the LDD structure of Example 1 of this invention. It is sectional drawing which shows the double gate TFT of the LDD structure of Example 2 of this invention. It is process drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 2 of this invention. It is process drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 2 of this invention. It is process drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 3 of this invention. It is sectional drawing which shows the double gate TFT of the LDD structure of Example 4 of this invention. It is sectional drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 4 of this invention. It is sectional drawing which shows the double gate TFT of the LDD structure of Example 5 of this invention. It is sectional drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 5 of this invention. It is sectional drawing which shows the double gate TFT of the LDD structure of Example 6 of this invention. It is process drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 6 of this invention. It is process drawing which shows the manufacturing method of the double gate TFT of the LDD structure of Example 6 of this invention. It is a figure which shows an example of the mobile telephone which has the liquid crystal display part of the liquid crystal device provided with the double gate TFT of the LDD structure of Examples 1-6 of this invention.

Explanation of symbols

10A Translucent substrate body (translucent substrate)
33 Lower gate electrode (first gate electrode)
34 Lower gate insulating film (first insulating film)
35 Semiconductor thin film 35a Channel region 35b Low concentration source region 35c Low concentration drain region 35d High concentration source region 35e High concentration drain region 36 Upper gate insulating film (second insulating film)
36a First insulating layer 36b Second insulating layer 37 Upper gate electrode (second gate electrode)
38 Interlayer Insulating Film 39 Opening 71 Opening 76 Positive Photoresist 76a Hardened Region 77 Low Concentration Ion Ion 81 High Concentration Impurity Ion 91 Opening 111 Upper Gate Insulating Film (Second Insulating Film)
111a Central portion 111b Peripheral portion 112 Negative photoresist 113 Opening 114 Recess

Claims (9)

A first insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and a second insulating film are sequentially stacked;
A first gate electrode is disposed opposite to the channel region via the first insulating film, and a second gate electrode is disposed opposite to the channel region via the second insulating film. In the thin film semiconductor device in which a high concentration region having a relatively high impurity concentration and a low concentration region having a relatively low impurity concentration are formed in each region,
The thin film semiconductor, wherein the second insulating film has a thickness corresponding to a central portion of the channel region that is smaller than a thickness corresponding to the vicinity of each of the source region and the drain region of the channel region. apparatus. The second insulating film includes a first insulating layer formed on the semiconductor thin film, and a second insulating layer formed on the first insulating layer,
2. The thin film semiconductor device according to claim 1, wherein an opening having the same size as that of the first gate electrode is formed at a position corresponding to the channel region of the first insulating layer. The second insulating film includes a first insulating layer formed on the semiconductor thin film, and a second insulating layer formed on the first insulating layer,
2. The thin film semiconductor device according to claim 1, wherein an opening narrower than the first gate electrode is formed at a position corresponding to the channel region of the first insulating layer. The second insulating film includes a first insulating layer formed on the semiconductor thin film, and a second insulating layer formed on the first insulating layer,
2. The thin film semiconductor device according to claim 1, wherein an opening wider than the first gate electrode is formed at a position corresponding to the channel region of the first insulating layer. A first insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and a second insulating film composed of first and second insulating layers are sequentially stacked;
A first gate electrode is disposed opposite to the channel region via the first insulating film, and a second gate electrode is disposed opposite to the channel region via the second insulating film. Each of the regions is a method of manufacturing a thin film semiconductor device in which a high concentration region having a relatively high impurity concentration and a low concentration region having a relatively low impurity concentration are formed.
Forming a light-shielding first gate electrode on a light-transmitting substrate;
Sequentially stacking a first insulating film and a semiconductor thin film on the translucent substrate including the first gate electrode;
Applying a positive photoresist on the semiconductor thin film;
Exposing the photoresist from the back side of the translucent substrate using the first gate electrode as a mask, and patterning the photoresist into a predetermined shape;
Implanting low-concentration impurities into the semiconductor thin film using the patterned photoresist as a mask;
Forming a first insulating layer on the first insulating film including the patterned photoresist and semiconductor thin film; and
The patterned photoresist and the first insulating layer on the photoresist are removed by a lift-off method, and a portion corresponding to the central portion of the channel region of the semiconductor thin film of the first insulating layer is used as an opening. Process,
Forming a second insulating layer on the semiconductor thin film including the remaining first insulating layer;
Forming a second gate electrode wider than the first gate electrode on the second insulating layer;
Using the second gate electrode as a mask, implanting high-concentration impurities into the semiconductor thin film;
A method for manufacturing a thin film semiconductor device, comprising: A first insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and a second insulating film composed of first and second insulating layers are sequentially stacked;
A first gate electrode is disposed opposite to the channel region via the first insulating film, and a second gate electrode is disposed opposite to the channel region via the second insulating film. Each of the regions is a method of manufacturing a thin film semiconductor device in which a high concentration region having a relatively high impurity concentration and a low concentration region having a relatively low impurity concentration are formed.
Forming a light-shielding first gate electrode on a light-transmitting substrate;
Sequentially stacking a first insulating film and a semiconductor thin film on the translucent substrate including the first gate electrode;
Applying a positive photoresist on the semiconductor thin film;
Exposing the photoresist from the back side of the translucent substrate using the first gate electrode as a mask, and patterning the photoresist into a predetermined shape;
Forming a first insulating layer on the first insulating film including the patterned photoresist and semiconductor thin film; and
Implanting low-concentration impurities into the semiconductor thin film using the patterned photoresist and the first insulating layer as a mask;
The patterned photoresist and the first insulating layer on the photoresist are removed by a lift-off method, and a portion corresponding to the central portion of the channel region of the semiconductor thin film of the first insulating layer is used as an opening. Process,
Forming a second insulating layer on the semiconductor thin film including the remaining first insulating layer;
Forming a second gate electrode wider than the first gate electrode on the second insulating layer;
Using the second gate electrode as a mask, implanting high-concentration impurities into the semiconductor thin film;
A method for manufacturing a thin film semiconductor device, comprising: A first insulating film, a channel region, a semiconductor thin film having a source region and a drain region, and a second insulating film are sequentially stacked;
A first gate electrode is disposed opposite to the channel region via the first insulating film, and a second gate electrode is disposed opposite to the channel region via the second insulating film. Each of the regions is a method of manufacturing a thin film semiconductor device in which a high concentration region having a relatively high impurity concentration and a low concentration region having a relatively low impurity concentration are formed.
Forming a light-shielding first gate electrode on a light-transmitting substrate;
Sequentially stacking a first insulating film and a semiconductor thin film on the translucent substrate including the first gate electrode;
Applying a positive photoresist on the semiconductor thin film;
Exposing the positive photoresist from the back side of the translucent substrate using the first gate electrode as a mask, and patterning it into a predetermined shape;
Implanting low-concentration impurities into the semiconductor thin film using the patterned positive photoresist as a mask;
Forming a second insulating film on the first insulating film including the patterned photoresist and semiconductor thin film; and
Applying a negative photoresist on the second insulating film;
Exposing the negative photoresist from the back side of the translucent substrate using the first gate electrode as a mask, and patterning the negative photoresist;
The second insulating film is selectively removed using the patterned negative photoresist as a mask, and the thickness of the portion of the second insulating film corresponding to the central portion of the channel region of the semiconductor thin film is set to a portion other than this portion. Making it thinner than the thickness;
Removing the negative photoresist and forming a second gate electrode wider than the first gate electrode on the second insulating film;
Using the second gate electrode as a mask, implanting high-concentration impurities into the semiconductor thin film;
A method for manufacturing a thin film semiconductor device, comprising:   An electro-optical device comprising the thin film semiconductor device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 8.

Images