JP5243414B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device suitable for a display device such as a liquid crystal display device and a method for manufacturing the same.

A semiconductor device is an electronic device that includes an active element that utilizes electrical characteristics of a semiconductor, and is widely applied to, for example, audio equipment, communication equipment, computers, and home appliances. In particular, a semiconductor device including a thin film transistor (TFT) is widely applied to a pixel switching element, a driver circuit, and the like in an active matrix liquid crystal display device.

In recent years, display devices for mobile applications (displays) have been increasingly demanded for low power consumption, high functionality, high speed operation, high reliability, high definition, miniaturization, and the like. The development of displays is actively underway. For such problems, it is important to improve the performance of TFTs constituting various circuits of a display device and to make a technique for separately producing TFTs having optimum characteristics for various circuits. Therefore, a technique for forming TFTs having different characteristics on the same substrate has been developed.

Conventionally, a TFT driven with a low voltage (for example, 5 V or less) (hereinafter also referred to as “low voltage transistor”) and a TFT driven with a high voltage (for example, 10 V or more) (hereinafter referred to as “high voltage transistor”). In other words, a method of changing the thickness of the gate insulating film of both TFTs has been developed. More specifically, in the low voltage transistor, the gate insulating film has a single layer structure made of the first gate insulating film, while in the high voltage transistor, the gate insulating film is made up of the first gate insulating film and the second gate insulating film. A technique for forming a laminated structure has been developed. However, in this case, when the first gate insulating film is etched, the end portion of the semiconductor layer under the gate insulating film is exposed, the base insulating film under the semiconductor layer is etched (a counterbore enters the base insulating film), The coverage of the second gate insulating film formed thereafter deteriorates, and the breakdown voltage of the gate insulating film may decrease.

On the other hand, as a technique for preventing counterboring from entering the base insulating film under the semiconductor layer, a first semiconductor layer and a second semiconductor layer are formed on the base insulating film, and the first semiconductor layer Fabrication of a semiconductor device in which an insulating film is formed on the second semiconductor layer, and the insulating film located on the channel formation region of the first semiconductor layer is etched away using the first semiconductor layer as an etching stopper A method is disclosed (for example, refer to Patent Document 1).

Here, the configuration of the semiconductor device described in Patent Document 1 will be described in more detail. FIG. 11 is a schematic cross-sectional view showing a configuration of a conventional semiconductor device according to Patent Document 1, wherein (a) shows a low voltage transistor and (b) shows a high voltage transistor. As shown in FIG. 11, the conventional semiconductor device includes a TFT 110a and a TFT 110b on the same substrate 111. The TFT 110a functions as a low voltage transistor, and the TFT 110b functions as a high voltage transistor.

The TFT 110a has a structure in which an island-shaped semiconductor layer 120a, a first insulating film 112, a second insulating film 113, and a gate electrode 114a are formed in this order from the substrate 111 side, and an interlayer insulating film 115 covering these layers, A wiring 116 a and a wiring 117 a are formed over the insulating film 115. The semiconductor layer 120a has a channel region 121a and source / drain regions 123a.

On the other hand, the TFT 110b has a structure in which the island-shaped semiconductor layer 120b, the first insulating film 112, the second insulating film 113, and the gate electrode 114b are formed in this order from the substrate 111 side and covers the same as the TFT 110a. An interlayer insulating film 115 and wirings 116b and 117b formed over the interlayer insulating film 115 are included. The semiconductor layer 120b has a channel region 121b and source / drain regions 123b. As described above, in the TFT 110b, the gate insulating film includes the first insulating film 112 and the second insulating film 113.

In addition, in order to prevent the counterbore from entering a base insulating film (not shown) formed between the substrate 111 and the semiconductor layer 120a and the semiconductor layer 120b, the first insulating film 112 includes the semiconductor layer 120a and the semiconductor layer 120a. A layer 120b is formed so as to cover an end portion. Furthermore, the first insulating film 112 is removed by etching only in a region located on the channel region 121a of the TFT 110a. That is, in the TFT 110a, the gate insulating film is composed of the first insulating film 112 and the second insulating film 113 except on the channel region 121a.
JP 2005-183774 A

However, in Patent Document 1, the source / drain region 123a and the source / drain region are formed so that the source / drain region 123a and the source / drain region 123b of the low voltage transistor (TFT110a) and the high voltage transistor (TFT110b) can be doped simultaneously. The insulating film above the region 123b has two layers. In this case, the insulating film on the channel region 121a of the TFT 110a is a single layer, and the insulating film on the source / drain region 123a of the TFT 110a is two layers. Therefore, as shown in FIG. 12, when alignment misalignment occurs during the formation of the resist for etching the first insulating film 112, the gate insulating film on the channel region 121a has two layers in the end region of the gate electrode 114a. In some cases, the gate insulating film on the source / drain region 123a becomes a single layer outside the end of the gate electrode 114a. Such non-uniform two-layered gate insulating film on the channel region 121a causes variations in threshold voltage of the TFT 110a. Further, such non-uniform thickness of the gate insulating film on the source / drain region 123a causes an abnormality in the resistance value of the source / drain region 123a. In particular, as shown in FIG. 12, when the gate insulating film has two layers on the source / drain region 123a having a contact portion for forming a contact with the wiring 116a, the wiring 116a and the source / drain region 123a are formed. In order to reduce the contact resistance to the contact portion, it is necessary to optimize the impurity doping amount in the contact portion. For this reason, in the single layer region of the gate insulating film located outside the end portion of the gate electrode 114a, the doping amount becomes excessive, and the silicon crystal constituting the semiconductor layer 120a becomes amorphous. May occur.

In order to prevent the resistance value abnormality of the source / drain region 123a outside the end portion of the gate electrode 114a from occurring, a method of forming a two-layered gate insulating film located inside the end portion of the gate electrode 114a is also conceivable. . However, in this case, it is considered that the threshold voltage increases and the drain current decreases in the low voltage transistor. That is, it is generally necessary to reduce the channel length as the low-voltage transistor. However, if the channel length of the low-voltage transistor is 2 μm, for example, the length of the two-layer region of the gate insulating film located inside the end of the gate electrode 114a In consideration of misalignment, it is necessary to secure at least about 0.5 μm on one side. Therefore, the length of the channel region in which the gate insulating film is a single layer is 1 μm. As a result, in a low voltage transistor, it is considered that characteristics such as an increase in threshold voltage and a decrease in drain current are caused.

The present invention has been made in view of the above situation, and an object thereof is to provide a semiconductor device having high performance and high reliability, and a manufacturing method thereof, in which thin film transistors having different characteristics are formed on the same substrate. To do.

The inventors of the present invention have formed thin film transistors having different characteristics on the same substrate, and variously studied a semiconductor device having high performance and high reliability and a method for manufacturing the same. We focused on the method of changing the film thickness. The semiconductor device has a structure in which a semiconductor layer, an insulating film, and a wiring are stacked in this order from the substrate side on one main surface side of the substrate, and the semiconductor layer has a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first channel region and a first source / drain region including a first contact portion that contacts the wiring, and the second semiconductor layer contacts the second channel region and the wiring. A second source / drain region including a second contact portion, and the insulating film includes a first insulating film and a second insulating film stacked in this order from the substrate side. The second insulating film is formed on a region including the two-channel region and excluding the first channel region, the first contact portion, and the second contact portion. The second insulating film includes a first channel region and a second channel region of the first insulating film. And is formed on the area opposite to the first By facing the first source / drain region excluding the contact portion and the second source / drain region excluding the second contact portion, the occurrence of defects due to characteristic abnormalities, characteristic deterioration, etc. is suppressed. However, the inventors have found that transistors exhibiting different characteristics such as a low-voltage transistor and a high-voltage transistor can be formed on the same substrate, and have conceived that the above problems can be solved brilliantly and have reached the present invention. It is.

That is, the present invention is a semiconductor device having a structure in which a semiconductor layer, an insulating film, and a wiring are stacked in this order from the substrate side on one main surface side of the substrate, and the semiconductor layer includes the first semiconductor layer and A first semiconductor layer having a first channel region and a first source / drain region including a first contact portion in contact with the wiring; A two-channel region and a second source / drain region including a second contact portion in contact with the wiring, and the insulating film includes a first insulating film and a second insulating film stacked in this order from the substrate side. The first insulating film includes a second channel region and is formed on a region excluding the first channel region, the first contact portion, and the second contact portion, and the second insulating film includes the first channel region. And in the second channel region of the first insulating film And a first source / drain region excluding the first contact portion and a second source / drain region excluding the second contact portion. . Accordingly, thin film transistors having different characteristics can be formed over the same substrate, and a semiconductor device having high performance and high reliability can be realized.

The configuration of the semiconductor device of the present invention is not particularly limited as long as such a component is formed as an essential component, and may or may not include other components. . Note that the semiconductor device of the present invention may have a structure in which a semiconductor layer, an insulating film, a gate electrode, an interlayer insulating film, and a wiring are stacked in this order from the substrate side on one main surface side of the substrate.
A preferred embodiment of the semiconductor device of the present invention will be described in detail below. In addition, each form shown below may be combined suitably.

From the viewpoint of realizing a semiconductor device having high performance and high reliability by using a TFT having an LDD (Lightly Doped Drain) structure suitable for a low voltage transistor and a TFT having an LDD structure suitable for a high voltage transistor. The first semiconductor layer further has a first low-concentration impurity region having a lower impurity concentration than the first source / drain region, and the second semiconductor layer has an impurity concentration higher than that of the second source / drain region. The first insulating layer includes a second channel region and a second low concentration impurity region, and the first channel region, the first low concentration impurity region, and the first contact. The second insulating film is formed on a region excluding the first contact portion and the second contact portion, and the second insulating film includes a first channel region and a first low-concentration impurity region, A first source / drain region excluding the first contact portion and a second source / drain region excluding the second contact portion. It is preferable that the first low-concentration impurity regions are formed to face each other and have a sheet resistance smaller than that of the second low-concentration impurity regions.

The sheet resistance of the first low concentration impurity region is preferably about 20 to 50 kΩ / □, and the sheet resistance of the second low concentration impurity region is preferably about 40 to 150 kΩ / □. The first low-concentration impurity region preferably has a higher impurity concentration than the second low-concentration impurity region. Further, the first low-concentration impurity region preferably has a lower impurity concentration than the first source / drain region, and the second low-concentration impurity region has a lower impurity concentration than the second source / drain region. It is preferable.

From the viewpoint of improving the breakdown voltage of the first insulating film and the second insulating film, the semiconductor device includes a first gate electrode formed on the second insulating film facing the first channel region, and a second channel. And a second gate electrode formed on the second insulating film so as to face the region, wherein the first insulating film includes a second channel region, and the first channel region, the first contact portion, and the second Formed on the region excluding the contact portion, the region facing the first gate electrode at the end of the first semiconductor layer, and the region facing the second gate electrode at the end of the second semiconductor layer. preferable.

Note that, in the semiconductor device of the present invention, regions where the first insulating film and the second insulating film are not clearly defined may be formed or may not be formed.

That is, the first insulating film includes a second channel region and is formed at least on a region excluding the first channel region, the first contact portion, and the second contact portion, and the second insulating film A first source / drain region excluding the first contact portion and a second source / excluding the second contact portion, and at least formed on the region and the region facing the second channel region of the first insulating film. It may be formed at least facing the drain region.

The first insulating layer includes a second channel region and a second low concentration impurity region, and is on a region excluding the first channel region, the first low concentration impurity region, the first contact portion, and the second contact portion. At least formed, and the second insulating film is formed at least on the first channel region and the first low-concentration impurity region and the region facing the second channel region and the second low-concentration impurity region of the first insulating film. In addition, the first source / drain region excluding the first contact portion and the second source / drain region excluding the second contact portion may be formed opposite to each other.

Further, the first insulating film includes a second channel region and faces the first channel region, the region excluding the first contact portion and the second contact portion, and the first gate electrode at the end of the first semiconductor layer. And at least the region facing the second gate electrode at the end of the second semiconductor layer.

The present invention is also a method for manufacturing a semiconductor device having a structure in which a semiconductor layer, an insulating film, and a wiring are stacked in this order from the substrate side on one main surface side of the substrate, wherein the semiconductor layer includes the first semiconductor The first semiconductor layer has a first channel region and a first source / drain region including a first contact portion that contacts the wiring, and the second semiconductor layer includes: And a second channel region and a second source / drain region including a second contact portion in contact with the wiring, and the insulating film is a first insulating film and a second insulating film stacked in this order from the substrate side The manufacturing method includes forming a first insulating film on a region including the second channel region and excluding the first channel region, the first contact portion, and the second contact portion, and the first channel region And the second channel region of the first insulating film A method of manufacturing a semiconductor device including a step of forming a second insulating film on an opposing region and forming a second insulating film opposite to the first source / drain region and the second source / drain region. is there. Accordingly, thin film transistors having different characteristics can be formed over the same substrate, and a semiconductor device having high performance and high reliability can be manufactured.

The method for manufacturing a semiconductor device of the present invention is not particularly limited by other steps as long as it has the above steps. In the semiconductor device manufacturing method of the present invention, a semiconductor device having a structure in which a semiconductor layer, an insulating film, a gate electrode, an interlayer insulating film, and a wiring are stacked in this order from the substrate side on one main surface side of the substrate. It may be a manufacturing method.
A preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described in detail below. In addition, each form shown below may be combined suitably.

From the viewpoint of manufacturing a semiconductor device having high performance and high reliability using a TFT having an LDD structure suitable for a low voltage transistor and a TFT having an LDD structure suitable for a high voltage transistor, the first semiconductor The layer further includes a first low-concentration impurity region having a lower impurity concentration than the first source / drain region, and the second semiconductor layer has a second low-concentration impurity lower than the second source / drain region. The semiconductor device manufacturing method further includes a second channel region and a second low concentration impurity region, and includes a first channel region, a first low concentration impurity region, a first contact portion, and a second contact region. Forming a first insulating film on a region excluding the contact portion; a first channel region and a first low concentration impurity region; a second channel region and a second low concentration impurity region of the first insulating film; Forming a second insulating film on the region facing the first source / drain region and forming the second insulating film facing the first source / drain region and the second source / drain region; Forming a first gate electrode on a region facing the one channel region and forming a second gate electrode on a region facing the second channel region of the second insulating film; It is preferable to include a step of doping the first semiconductor layer and the second semiconductor layer with impurities using the gate electrode as a mask.

The sheet resistance of the first low concentration impurity region is preferably about 20 to 50 kΩ / □, and the sheet resistance of the second low concentration impurity region is preferably about 40 to 150 kΩ / □. The first low-concentration impurity region preferably has a higher impurity concentration than the second low-concentration impurity region. Further, the first low-concentration impurity region preferably has a lower impurity concentration than the first source / drain region, and the second low-concentration impurity region has a lower impurity concentration than the second source / drain region. It is preferable.

From the viewpoint of improving the breakdown voltage of the first insulating film and the second insulating film, the semiconductor device includes a first gate electrode formed on the second insulating film facing the first channel region, and a second channel. And a second gate electrode formed on the second insulating film so as to face the region. The method for manufacturing a semiconductor device includes a second channel region, and includes a first channel region, a first contact portion, and a first contact portion. The first insulating film on the region excluding the two contact portions, the region facing the first gate electrode at the end of the first semiconductor layer, and the region facing the second gate electrode at the end of the second semiconductor layer It is preferable to include the process of forming.

In the method for manufacturing a semiconductor device of the present invention, the regions where the first insulating film and the second insulating film are not clearly specified may be formed or may not be formed.

That is, the manufacturing method of the semiconductor device includes a step of forming a first insulating film on a region including at least the second channel region and excluding the first channel region, the first contact portion, and the second contact portion, and at least Forming a second insulating film on the first channel region and a region of the first insulating film facing the second channel region, and at least facing the first source / drain region and the second source / drain region And a step of forming a second insulating film.

The method for manufacturing a semiconductor device includes at least a second channel region and a second low concentration impurity region, and excludes the first channel region, the first low concentration impurity region, the first contact portion, and the second contact portion. Forming a first insulating film on the region; at least a first channel region and a first low-concentration impurity region; and a region facing the second channel region and the second low-concentration impurity region of the first insulating film. A step of forming a second insulating film on the first source / drain region and a second source / drain region opposite to the first source / drain region;

Further, the method for manufacturing the semiconductor device includes at least a second channel region and a region excluding the first channel region, the first contact portion, and the second contact portion, and a first gate at an end portion of the first semiconductor layer. You may include the process of forming a 1st insulating film on the area | region which opposes an electrode, and the area | region which opposes the 2nd gate electrode of the edge part of a 2nd semiconductor layer.

According to the semiconductor device of the present invention, thin film transistors having different characteristics can be formed on the same substrate, and a semiconductor device having high performance and high reliability can be realized.

Embodiments will be described below, and the present invention will be described in more detail with reference to the drawings. However, the present invention is not limited only to these embodiments.

(Embodiment 1)
1A and 1B are schematic views showing the configuration of the semiconductor device of Embodiment 1. FIG. 1A is a schematic cross-sectional view of a low-voltage transistor taken along line X1-Y1 in FIG. 1C, and FIG. It is a cross-sectional schematic diagram of the high voltage transistor in X2-Y2 line in d), (c) is a plane schematic diagram of a low voltage transistor, (d) is a plane schematic diagram of a high voltage transistor. In addition, the thick line in FIG.1 (c) and (d) shows the position of the edge part of a 1st insulating film.

As shown in FIG. 1, the semiconductor device of Embodiment 1 includes a TFT 10 a and a TFT 10 b on the same substrate 11. The TFT 10a and the TFT 10b are planar (top gate) TFTs and have a single drain structure.

The TFT 10a has a structure in which an island-shaped semiconductor layer 20a, a first insulating film 12, a second insulating film 13, and a gate electrode 14a are formed in this order from the substrate 11 side, and an interlayer insulating film 15 covering these layers, A wiring 16a and a wiring 17a are formed on the insulating film 15.

On the other hand, the TFT 10b has a structure in which the island-shaped semiconductor layer 20b, the first insulating film 12, the second insulating film 13, and the gate electrode 14b are formed in this order from the substrate 11 side and covers the same as the TFT 10a. Interlayer insulating film 15 and wirings 16b and 17b formed on interlayer insulating film 15 are included.

Thus, the 1st insulating film 12, the 2nd insulating film 13, and the interlayer insulating film 15 are used in common with TFT10a and TFT10b. That is, the first insulating film 12, the second insulating film 13, and the interlayer insulating film 15 constituting the TFT 10a, and the first insulating film 12, the second insulating film 13 and the interlayer insulating film 15 constituting the TFT 10b are respectively in the same process. It is formed by.

First, each configuration of the TFT 10a will be described. The semiconductor layer 20a has a channel region 21a located in a region facing the gate electrode 14a, and a source / drain region 23a located in a region other than the channel region 21a. That is, the source / drain region 23a is arranged adjacent to the channel region 21a in the channel length direction. The source / drain region 23a includes a contact portion 24a that contacts the wiring 16a.

Note that in this specification, a source / drain region is a region that functions as a source and / or a drain of a transistor. That is, when one source / drain region functions as a source, the other source / drain region functions as a drain.

The first insulating film 12 is formed in a region excluding the channel region 21a and the contact portion 24a in the TFT 10a. More specifically, the first insulating film 12 is an island-shaped semiconductor layer 20a including a channel region 21a and a contact portion 24a when the substrate 11 is viewed in plan view in the TFT 10a as shown in FIG. It is formed in a region excluding the inner region. The first insulating film 12 is formed so as to cover the end of the semiconductor layer 20a in the TFT 10a.

The second insulating film 13 is formed in the TFT 10a in a region including at least the channel region 21a and the source / drain region 23a excluding the contact portion 24a. More preferably, in the TFT 10a, the second insulating film 13 is formed on the semiconductor layer 20a and the first insulating film 12 except for the contact portion 24a.

The gate electrode 14a is formed to face the channel region 21a with the second insulating film 13 interposed therebetween. Therefore, in the TFT 10a, the second insulating film 13 functions as a gate insulating film.

The wiring 16 a is connected to the source / drain region 23 a through a contact hole formed in the interlayer insulating film 15. More specifically, the wiring 16a is connected to the source / drain region 23a by contacting the contact portion 24a of the source / drain region 23a. On the other hand, the wiring 17a is connected to the gate electrode 14a through a contact hole formed in the interlayer insulating film 15.

As described above, in the TFT 10 a, the gate insulating film is composed only of the second insulating film 13. Therefore, the TFT 10a can be driven at a high speed, and is suitable for a TFT (low voltage transistor) driven at a low voltage of 5 V or less (for example, 2 to 5 V), for example. Specifically, the TFT 10a can be suitably used for a logic circuit. When the semiconductor device of this embodiment is used for a display device such as a liquid crystal display device, the TFT 10a can be suitably used for a shift register circuit, a source driver, and the like.

Next, each configuration of the TFT 10b will be described. The semiconductor layer 20b has a channel region 21b located in a region facing the gate electrode 14b, and a source / drain region 23b located in a region other than the channel region 21b. That is, the source / drain region 23b is arranged adjacent to the channel region 21b in the channel length direction. The source / drain region 23b includes a contact portion 24b in contact with the wiring 16b.

As shown in FIG. 1D, the first insulating film 12 is formed in a region including the channel region 21a and excluding the contact portion 24b in the TFT 10b. The first insulating film 12 is formed so as to cover the end of the semiconductor layer 20a in the TFT 10b. Furthermore, the width in the channel length direction of the region located on the channel region 21b of the first insulating film 12 is set larger by about 0.5 to 4 μm (preferably 1 to 2 μm) than the channel length.

In the TFT 10b, the second insulating film 13 is formed in a region including at least the channel region 21b and the source / drain region 23a excluding the contact portion 24b. More preferably, in the TFT 10b, the second insulating film 13 is formed on the semiconductor layer 20b and the first insulating film 12 except for the contact portion 24b.

The gate electrode 14b is formed to face the channel region 21b with the first insulating film 12 and the second insulating film 13 interposed therebetween. Therefore, in the TFT 10b, the first insulating film 12 and the second insulating film 13 function as a gate insulating film.

The wiring 16 b is connected to the source / drain region 23 b through a contact hole formed in the interlayer insulating film 15. More specifically, the wiring 16b is connected to the source / drain region 23b by contacting the contact portion 24b of the source / drain region 23b. On the other hand, the wiring 17b is connected to the gate electrode 14b through a contact hole formed in the interlayer insulating film 15.

As described above, in the TFT 10b, since the gate insulating film is composed of the laminated film of the first insulating film 12 and the second insulating film 13, for example, a TFT (high voltage transistor) driven at a high voltage of 10 V or more. Is preferred. Specifically, the TFT 10b is suitable as a transistor that functions as an analog switch.

As described above, in the semiconductor device of this embodiment having the TFT 10a and the TFT 10b, the first insulating film 12 includes the channel region 21b and is formed on the region excluding the channel region 21a, the contact portion 24a, and the contact portion 24b. Is done. The second insulating film 13 is formed on the channel region 21a and the region facing the channel region 21b of the first insulating film 12, and the source / drain region 23a excluding the contact portion 24a and the contact portion. It is formed opposite to the source / drain regions 23b except 24b. Therefore, the gate insulating film in the TFT 10a can have a single layer structure, and the gate insulating film in the TFT 10b can have a stacked structure (two-layer structure). Therefore, the semiconductor device of this embodiment can have the TFT 10a that exhibits excellent characteristics as a low-voltage transistor and the TFT 10b that exhibits excellent characteristics as a high-voltage transistor on the same substrate 11.

Further, the width in the channel length direction of the first insulating film 12 in the region located on the channel region 21b can be appropriately set within a range not overlapping the contact portion 24b. That is, a margin for misalignment during patterning of the first insulating film 12 can be given to the first insulating film 12. Therefore, the semiconductor device of this embodiment suppresses the gate insulating film from becoming non-uniformly (partially) a single layer in the TFT 10b even if misalignment occurs during patterning of the first insulating film 12. Can do. As a result, it is possible to prevent the threshold value from varying in the TFT 10b. On the other hand, in the TFT 10a, the channel region 21a and the source / drain region 23a excluding the contact portion 24a are only covered with the single-layer second insulating film 13, so the TFT 10a patterns the first insulating film 12. It is not affected by misalignment. Thus, the semiconductor device of this embodiment can have the TFT 10a and the TFT 10b excellent in reliability on the same substrate 11.

A single-layer second insulating film 13 is provided above the source / drain regions 23a excluding the contact portions 24a and the source / drain regions 23b excluding the contact portions 24b. It should be noted that the second insulating film 13 is also provided on the contact portion 24a and the contact portion 24b when doping impurities into the source / drain region 23a and the source / drain region 23b. Therefore, when doping the source / drain region 23a and the source / drain region 23b, the single-layer second insulating film 13 is disposed above the source / drain region 23a and the source / drain region 23b including the contact portion 24a and the contact portion 24b. Is provided. For this reason, the source / drain region 23a and the source / drain region 23b can be collectively doped with impurities, and the source / drain region 23a and the source / drain region 23b are highly doped (N ⁺ or P ^+). ) Can be easily optimized. As a result, the contact resistance of the contact part 24a and the contact part 24b can be reduced. That is, the TFT 10a and the TFT 10b can each include an optimum impurity concentration region 25a and an optimum impurity concentration region 25b, which are regions doped with impurities at an optimum concentration.

Further, in the TFT 10b, the source / drain region 23b outside the end of the gate electrode 14b (channel region 21b) and in which the first insulating film 12 and the second insulating film 13 are stacked is an optimum impurity concentration region. Compared with 25b, the doping amount is reduced. That is, this region becomes a low dose region 26b in which the impurity doping amount is smaller than that in the optimum impurity concentration region 25b. Therefore, it is possible to effectively suppress the occurrence of a resistance value abnormality due to excessive doping in the TFT 10b.

Note that the low dose region 26b has a smaller impurity doping amount than the optimum impurity concentration region 25a and the optimum impurity concentration region 25b, and thus has a sheet resistance value larger than that of the optimum impurity concentration region 25a and the optimum impurity concentration region 25b. More specifically, the resistance value of the low dose region 26b is about 1 to 2 kΩ / □, while the resistance values of the optimum impurity concentration region 25a and the optimum impurity concentration region 25b are about 0.5 to 1 kΩ / □. Become. That is, the low dose region 26b has a resistance value about twice that of the optimum impurity concentration region 25a and the optimum impurity concentration region 25b. However, the resistance value of the low dose region 26b is large enough not to affect the on-state current of the transistor characteristics, and the characteristics of the TFT 10b are not deteriorated.

Conventionally, dielectric breakdown is likely to occur between the gate electrode and the semiconductor layer near the end of the island-shaped semiconductor layer. This is because the coverage of the gate insulating film is deteriorated at the end portion of the semiconductor layer, and the film thickness is reduced. However, in the present embodiment, the first insulating film 12 is formed so as to cover the end portion of the semiconductor layer 20a and the end portion of the semiconductor layer 20b. Therefore, the end of the region facing the gate electrode 14 a of the semiconductor layer 20 a is covered with the two insulating layers of the first insulating film 12 and the second insulating film 13. Similarly, the end of the region facing the gate electrode 14 b of the semiconductor layer 20 b is covered with two insulating layers, the first insulating film 12 and the second insulating film 13. Therefore, the breakdown voltage of the gate insulating film can be improved in the TFTs 10a and 10b.

In the case of an N-channel TFT with channel doping, the threshold voltage of the parasitic transistor at the end of the semiconductor layer is low because the end of the semiconductor layer is thinner than the center of the channel. Furthermore, since the gate insulating film is thin at the end of the semiconductor layer, the threshold voltage of the parasitic transistor is low. As a result, there is a problem that the leakage current increases when the gate voltage is 0 volts. This problem becomes more prominent in the case of a low voltage transistor that requires a low threshold voltage. On the other hand, in the present invention, since the gate insulating film thickness at the end of the semiconductor layer is thick, such a problem can be improved.

Further, since the gate insulating film is thin at the edge of the semiconductor layer, it is easily affected by plasma damage and static electricity during the TFT formation process, and it is easy to trap fixed charges. As a result, the threshold value of the parasitic transistor at the end of the semiconductor layer fluctuates, increasing the leakage current and increasing the variation in the threshold voltage of the TFT. In contrast, in the present invention, since the gate insulating film thickness at the end of the semiconductor layer is thick, such a problem can be improved.

2A and 2B are schematic views showing the configuration of the semiconductor device of Embodiment 1, FIG. 2A is a schematic plan view showing a modification of the low-voltage transistor, and FIG. 2B is a modification of the high-voltage transistor. It is a plane schematic diagram to show. 2A and 2B indicate the position of the end portion of the first insulating film. From the viewpoint of improving the breakdown voltage of the gate insulating film, the first insulating film 12 opposes the region facing the gate electrode 14a at the end of the semiconductor layer 20a and the gate electrode 14b at the end of the semiconductor layer 20b. What is necessary is just to form at least on an area | region. Therefore, when the source / drain region 23a and the source / drain region 23b do not have a sufficient area, the gate electrode 14a intersects the first insulating film 12 as shown in FIGS. It may be formed so as to cover the end of the semiconductor layer 20a and the end of the semiconductor layer 20b where the gate electrode 14b intersects. This also provides a sufficient breakdown voltage of the gate insulating film. When the source / drain region 23a and the source / drain region 23b are sufficiently large, particles caused by etching residues of the gate electrode and photoresist residues that are likely to occur in the counterbore portions formed at the end portions of the semiconductor layer are generated. From the viewpoint of preventing this, it is preferable that all of the ends of the first insulating film 12 are disposed on the semiconductor layer 20a and the semiconductor layer 20b as shown in FIGS.

Next, a modification of this embodiment will be described.
FIG. 3 is a schematic cross-sectional view showing a configuration of a modified example of the semiconductor device of Embodiment 1, wherein (a) shows a high-voltage transistor having a GOLD structure, and (b) is a high-voltage transistor having an LDD structure. (C) shows a low voltage transistor having an LDD structure.

As shown in FIG. 3, the semiconductor device of this embodiment includes a TFT 10c having a GOLD (Gate Overlapped LDD) structure, a TFT 10d having an LDD structure, and a TFT 10e having an LDD structure on the same substrate 11. Also good.

The TFT 10c includes a channel region 21c located in a region facing the gate electrode 14c, a low concentration impurity region 22c disposed on both outer sides of the channel region 21c in the channel length direction, and other than the channel region 21c and the low concentration impurity region 22c. A semiconductor layer 20c having a source / drain region 23c located in the first region. That is, the low concentration impurity region 22c is arranged adjacent to the channel region 21c in the channel length direction, and the source / drain region 23c is arranged adjacent to the low concentration impurity region 22c in the channel length direction. The source / drain region 23c includes a contact portion 24c that contacts the wiring 16c. The low concentration impurity region 22c functions as an LDD region.

In the TFT 10c, the first insulating film 12 is formed in a region including the channel region 21c and the low concentration impurity region 22c and excluding the contact portion 24c. The first insulating film 12 is formed so as to cover the end of the semiconductor layer 20c in the TFT 10c. Furthermore, the width in the channel length direction of the region located on the channel region 21c and the low concentration impurity region 22c of the first insulating film 12 is 0.5 than the length in the channel length direction of the channel region 21c and the low concentration impurity region 22c. It is set larger by about 4 μm (preferably 1-2 μm).

In the TFT 10c, the second insulating film 13 is formed in a region including at least the channel region 21c, the low-concentration impurity region 22c, and the source / drain region 23c excluding the contact portion 24c. More preferably, the second insulating film 13 is formed on the semiconductor layer 20c and the first insulating film 12 in the TFT 10c except for the contact portion 24c.

The gate electrode 14c is formed to face the channel region 21c and the low concentration impurity region 22c with the first insulating film 12 and the second insulating film 13 interposed therebetween. Therefore, in the TFT 10b, the first insulating film 12 and the second insulating film 13 function as a gate insulating film.

Similar to the TFT 10a and the like, the TFT 10c includes an interlayer insulating film 15, a wiring 16c connected to the contact portion 24c, and a wiring 17c connected to the gate electrode 14c.

As described above, in the TFT 10c, the gate insulating film is composed of the laminated film of the first insulating film 12 and the second insulating film 13. The TFT 10c has a GOLD structure. Therefore, the TFT 10c is inferior in driving speed as compared with the TFT 10b, but has extremely excellent reliability and extremely excellent resistance to hot carrier deterioration, and suppresses the short channel effect very effectively. Can do. The TFT 10c is suitable for a high voltage transistor. Specifically, the TFT 10c can be suitably used for a circuit having a high power supply voltage, for example, a power supply voltage of 8 to 16 V (high voltage). Further, when the semiconductor device of this embodiment is used for a display device such as a liquid crystal display device, the TFT 10c can be suitably used for a gate driver or the like.

The TFT 10d includes a channel region 21d located in a region facing the gate electrode 14d, a low concentration impurity region 22d disposed on both outer sides of the channel region 21d in the channel length direction, and other than the channel region 21d and the low concentration impurity region 22d. A semiconductor layer 20d having a source / drain region 23d located in the region is provided. That is, the low concentration impurity region 22d is disposed adjacent to the channel region 21d in the channel length direction, and the source / drain region 23d is disposed adjacent to the low concentration impurity region 22d in the channel length direction. The source / drain region 23d includes a contact portion 24d that contacts the wiring 16d. The low concentration impurity region 22d functions as an LDD region.

In the TFT 10d, the first insulating film 12 is formed in a region including the channel region 21d and the low-concentration impurity region 22d and excluding the contact portion 24d. The first insulating film 12 is formed so as to cover the end portion of the semiconductor layer 20d in the TFT 10d. Furthermore, the width in the channel length direction of the region located on the channel region 21d and the low concentration impurity region 22d of the first insulating film 12 is 0.5 to 4 μm (preferably 1 mm) than the length in the channel length direction of the channel region 21d. About 2 μm). The first insulating film 12 is set larger by about 0.5 to 2 μm (preferably 1 to 1.5 μm) than the width of the channel region 21d in the channel length direction.

In the TFT 10d, the second insulating film 13 is formed in a region including at least the channel region 21d, the low-concentration impurity region 22d, and the source / drain region 23d excluding the contact portion 24d. More preferably, in the TFT 10d, the second insulating film 13 is formed on the semiconductor layer 20d and the first insulating film 12 except for the contact portion 24d.

The gate electrode 14d is formed to face the channel region 21d with the first insulating film 12 and the second insulating film 13 interposed therebetween. Therefore, in the TFT 10d, the first insulating film 12 and the second insulating film 13 function as a gate insulating film.

Similar to the TFT 10a and the like, the TFT 10d includes an interlayer insulating film 15, a wiring 16d connected to the contact portion 24d, and a wiring 17d connected to the gate electrode 14d.

As described above, in the TFT 10 d, the gate insulating film is composed of a laminated film of the first insulating film 12 and the second insulating film 13. The TFT 10d has an LDD structure. Therefore, although the TFT 10d is inferior in driving speed as compared with the TFT 10b, it has excellent reliability and excellent resistance to hot carrier deterioration, and can effectively suppress the short channel effect. The TFT 10d is suitable for a high voltage transistor. Specifically, when the semiconductor device of this embodiment is used in a display device such as a liquid crystal display device, the TFT 10c is suitable as a pixel switching transistor or the like.

The TFT 10e includes a channel region 21e located in a region facing the gate electrode 14e, a low concentration impurity region 22e disposed on both outer sides of the channel region 21e in the channel length direction, and other than the channel region 21e and the low concentration impurity region 22e. A semiconductor layer 20e having a source / drain region 23e located in the region is included. That is, the low concentration impurity region 22e is disposed adjacent to the channel region 21e in the channel length direction, and the source / drain region 23e is disposed adjacent to the low concentration impurity region 22e in the channel length direction. The source / drain region 23e includes a contact portion 24e that contacts the wiring 16e. The low concentration impurity region 22e functions as an LDD region.

In the TFT 10e, the first insulating film 12 is formed in a region excluding the channel region 21e, the low concentration impurity region 22e, and the contact portion 24e. More specifically, the first insulating film 12 includes an inner region of the island-shaped semiconductor layer 20e including the channel region 21e, the low-concentration impurity region 22e, and the contact portion 24e when the substrate 11 is viewed in plan view in the TFT 10e. It is formed in the excluded area. The first insulating film 12 is formed so as to cover the end of the semiconductor layer 20e in the TFT 10e.

In the TFT 10e, the second insulating film 13 is formed in a region including at least the channel region 21e, the low-concentration impurity region 22e, and the source / drain region 23e excluding the contact portion 24e. More preferably, in the TFT 10e, the second insulating film 13 is formed on the semiconductor layer 20e and the first insulating film 12 except for the contact portion 24e.

The gate electrode 14e is formed to face the channel region 21e with the second insulating film 13 interposed therebetween. Therefore, in the TFT 10e, the second insulating film 13 functions as a gate insulating film.

Similar to the TFT 10a and the like, the TFT 10e includes an interlayer insulating film 15, a wiring 16e connected to the contact portion 24e, and a wiring 17e connected to the gate electrode 14e.

As described above, in the TFT 10e, the gate insulating film is composed only of the second insulating film 13. The TFT 10d has an LDD structure. Therefore, the TFT 10d is superior in driving speed to the TFT 10b or the like, although it is inferior in driving speed to the TFT 10a. In addition, the TFT 10e has excellent reliability and excellent resistance to hot carrier deterioration, and can effectively suppress the short channel effect. Furthermore, the TFT 10e is suitable for a low voltage transistor. Specifically, the TFT 10e can be suitably used for a circuit that is driven with a voltage slightly higher than that of the TFT 10a. For example, the TFT 10a is suitable for use in a circuit having a power supply voltage of 5V or less, and the TFT 10e is suitable for use in a circuit having a power supply voltage of 4-8V (more preferably, 6-8V). .

As described above, in the semiconductor device of this embodiment having the TFT 10c, the TFT 10d, and the TFT 10e, the first insulating film 12 includes the channel region 21c, the low concentration impurity region 22c, the channel region 21d, and the low concentration impurity region 22d. In addition, the channel region 21e, the contact portion 24c, the contact portion 24d, and the contact portion 24e are formed on the region. The second insulating film 13 includes a channel region 21e and a low concentration impurity region 22e, a region facing the channel region 21c and the low concentration impurity region 22c of the first insulating film 12, and a channel region 21d of the first insulating film 12. And the source / drain region 23c excluding the contact portion 24c, the source / drain region 23d excluding the contact portion 24d, and the source / drain region excluding the contact portion 24e. It is formed opposite to the drain region 23e. Therefore, the semiconductor device of this embodiment can have the TFTs 10c and 10d that exhibit excellent characteristics as high-voltage transistors and the TFT 10e that exhibits excellent characteristics as low-voltage transistors on the same substrate 11.

The width in the channel length direction of the first insulating film 12 in the region located on the channel region 21c and the low-concentration impurity region 22c can be appropriately set within a range that does not overlap the contact portion 24c. Therefore, similarly to the TFT 10b, it is possible to suppress variation in threshold value in the TFT 10c.

The width in the channel length direction of the first insulating film 12 in the region located on the channel region 21d and the low-concentration impurity region 22d can be appropriately set within a range that does not overlap the contact portion 24d. Therefore, similarly to the TFT 10b, it is possible to suppress the variation in threshold value in the TFT 10d.

On the other hand, in the TFT 10e, the channel region 21e, the low-concentration impurity region 22e, and the source / drain region 23e excluding the contact portion 24e are only covered with the single-layer second insulating film 13, so the TFT 10e There is no influence of misalignment when the first insulating film 12 is patterned. Thus, the semiconductor device of this embodiment can have the TFT 10c, TFT 10d, and TFT 10e excellent in reliability on the same substrate 11.

A single-layer second insulating film 13 is formed above the source / drain region 23c excluding the contact portion 24c, the source / drain region 23d excluding the contact portion 24d, and the source / drain region 23e excluding the contact portion 24e. Is provided. Therefore, similarly to the TFT 10a and TFT 10b, the impurity doping amount for the source / drain region 23c, the source / drain region 23d and the source / drain region 23e is optimized, and the contact resistances of the contact part c, contact part 24d and contact part 24e are reduced. The resistance can be reduced.

Further, similarly to the TFT 10b, in the TFT 10c and the TFT 10d, it is possible to effectively suppress the occurrence of an abnormal resistance value due to excessive doping.

The first insulating film 12 is formed so as to cover end portions of the semiconductor layer 20c, the semiconductor layer 20d, and the semiconductor layer 20e. Therefore, the breakdown voltage of the gate insulating film can be improved in the TFT 10c, TFT 10d, and TFT 10e, similarly to the TFT 10a and TFT 10b.

Here, the TFT 10d and the TFT 10e having the LDD structure will be further described.
4A and 4B are schematic cross-sectional views showing a configuration of a modified example of the semiconductor device of Embodiment 1 during the manufacturing process. FIG. 4A shows a low-voltage transistor having an LDD structure, and FIG. 4B shows an LDD structure. 1 shows a high voltage transistor having.

As shown in FIG. 4, the low-concentration impurity regions 22d and the low-concentration impurity regions 22e functioning as LDD regions are formed by doping the low-concentration impurities after forming the gate electrode 14d and the gate electrode 14e. At this time, in the TFT 10e, the semiconductor layer 20e is doped through the second insulating film 13, while in the TFT 10d, the region to be the low concentration impurity region 22d of the semiconductor layer 20d is the first insulating film 12 and the second insulating film. Doped over 13 Therefore, the low concentration impurity region 22e of the TFT 10e is doped with a relatively high concentration, while the low concentration impurity region 22d of the TFT 10d is doped with a relatively low concentration. As a result, the sheet resistance of the low concentration impurity region 22e of the TFT 10e suitable as a low voltage transistor is set to 20 to 50 kΩ / □, and the sheet resistance of the low concentration impurity region 22d of the TFT 10d suitable as a high voltage transistor is set to 40 to 150 kΩ / □. It is possible to set.

The sheet resistance is measured by a resistance evaluation pattern (TEG) of 2 terminals or 4 terminals.

In general, since a low voltage transistor is driven at a low voltage, a high current driving force is required instead of high reliability. In this case, the resistance of the LDD region is preferably set to a low resistance. In order to perform high current driving, a single drain structure is preferable. However, the single drain structure has low reliability against hot carrier deterioration. For example, a transistor having a single drain structure with a channel length of 4 μm has a voltage of 6 V or more. Reliability cannot be guaranteed. In addition, since the single drain structure tends to cause a short channel effect, it is difficult to set a low threshold value. In contrast, the LDD structure is more resistant to hot carrier degradation than the single drain structure, and can suppress the short channel effect. As described above, in the TFT 10e, the current driving force can be relatively increased, and the reliability with respect to the case where the medium voltage, for example, the power supply voltage is 4 to 8 V (more preferably, 6 to 8 V) is secured. be able to.

On the other hand, a high voltage transistor is driven at a high voltage, and thus high reliability is required. Degradation due to an electric field (electric field due to a gate voltage) generated in a direction perpendicular to the substrate surface can be suppressed by increasing the thickness of the gate insulating film. That is, reliability can be improved by forming the gate insulating film in a stacked structure. Further, deterioration due to an electric field (electric field due to a drain voltage) generated in a direction parallel to the substrate surface (lateral direction) can be suppressed by increasing the resistance of the LDD region. That is, this makes it possible to improve resistance to hot carrier deterioration.

On the other hand, in a pixel switching transistor used as a switching element of a display device such as a liquid crystal display device, it is necessary to suppress leakage current. For such a pixel switching transistor, the occurrence of leakage current can be suppressed by using the TFT 10d having a large resistance in the LDD region.

In this manner, by using various transistors having a single drain structure, a GOLD structure, or an LDD structure at appropriate positions, a high-performance and highly reliable circuit can be formed.

FIG. 5 is a graph showing the relationship between the resistance of the LDD region, the on-current (current driving capability), and the hot carrier deterioration rate (on-current deterioration rate) in a TFT having an LDD structure. Thus, in the LDD structure, the hot carrier deterioration rate decreases as the resistance of the LDD region increases.

In the case of the GOLD structure, there is a resistance in the LDD region that minimizes the hot carrier deterioration rate, and the GOLD structure is very resistant to deterioration. Compared to the LDD structure, the GOLD structure has a feature that the current driving force is high, but has a demerit that the load capacity is large and the power consumption is large.

On the other hand, the LDD structure is less resistant to hot carrier degradation and has a lower current driving capability than the GOLD structure. However, the LDD structure has a smaller load capacity than the GOLD structure and is advantageous for a circuit that reduces power consumption. In addition, since the LDD structure can suppress generation of a leakage current, it is suitable for a circuit that needs to hold an output voltage. In a TFT having a conventional LDD structure, it is necessary to increase the resistance of the LDD region in order to improve resistance to hot carrier degradation. However, in a TFT having a conventional LDD structure, if the resistance in the LDD region is increased, the current drivability decreases. Therefore, both of them (hot carrier deterioration and current drivability) have been improved with a single type of transistor conventionally. Was very difficult.

In a low voltage transistor driven with a low voltage of about several volts, resistance to hot carrier deterioration is not so important, but rather a current driving capability for high-speed driving of the circuit is required. On the other hand, in a high voltage transistor driven with a high voltage of 10 V or more, high-frequency high-speed driving is not performed from the viewpoint of suppressing power consumption, so current driving capability is not important, and resistance to hot carrier degradation is important. Become. Therefore, if an LDD structure transistor having a low resistance LDD region is formed for a low voltage, and an LDD structure transistor having a high resistance LDD region is formed for a high voltage, an optimum circuit can be configured. Is possible.

On the other hand, according to the TFT 10d and the TFT 10e of the present embodiment, as described above, impurities are doped at a relatively high concentration by a single doping without passing through a photolithography process, that is, a relatively low resistance. A low-voltage transistor having an LDD region and a high-voltage transistor doped with impurities at a relatively low concentration, that is, having a relatively high resistance LDD region can be formed at the same time.

In this embodiment, as will be described later, a mask LDD structure by a photolithography method will be mainly described. However, as the LDD structure, an LDD structure in which sidewalls are formed, a high-concentration impurity region in a source / drain region, and the like. A self-aligned LDD structure formed by a method of thinning the gate electrode after doping may be used.

Below, the manufacturing method of the semiconductor device of this embodiment is demonstrated.
FIGS. 6A to 6D and FIGS. 7E to 7H are schematic cross-sectional views illustrating the configuration of the semiconductor device according to the first embodiment during the manufacturing process.

Here, as shown in FIG. 7H, a semiconductor device having a TFT 10f on the same substrate 11 in addition to the above-described TFT 10a, TFT 10b, TFT 10c, TFT 10d, and TFT 10e will be described. The case where the TFTs 10a, 10b, 10c, 10d, 10e, and 10f are N-channel TFTs will be mainly described.

First, the configuration of the TFT 10f will be described. FIG. 8 is a schematic cross-sectional view showing a configuration of a modified example of the semiconductor device of Embodiment 1, and shows a low-voltage transistor having a GOLD structure. As shown in FIG. 8, the TFT 10f includes a channel region 21f located in a region facing the gate electrode 14f, a low-concentration impurity region 22f disposed on both outer sides of the channel region 21f in the channel length direction, and a channel region 21f. And a semiconductor layer 20f having a source / drain region 23f located in a region other than the low concentration impurity region 22f. That is, the low concentration impurity region 22f is disposed adjacent to the channel region 21f in the channel length direction, and the source / drain region 23f is disposed adjacent to the low concentration impurity region 22f in the channel length direction. The source / drain region 23f includes a contact portion 24f in contact with the wiring 16f. The low concentration impurity region 22f functions as an LDD region.

In the TFT 10f, the first insulating film 12 is formed in a region excluding the channel region 21f, the low-concentration impurity region 22f, and the contact portion 24f. More specifically, the first insulating film 12 includes an inner region of the island-shaped semiconductor layer 20f including the channel region 21f, the low-concentration impurity region 22f, and the contact portion 24f when the substrate 11 is viewed in plan view in the TFT 10f. It is formed in the excluded area. The first insulating film 12 is formed so as to cover the end of the semiconductor layer 20f in the TFT 10f.

In the TFT 10f, the second insulating film 13 is formed in a region including at least the channel region 21f, the low-concentration impurity region 22f, and the source / drain region 23f excluding the contact portion 24f. More preferably, in the TFT 10f, the second insulating film 13 is formed on the semiconductor layer 20f and the first insulating film 12 except for the contact portion 24f.

The gate electrode 14f is formed to face the channel region 21f and the low concentration impurity region 22f with the second insulating film 13 interposed therebetween. Therefore, in the TFT 10f, the second insulating film 13 functions as a gate insulating film.

Similar to the TFT 10a and the like, the TFT 10f includes an interlayer insulating film 15, a wiring 16f connected to the contact portion 24f, and a wiring 17f connected to the gate electrode 14f.

As described above, in the TFT 10 f, the gate insulating film is composed only of the second insulating film 13. The TFT 10f has a GOLD structure. Accordingly, the TFT 10f is inferior in driving speed as compared with the TFT 10a, but has extremely excellent reliability and extremely excellent resistance to hot carrier deterioration, and suppresses the short channel effect very effectively. Can do. The TFT 10f is suitable for a low voltage transistor. Specifically, the TFT 10f requires a current driving force like a switching circuit or the like, but is negative when a voltage opposite to the ON state is applied to the voltage between the gate and the source, that is, in an N-channel TFT. When a positive bias is applied to the bias and P-channel TFTs, the single drain structure has a problem with reliability, and thus the TFT 10f having excellent current driving capability and reliability can be suitably used.

Next, a method for manufacturing the semiconductor device of this embodiment having the TFT 10a, TFT 10b, TFT 10c, TFT 10d, TFT 10e, and TFT 10f on the same substrate 11 will be described.

First, as shown in FIG. 6A, on one main surface of the substrate 11, an island-shaped semiconductor layer (active layer) 20a having a film thickness of 30 to 100 nm (preferably 40 to 50 nm), a semiconductor layer (active layer) Layer) 20b, semiconductor layer (active layer) 20c, semiconductor layer (active layer) 20d, semiconductor layer (active layer) 20e, and semiconductor layer (active layer) 20f. More specifically, each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is amorphous having an amorphous structure by sputtering, LPCVD (Low Pressure CVD), or plasma CVD (Chemical Vapor Deposition). After the semiconductor film is formed, the crystalline semiconductor film obtained by performing crystallization with a laser is patterned into a desired shape by a photolithography process. The material of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is not particularly limited, but is preferably silicon, silicon germanium (SiGe) alloy, or the like.

The crystallization process of each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is a solid phase in which a catalytic metal such as nickel (Ni) is applied to an amorphous semiconductor film and then heat treatment is performed using a laser or the like. A growth process may be performed. Thereby, a continuous grain boundary crystal silicon film (CG silicon film) can be formed.

Crystallization by laser may be a method of irradiating a laser only once in an air atmosphere containing about 20% of oxygen, or irradiating a laser again in a nitrogen atmosphere after laser irradiation in the air atmosphere. It may be a method to do. According to the latter method, the surfaces of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f can be further planarized.

The material of the substrate 11 is not particularly limited, and a glass substrate, a quartz substrate, a silicon substrate, a metal plate, a substrate having an insulating film formed on the surface of a stainless plate, a plastic substrate having heat resistance that can withstand the processing temperature, or the like. Among them, a glass substrate is preferable. The substrate 11 is preferably a substrate used for a display device such as a liquid crystal display device. Thus, the semiconductor device of this embodiment is suitable as a semiconductor device provided in a display device, and is particularly suitable as a semiconductor device provided on a substrate for a display device.

A base layer may be formed between the substrate 11 and each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f. As the base layer, an insulating film containing silicon (eg, SiO ₂ , SiN, SiNO) or the like can be used. In addition to the single layer structure of the insulating film, the base layer may have a structure in which two or more insulating films are stacked. As a result, even when a glass substrate is used as the substrate 11, diffusion of impurities such as alkali metal elements from the substrate 11 can be prevented, and variations in electrical characteristics of the TFTs 10a, 10b, 10c, 10d, 10e, and 10f can be prevented. Can be reduced.

Next, a first insulating film 12 having a thickness of 10 to 70 nm (preferably 30 to 50 nm) is formed. As the first insulating film 12, an insulating film containing silicon (for example, a SiO ₂ film, a SiN film, or a SiNO film) formed by a plasma CVD method or a sputtering method can be used. Among these, the first insulating film 12 is preferably a SiO ₂ film. The first insulating film 12 may have a structure in which two or more insulating films made of a plurality of insulating materials are stacked in addition to a single layer structure. In this case, the layer in contact with each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is preferably an SiO ₂ film. Thus the semiconductor layers 20a, 20b, 20c, 20d, 20e, by laminating a 20f and the SiO ₂ film in this order, the semiconductor layers 20a, 20b, 20c, 20d, 20e, 20f to the case of the silicon layer Since the interface state at the interface between the first insulating film 12 and each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f can be reduced, the electrical properties of the TFTs 10a, 10b, 10c, 10d, 10e, and 10f are reduced. Characteristics can be improved.

Next, an impurity element such as boron (B) is formed on the entire surface of each semiconductor layer 20a, 20b, 20c, 20d, 20e, 20f for the purpose of controlling the threshold voltage of each TFT 10a, 10b, 10c, 10d, 10e, 10f. Is doped by ion implantation (channel doping). More specifically, after doping is performed on conditions of 50 kV and 5 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² for both N-channel and P-channel TFTs, a semiconductor of a TFT that becomes a P-channel TFT In a state where the layer is masked with a resist, doping is performed on the N-channel TFT semiconductor layer under conditions of 50 kV and 5 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² . At this time, the concentration of the impurity element in each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is about 2 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^{−3 for} an N-channel TFT, A TFT that is a P-channel type is about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

When any of the TFTs 10a, 10b, 10c, 10d, 10e, and 10f is a P-channel TFT, the above-described channel doping may be performed only on the semiconductor layer of the N-channel TFT. Alternatively, it may be performed on the semiconductor layers of both N-channel and P-channel TFTs. Further, in order to obtain a desired threshold voltage in each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f, the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f are each appropriately doped. The impurity elements in the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f may have different concentrations. Further, the channel doping described above may be performed after the second insulating film 13 is formed. As a result, the threshold values of the TFTs 10a, 10e, and 10f suitable as low voltage transistors and the threshold values of the TFTs 10b, 10c, and 10d suitable as high voltage transistors can be made different. On the other hand, TFTs 10a, 10e, and 10f suitable as low voltage transistors and TFTs 10b, 10c, and 10d suitable as high voltage transistors have the same channel region impurity concentration and channel doping is performed under optimum doping conditions. As described above, the channel doping is preferably performed after the formation of the first insulating film 12 and before the patterning of the first insulating film 12.

Next, as shown in FIG. 6B, the regions serving as the channel regions of the TFTs 10c and 10f and the semiconductor layers (semiconductor layers 20a, 20b, 20d, and 20e) of the TFTs other than the TFTs 10c and 10f are masked with a resist 31a. In this state, an impurity element such as phosphorus (P) is added to the regions to be the low concentration impurity regions 22c and the source / drain regions 23c of the TFT 10c and the regions to be the low concentration impurity regions 22f and the source / drain regions 23f of the TFT 10f. Doping (low concentration doping for GOLD structure) is performed under the conditions of 50 kV and 2 × 10 ^{13 to} 5 × 10 ¹³ cm ⁻² by ion implantation. At this time, the concentration of the impurity element in the region to be the low concentration impurity region 22c and the source / drain region 23c of the semiconductor layer 20c and the region to be the low concentration impurity region 22f and the source / drain region 23f of the semiconductor layer 20f is About 5 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . Thereby, the low concentration impurity region 22c and the low concentration impurity region 22f functioning as the LDD region are formed in the TFTs 10c and 10f having the GOLD structure. Thereafter, the resist 31a is removed. As described above, the low-concentration impurity region 22c and the low-concentration impurity region 22f can be set to optimum concentrations by separately performing the low-concentration doping for the GOLD structure and the low-concentration doping for the LDD structure described later.

Note that the low concentration doping for the GOLD structure may be performed after the second insulating film is formed. As a result, the resistance value of the LDD region (low concentration impurity region 22c) of the TFT 10c having the GOLD structure can be made different from the resistance value of the LDD region (low concentration impurity region 22f) of the TFT 10f having the GOLD structure.

Next, as shown in FIG. 6C, the first insulating film 12 is patterned by performing etching after patterning the resist 31b. As a result, in the TFTs 10a, 10e, and 10f, the first insulating film 12 in the region overlapping the end portions of the semiconductor layers 20a, 20e, and 20f is left, and the channel regions 21a, 21e, and 21f, and the source / drain regions 23a, 23e, and 23f are left. Then, the first insulating film 12 in the regions to be the low concentration impurity regions 22e and 22f is removed. In the TFTs 10b, 10c, and 10d, the first insulating film 12 in the region overlapping with the end portions of the semiconductor layers 20b, 20c, and 20d, and the first regions in the regions that become the channel regions 21b, 21c, and 21d and the low-concentration impurity regions 22c and 22d. The one insulating film 12 is left, and the first insulating film 12 in the regions to be the contact portions 24b, 24c, 24d of the source / drain regions 23b, 23c, 23d is removed. In consideration of the case where misalignment of the photomask and / or misalignment of the pattern occurs during the patterning of the resist 31b by the photolithography process, the end portions of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f are taken into consideration. The end portion of the overlapping first insulating film 12 is positioned on the inner side of 0 to 2 μm (preferably 0.5 to 1 μm) from the end portion of each semiconductor layer 20a, 20b, 20c, 20d, 20e, and 20f. The end portion of the first insulating film 12 on the region to be the channel region 21b is positioned outside by 0 to 2 μm (preferably 0.5 to 1 μm) from the end portion of the gate electrode 14b (that is, the channel region 21b). The first insulating film 12 is patterned. In the case of a single drain structure or a GOLD structure, the first insulating film 12 may be formed so as to be positioned outside the end of the gate electrode by 0 to 2 μm (preferably 0.5 to 1 μm). In this case, the gate electrode may be formed so as to be located outside by 0.5 to 2 μm (preferably 1 to 1.5 μm) from the end of the gate electrode. Thereafter, the resist 31b is removed.

Note that the first insulating film 12 in the region overlapping the end portions of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is formed in the semiconductor layers 20a, 20b, and 20c in the channel width direction as shown in FIG. , 20d, 20e, and 20f may be overlapped only on the ends.

Next, as shown in FIG. 6D, a second insulating film 13 having a thickness of 10 to 70 nm (preferably 30 to 50 nm) is formed on the entire surface of the substrate 11. As the second insulating film 13, an insulating film containing silicon (for example, a SiO ₂ film, a SiN film, or a SiNO film) formed by a plasma CVD method or a sputtering method can be used. Among these, as the second insulating film 13, a SiO ₂ film is suitable. The second insulating film 13 may have a structure in which two or more insulating films made of a plurality of insulating materials are stacked in addition to a single layer structure. In this case, the layer in contact with each of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f is preferably an SiO ₂ film. In this manner, the respective semiconductor layers 20a, 20b, 20c, 20d, 20e, 20f and the SiO ₂ film are laminated in order, so that the TFTs 10a, 10b, 10c, 10d, 10e are formed as in the case of the first insulating film 12. The electrical characteristics of 10f can be improved.

Next, after forming a conductive film having a film thickness of 200 to 600 nm (preferably 300 to 400 nm) by sputtering, the conductive film is patterned into a desired shape by a photolithography process, as shown in FIG. Gate electrodes 14a, 14b, 14c, 14d, 14e, and 14f are formed. At this time, the gate electrode 14a is formed to face the region to be the channel region 21a, the gate electrode 14b is formed to face the region to be the channel region 21b, and the gate electrode 14c is formed from the channel region 21c and the low concentration. The gate electrode 14d is formed to face the region to be the channel region 21d, the gate electrode 14e is formed to face the region to be the channel region 21e, and is formed to face the region to be the impurity region 22c. The electrode 14f is formed so as to face a region that becomes the channel region 21f and the low-concentration impurity region 22f. The material of each gate electrode 14a, 14b, 14c, 14d, 14e, 14f is a refractory metal such as tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), or these refractory metals. An alloy material or a compound material containing as a main component is suitable. In addition, a nitride is suitable as the compound mainly composed of a refractory metal. Each gate electrode 14a, 14b, 14c, 14d, 14e, 14f may have a structure in which conductive films formed using these materials are stacked.

Subsequently, an impurity such as phosphorus (P) is ion-implanted into each semiconductor layer 20a, 20b, 20c, 20d, 20e, 20f in a self-aligning manner using each gate electrode 14a, 14b, 14c, 14d, 14e, 14f as a mask. Then, doping (low concentration doping for LDD structure) is performed under conditions of 70 kV and 1 × 10 ^{13 to} 3 × 10 ¹³ cm ⁻² . At this time, the region to be the source / drain region 23a of the semiconductor layer 20a, the region to be the source / drain region 23b of the semiconductor layer 20b, the region to be the source / drain region 23c of the semiconductor layer 20c, and the semiconductor layer 20d A region to be the low concentration impurity region 22d and the source / drain region 23d, a region to be the low concentration impurity region 22e and the source / drain region 23e of the semiconductor layer 20e, and a region to be the source / drain region 23f of the semiconductor layer 20f. The concentration of the impurity element in is about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . Thereby, the low concentration impurity region 22d and the low concentration impurity region 22e functioning as an LDD region are formed in the TFTs 10d and 10e having the LDD structure.

Next, as shown in FIG. 7F, the semiconductor layers 20a, 20b, 20c, 20d, 20e, in the state where the semiconductor layers 20d, 20e in the regions to be the LDD regions of the TFTs 10d, 10e are masked with a resist 31c. 20f is doped with impurities such as phosphorus (P) under the conditions of 40 kV and 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² by ion implantation (high concentration doping for source and drain). At this time, the region to be the source / drain region 23a of the semiconductor layer 20a, the region to be the source / drain region 23b of the semiconductor layer 20b, the region to be the source / drain region 23c of the semiconductor layer 20c, and the semiconductor layer 20d The concentration of the impurity element in the region to be the source / drain region 23d, the region to be the source / drain region 23e of the semiconductor layer 20e, and the region to be the source / drain region 23f of the semiconductor layer 20f is 1 × 10 ¹⁹ to. It is set to about 1 × 10 ²⁰ cm ⁻³ . Thereby, low-concentration impurity regions 22c, 22d, 22e, and 22f that function as LDD regions are formed. In addition, high concentration impurity regions 23a, 23b, 23c, 23d, 23e, and 23f that function as source / drain regions are formed. At this time, in the TFTs 10b, 10c, and 10d, the regions doped with impurities through the first insulating film 12 and the second insulating film 13 are low-dose regions with a small impurity doping amount as described above. Since the resistance value of the low dose region is smaller than the resistance values of the low concentration impurity region 22c and the low concentration impurity region 22d functioning as the LDD region, the low dose region has a current driving force of the TFTs 10b, 10c, and 10d. Has no effect.

Note that when any of the TFTs 10a, 10b, 10c, 10d, 10e, and 10f is a P-channel TFT, the N-channel TFT is masked in a state where the semiconductor layer of the P-channel TFT is masked. A region that becomes a source / drain region of a TFT that becomes a P-channel type in a state in which a region that becomes a source / drain region of the semiconductor layer is heavily doped and a semiconductor layer of the TFT that becomes an N-channel type is masked And a step of performing high concentration doping.

Here, the source / drain regions 23a, 23b, 23c, 23d, 23e, and 23f are doped only with unipolar impurities, but CG is used as the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f. In the case of forming a silicon film, in order to getter a catalytic metal such as Ni, end portions of the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f or the semiconductor layers 20a, 20b, 20c, 20d, 20e, A region having no influence on TFT characteristics other than the contact portions 24a, 24b, 24c, 24d, 24e, and 24f of 20f may be doped with an impurity having a reverse polarity.

Next, an interlayer insulating film 15 having a film thickness of 0.5 to 1.5 μm (preferably 0.7 to 1.0 μm) is formed on the entire surface of the substrate 11. As the interlayer insulating film 15, an insulating film containing silicon (for example, a SiO ₂ film, a SiN film, or a SiNO film) formed by a plasma CVD method or a sputtering method can be used. The interlayer insulating film 15 may have a structure in which two or more insulating films are stacked in addition to a single-layer structure of the insulating film. In particular, the interlayer insulating film 15 includes a silicon nitride (SiN: H) film containing hydrogen having a thickness of 0.2 to 0.4 μm and a SiO ₂ film having a thickness of 0.4 to 0.6 μm from the substrate 11 side. A laminated film in which films are laminated is preferable. Thereafter, the semiconductor substrate 20a, 20b, 20c, 20d, 20e, and 20f are hydrogenated and activated by heating the entire substrate 11 at 400 to 450 ° C. for about 0.5 to 1 hour. At this time, hydrogen contained in the silicon nitride film diffuses into the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f, and dangling bonds in the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f. Terminate. As described above, by using a silicon nitride film containing hydrogen, the semiconductor layers 20a, 20b, 20c, 20d, 20e, and 20f can be effectively hydrogenated. Then, by the photolithography process, as shown in FIG. 7G, each source / drain region 23a, 23b, 23c, 23d, 23e, 23f and each gate electrode 14a, 14b, 14c, 14d, 14e, 14f are formed. Correspondingly, contact holes are formed in the interlayer insulating film 15 and the second insulating film 13.

In addition, the hydrogenation and activation process of each semiconductor layer 20a, 20b, 20c, 20d, 20e, and 20f may be performed after the contact hole is formed.

Finally, after a conductive film having a film thickness of 400 to 1000 nm (preferably 600 to 800 nm) is formed by sputtering, the conductive film is patterned into a desired shape by a photolithography process, as shown in FIG. The wirings 16a, 17a, 16b, 17b, 16c, 17c, 16d, 17d, 16e, 17e, 16f, and 17f are formed. Thereby, the semiconductor device of this embodiment can be completed. The wirings 16a, 17a, 16b, 17b, 16c, 17c, 16d, 17d, 16e, 17e, 16f, and 17f are made of a low resistance material such as aluminum (Al), copper (Cu), or silver (Ag). A metal or an alloy material or a compound material mainly composed of these low resistance metals is preferable. Further, each of the wirings 16a, 17a, 16b, 17b, 16c, 17c, 16d, 17d, 16e, 17e, 16f, and 17f may have a structure in which conductive films formed using these materials are stacked. .

In addition, after the formation of each wiring 16a, 17a, 16b, 17b, 16c, 17c, 16d, 17d, 16e, 17e, 16f, and 17f, a multilayer wiring structure is formed as needed, a resin film and / or silicon A protective film may be formed by a nitride film.

As described above, according to the method for manufacturing a semiconductor device of this embodiment, a semiconductor device having the TFTs 10a, 10b, 10c, 10d, 10e, and 10f having excellent performance and reliability on the same substrate 11 is manufactured. be able to.

Hereinafter, another method for manufacturing the semiconductor device of this embodiment will be described.
FIGS. 9A to 9E and FIGS. 10F to 10J are schematic cross-sectional views illustrating configurations of modified examples of the semiconductor device of the first embodiment during the manufacturing process.

Here, as shown in FIG. 10J, a TFT 10d / n and a TFT 10d / p having the same configuration as the above-described TFT 10d will be described. However, the TFT 10d / n is an N-channel type, and the TFT 10d / p is a P-channel type.

First, as shown in FIG. 9A, in the same manner as described above, an island-shaped semiconductor layer (active layer) having a film thickness of 30 to 100 nm (preferably 40 to 50 nm) is formed on one main surface of the substrate 11. ) 20 d / n and a semiconductor layer (active layer) 20 d / p are formed.

Next, the first insulating film 12 having a thickness of 10 to 70 nm (preferably 30 to 50 nm) is formed in the same manner as described above.

Next, for the purpose of controlling the threshold voltages of the TFTs 10d / n and 10d / p, an impurity element such as boron (B) is doped by ion implantation on the entire surface of the semiconductor layers 20d / n and 20d / p (channels). Doping). More specifically, the semiconductor layers 20d / n and 20d / p are doped under conditions of 50 kV and 5 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² , and then the semiconductor layers 20d / p are masked. The doping is performed on the semiconductor layer 20 d / n under the conditions of 50 kV and 5 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² . At this time, the concentration of the impurity element in the semiconductor layer 20d / n is about 2 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^−3, and the concentration of the impurity element in the semiconductor layer 20d / p is 1 × 10 ^16. It is set to about ˜1 × 10 ¹⁷ cm ⁻³ .

Note that the above-described channel doping may be performed only on the semiconductor layer 20d / n, or may be performed on the semiconductor layer 20d / n and the semiconductor layer 20d / p. Further, in order to obtain a desired threshold voltage in each of the semiconductor layers 20d / n and 20d / p, the semiconductor layers 20d / n and 20d are appropriately doped for each of the semiconductor layers 20d / n and 20d / p. The concentration of the impurity element at / p may be different. Further, in the case where a low voltage transistor is formed on the substrate 11 in addition to the TFTs 10 d / n and 10 d / p, the above-described channel doping may be performed after the second insulating film 13 is formed. As a result, the threshold values of the TFTs 10d / n and 10d / p, which are suitable as high voltage transistors, can be made different from the threshold values of the low voltage transistors. On the other hand, in the low voltage transistor and the TFTs 10d / n and 10d / p suitable as the high voltage transistor, the channel region has the same impurity concentration in the channel region and the channel doping is performed as described above from the viewpoint of performing the channel doping under the optimum doping conditions. As described above, the first insulating film 12 is preferably formed and before the first insulating film 12 is patterned.

Next, as shown in FIG. 9B, in order to form the LDD region of the TFT having the GOLD structure, the TFT having the GOLD structure in a state where the semiconductor layers 20d / n and 20d / p are masked by the resist 31d. The semiconductor layer is doped with an impurity element such as phosphorus (P) under the conditions of 50 kV and 2 × 10 ^{13 to} 5 × 10 ¹³ cm ⁻² by ion implantation (low concentration doping for GOLD structure). At this time, the concentration of the impurity element in the low concentration impurity region and the source / drain region in the semiconductor layer of the TFT having the GOLD structure is about 5 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . Thereafter, the resist 31a is removed.

Note that the low concentration doping for the GOLD structure may be performed after the second insulating film is formed. As a result, the resistance value of the LDD region of the high voltage transistor having the GOLD structure can be made different from the resistance value of the LDD region of the low voltage transistor having the GOLD structure. In the case where a TFT having a GOLD structure is not formed on the substrate 11, this step may be omitted.

Next, as shown in FIG. 9C, similarly to the case of the TFT 10d described above, after the resist 31e is patterned, the first insulating film 12 is patterned by etching. Thereafter, the resist 31e is removed.

Next, as shown in FIG. 9D, the second insulating film 13 having a film thickness of 10 to 70 nm (preferably 30 to 50 nm) is formed in the same manner as described above.

Next, similarly to the above-described method, a conductive film having a film thickness of 200 to 600 nm (preferably 300 to 400 nm) is formed by a sputtering method, and then the conductive film is patterned into a desired shape by a photolithography process, whereby FIG. As shown in (e), gate electrodes 14d / n and 14d / p are formed. At this time, the gate electrode 14d / p is formed to face the region to be the channel region 21d / p, and the gate electrode 14d / n is formed to face the region to be the channel region 21d / n.

Subsequently, using the gate electrodes 14d / n and 14d / p as a mask, impurities such as phosphorus (P) are self-aligned to the semiconductor layers 20d / n and 14d / p by an ion implantation method to 70 kV, 1 × 10 ¹³ to Doping is performed under the condition of 3 × 10 ¹³ cm ⁻² (first low concentration doping for LDD structure). At this time, the concentration of the impurity element in the low concentration impurity region 22d / n and the source / drain region 23d / n of the semiconductor layer 20d / n is about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^−3. To do. Thereby, a low concentration impurity region 22d / n functioning as an LDD region is formed in the TFT 10d / n. At this time, the regions to be the low-concentration impurity regions 22d / p and the source / drain regions 23d / p of the semiconductor layer 20d / p are similarly doped.

Next, as shown in FIG. 10F, in a state where the semiconductor layer 20d / n is masked with the resist 31f, an impurity such as boron (B) is doped into the semiconductor layer 20d / p by an ion implantation method (second second). Low concentration doping for LDD structure). In the second low concentration doping for the LDD structure, it is necessary to cancel the impurities (phosphorus) doped in the first low concentration doping for the LDD structure. Therefore, in the second low concentration doping for the LDD structure, the impurity (boron) is doped at a concentration about twice that of the first low concentration doping for the LDD structure. More specifically, the second low concentration doping for the LDD structure is performed under conditions of 50 kV and 2 × 10 ^{13 to} 6 × 10 ¹³ cm ⁻² . At this time, the concentration of the impurity element in the regions to be the low-concentration impurity regions 22d / p and the source / drain regions 23d / p of the semiconductor layer 20d / p is about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^−3. To do. Thereby, a low concentration impurity region 22d / p that functions as an LDD region is formed in the TFT 10d / p. Thereafter, the resist 31f is removed.

Here, the LDD region of the TFT 10d / n is formed first, but the LDD region of the TFT 10d / p may be formed first.

Next, as shown in FIG. 10 (g), the TFT 10d / p and the semiconductor layer 20d / n in the region to be the LDD region of the TFT 10d / n are masked with a resist 31g, and the semiconductor layer 20d / n is phosphorusated. Impurities such as (P) are doped by ion implantation under the conditions of 40 kV and 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² (first high concentration doping for source / drain). At this time, the concentration of the impurity element in the region to be the source / drain region 23d / n of the semiconductor layer 20d / n is about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . As a result, a low concentration impurity region 22d / n functioning as an LDD region is formed. Also, high concentration impurity regions 23d / n functioning as source / drain regions are formed. Thereafter, the resist 31g is removed.

Next, as shown in FIG. 10 (h), in the state where the TFT 10d / n and the semiconductor layer 20d / p in the region to be the LDD region of the TFT 10d / p are masked with a resist 31h, boron is applied to the semiconductor layer 20d / p. Impurities such as (B) are doped by ion implantation under the conditions of 40 kV and 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² (second high concentration doping for source / drain). At this time, the concentration of the impurity element in the region to be the source / drain region 23d / p of the semiconductor layer 20d / p is set to about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . Thereby, the low concentration impurity region 22d / p functioning as the LDD region is formed. Also, a high concentration impurity region 23d / p that functions as a source / drain region is formed. Thereafter, the resist 31h is removed.

Here, the source / drain region 23d / n of the TFT 10d / n is formed first, but the source / drain region 23d / p of the TFT 10d / p may be formed first.

Here, the source / drain regions 23d / p and 23d / n are doped only with unipolar impurities, but when a CG silicon film is formed as the semiconductor layers 20d / p and 20d / n. In order to getter catalytic metals such as Ni, TFT characteristics other than the end portions of the semiconductor layers 20d / p and 20d / n or the contact portions 24d / p and 24d / n of the semiconductor layers 20d / p and 20d / n A region having no influence may be doped with an impurity having a reverse polarity.

Next, in the same manner as described above, an interlayer insulating film 15 having a film thickness of 0.5 to 1.5 μm (preferably 0.7 to 1.0 μm) is formed. Thereafter, in the same manner as described above, the semiconductor layers 20d / p and 20d / n are hydrogenated and activated. Then, by the photolithography process, as shown in FIG. 10I, the interlayer insulating film 15 and the source / drain regions 23d / p, 23d / n and the gate electrodes 14d / p, 14d / n Contact holes are formed in the second insulating film 13.

Note that the hydrogenation and activation processes of the semiconductor layers 20d / p and 20d / n may be performed after the contact holes are formed.

Finally, similarly to the above-described method, a conductive film having a film thickness of 400 to 1000 nm (preferably 600 to 800 nm) is formed by a sputtering method, and then the conductive film is patterned into a desired shape by a photolithography process, whereby FIG. As shown in (j), wirings 16d / p, 17d / p, 16d / n, and 17d / n are formed. Thereby, the semiconductor device of this embodiment having TFTs 10d / p and 10d / n can be completed.

In addition, after forming each wiring 16d / p, 17d / p, 16d / n, and 17d / n, if necessary, a multilayer wiring structure is formed, or a protective film is formed using a resin film and / or a silicon nitride film. Or you may.

As described above, according to this manufacturing method, it is possible to manufacture a semiconductor device having the TFTs 10d / p and 10d / n having excellent performance and reliability and different conductivity types on the same substrate 11.

This application claims priority based on the Paris Convention or the laws and regulations in the country of transition based on Japanese Patent Application No. 2007-134465 filed on May 21, 2007. The contents of the application are hereby incorporated by reference in their entirety.

It is a schematic diagram which shows the structure of the semiconductor device of Embodiment 1, (a) is a cross-sectional schematic diagram of the low voltage transistor which has the single drain structure in the X1-Y1 line | wire in (c), (b) is (D) is a schematic cross-sectional view of a high-voltage transistor having a single drain structure along line X2-Y2 in (d), (c) is a schematic plan view of a low-voltage transistor having a single drain structure, and (d) is It is a plane schematic diagram of a high voltage transistor having a single drain structure. 2A is a schematic diagram illustrating a configuration of a semiconductor device of Embodiment 1, FIG. 3A is a schematic plan view illustrating a modified example of a low-voltage transistor having a single drain structure, and FIG. It is a plane schematic diagram which shows the modification of a voltage transistor. 4A and 4B are schematic cross-sectional views illustrating a configuration of a modified example of the semiconductor device of Embodiment 1, wherein FIG. 5A illustrates a high-voltage transistor having a GOLD structure, FIG. 5B illustrates a high-voltage transistor having an LDD structure, c) shows a low voltage transistor having an LDD structure. FIG. 7 is a schematic cross-sectional view showing a configuration of a modification of the semiconductor device of Embodiment 1 during a manufacturing process, where (a) shows a low-voltage transistor having an LDD structure, and (b) is a high-voltage transistor having an LDD structure. Indicates. It is a graph which shows the relationship between resistance of the LDD area | region in TFT which has an LDD structure, an on-current (current drive capability), and a hot carrier deterioration rate (on-current deterioration rate). (A)-(d) is a cross-sectional schematic diagram which shows the structure of the semiconductor device of Embodiment 1 in a manufacturing process. (E)-(h) is a cross-sectional schematic diagram which shows the structure of the semiconductor device of Embodiment 1 in a manufacturing process. FIG. 6 is a schematic cross-sectional view showing a configuration of a modification of the semiconductor device of Embodiment 1, and shows a low voltage transistor having a GOLD structure. (A)-(e) is a cross-sectional schematic diagram which shows the structure of the modification of the semiconductor device of Embodiment 1 in a manufacturing process. (F)-(j) is a cross-sectional schematic diagram which shows the structure of the modification of the semiconductor device of Embodiment 1 in a manufacturing process. It is a cross-sectional schematic diagram which shows the structure of the conventional semiconductor device which concerns on patent document 1, (a) shows a low voltage transistor, (b) shows a high voltage transistor. It is a cross-sectional schematic diagram which shows the structure of the low voltage transistor in the conventional semiconductor device which concerns on patent document 1, and shows the case where the arrangement place of a 1st insulating film has shifted | deviated.

Explanation of symbols

10a to 10f, 10d / p, 10d / n, 110a, 110b: thin film transistor (TFT)
11, 111: substrate 12, 112: first insulating film 13, 113: second insulating films 14a to 14f, 14d / p, 14d / n, 114a, 114b: gate electrode 15, 115: interlayer insulating films 16a to 16f, 17a-17, 16d / p, 16d / n, 17d / p, 17d / n, 116a, 116b, 117a, 117b: wirings 20a-20f, 20d / p, 20d / n, 120a, 120b: semiconductor layers 21a-21f , 21d / p, 21d / n, 121a, 121b: channel regions 22c-22f, 22d / p, 22d / n: low-concentration impurity regions 23a-23f, 23d / p, 23d / n, 123a, 123b: source / drain Region (High concentration impurity region)
24a to 24f: contact portions 25a and 25b: optimum impurity concentration region 26b: low dose regions 31a to 31h: resist

Claims (6)

A method of manufacturing a semiconductor device having a structure in which a semiconductor layer, an insulating film, and a wiring are stacked in this order from the substrate side on one main surface side of the substrate,
The semiconductor layer has a first semiconductor layer and a second semiconductor layer,
The first semiconductor layer includes a first channel region, a first source / drain region including a first contact portion in contact with the wiring, and a first low-concentration impurity region having a lower impurity concentration than the first source / drain region. And
The second semiconductor layer includes a second channel region, a second source / drain region including a second contact portion in contact with the wiring, and a second low-concentration impurity region having a lower impurity concentration than the second source / drain region. And
The insulating film has a first insulating film and a second insulating film laminated in this order from the substrate side,
The semiconductor device includes a first gate electrode formed on the second insulating film facing at least the first channel region, and a second gate formed on the second insulating film facing at least the second channel region. An electrode,
The manufacturing method includes forming a first insulating film so as to cover the first and second semiconductor layers;
Patterning the first insulating film;
After patterning the first insulating film, forming a second insulating film so as to cover the first and second semiconductor layers;
Forming the first and second gate electrodes after forming the second insulating film;
Doping the impurities after forming the first insulating film to form first and second low-concentration impurity regions;
Doping the impurities after forming the gate electrode to form first and second high-concentration impurity regions that function as first and second source / drain regions, respectively;
Forming a contact hole in the second insulating film after forming the first and second high-concentration impurity regions,
The first insulating film includes a second channel region , a second low-concentration impurity region, a region facing the first gate electrode at the end of the first semiconductor layer, and a second gate at the end of the second semiconductor layer. A first channel region , a first low-concentration impurity region, a first contact portion, a region between the first channel region and the first contact portion, and a second contact portion . Is patterned on the area excluding
A portion of the end portion of the first insulating film adjacent to the second low-concentration impurity region is located outside the end portion of the second low-concentration impurity region . The first and second low-concentration impurity regions are formed by doping impurities in a self-aligned manner using the first and second gate electrodes as a mask after forming the first and second gate electrodes,
The first low-concentration impurity region is doped through the second insulating film;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second low-concentration impurity region is doped through the first and second insulating films. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the first low-concentration impurity region is doped with an impurity at a higher concentration than the second low-concentration impurity region. The semiconductor device manufacturing method further includes forming a resist,
2. The semiconductor device according to claim 1, wherein the first and second low-concentration impurity regions are formed by doping impurities in a state where the first and second channel regions are masked with a resist. Production method. The resist is formed on the first insulating film before patterning the first insulating film,
5. The method of manufacturing a semiconductor device according to claim 4, wherein the first and second low-concentration impurity regions are doped through the first insulating film. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the doping for forming the first and second low-concentration impurity regions is performed after the formation of the second insulating film.

Images