JPH0688972A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To optimize the LDD structure of thin-film transistors(TFTs) of the active matrix type liquid crystal display device integrally formed with a display picture element part and a peripheral circuit part on the same substrate. CONSTITUTION:The display picture element part 3 which includes plural pieces of picture elements TFTs 4 and the peripheral circuit part 2 which is disposed on the periphery of this display picture element part 3 and is constituted of plural pieces of the peripheral TFTs 5 are formed on the main surface of the insulating substrate 1. Both of the picture elements TFTs 4 and peripheral TFTs 5 are constituted of polycrystalline silicon thin films 6 having LDD regions of the same conduction type in at least either of between the source regions S and drain regions D and the channel regions. The length side of the LDD regions of the peripheral TFTs 5 or the impurity concn. of the LDD thereof is preferentially set in the increase of transistor-on-current and the length size of the LDD regions of the picture elements TFTs 4 or the impurity concn. of the LDD thereof is preferentially set in the surpressing of transistor- offcurrent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device. More specifically, the present invention relates to the structure of a monolithic type thin film transistor in which a display pixel section and a peripheral circuit section for driving the display pixel section are formed on the same substrate.

[0002]

2. Description of the Related Art A thin film transistor (TFT) has been actively developed in recent years because it can be applied to an active matrix type liquid crystal display device and a contact type image sensor.
In particular, polycrystalline silicon (poly-S) is used as a thin film material.
When a TFT (poly-Si TFT) using i) is incorporated as an integrated circuit device, the peripheral drive circuit unit can be integrated on the same substrate as the display unit and the sensor unit, and therefore, it is drawing attention. Above all, a so-called LDD structure TFT (LD) having a low-concentration impurity region (LDD) of the same conductivity type and thinner than the region at the drain impurity region end of the TFT
D / TFT) is applicable to an active matrix type liquid crystal display device, etc., because it can reduce the electric field concentration at the edge of the drain impurity region and reduce the transistor leak current through the crystal grain boundaries and defect levels of polycrystalline silicon. ing. LD
The D-structure TFT is disclosed, for example, in Japanese Patent Publication No. 3-38755.

In order to clarify the background of the present invention, a conventional monolithic structure using an LDD / TFT will be briefly described with reference to FIG. A peripheral circuit portion 102 and a display pixel portion 103 are integrally formed on one main surface of the insulating substrate 101. In the figure, one thin film transistor (peripheral TFT) 104 that constitutes the peripheral circuit portion 102 and one thin film transistor (pixel TFT) 105 for a pixel switch included in the display pixel portion 103 are schematically shown. The peripheral TFT 104 and the pixel TFT 105 are the same insulating substrate 1
When it is formed on the liquid crystal display device 01, the process can be greatly simplified and shortened, and an inexpensive and high-performance small liquid crystal display device can be obtained. The peripheral TFT 104 is configured by using a polycrystalline silicon thin film 106 that becomes an active layer, and a gate electrode 108 is provided on the peripheral TFT 104 with an insulating film 107 interposed therebetween.
In this conventional example, a normal drain impurity region D and a source impurity region S are formed in the polycrystalline silicon thin film 106. Further, the metal wiring layer 110 is formed by patterning via the first interlayer insulating film 109, and the peripheral circuit portion 1 is formed.
02.

On the other hand, the pixel TFT 105 is also composed of the same polycrystalline silicon thin film 106, on which a gate electrode 111 is patterned through an insulating film 107. A metal wiring 110 is electrically connected to the source impurity region S of the pixel TFT 105 via a first interlayer insulating film 109. The pixel electrode 1 is formed in the drain impurity region D via the first interlayer insulating film 109 and the second interlayer insulating film 112.
13 is electrically connected. Further, at the end of the drain impurity region D and the end of the source impurity region S, low-concentration impurity regions of the same conductivity type, that is, LDD regions are provided.

In the above-mentioned conventional example, only the pixel TFT is LD
The peripheral TFT having a D structure has a normal structure. In recent years, it has been proposed to employ an LDD structure also in the peripheral circuit section 102 in order to improve the operation characteristics of the peripheral TFT. In this case, the pixel TFT 105 and the peripheral TFT 104 have the same LDD length dimension and LDD for the sake of simplicity of the process.
It was set to the impurity concentration.

[0006]

In order to prevent the bright spot defect of the display pixel, the pixel TFT is required to have a sufficiently low off current characteristic or leakage current characteristic. On the other hand, the peripheral TFT is required to have a sufficiently large drain current characteristic or ON current characteristic in order to drive the scanning circuit and the like included in the peripheral circuit portion at high speed. In this way, the pixel TFT and the peripheral T
The required characteristics are different from those of FT.

On the other hand, as the definition of the active matrix type liquid crystal display device becomes higher, it is necessary to shorten the channel length of the TFT formed integrally, and the channel length is 5 μm.
The following poly-Si TFTs are being formed. If the channel length is shortened, it becomes difficult to suppress the leak current to a low level and obtain a sufficiently large on-current characteristic. In particular, if the peripheral TFT is not provided with the LDD structure, if the channel length is shortened to 5 μm or less, the transistor threshold voltage shifts in the depletion direction, and a TFT having normal characteristics cannot be obtained. The LDD structure is effective for preventing the threshold voltage shift, and has been adopted in advancing miniaturization.

However, as described above, when the pixel TFT and the peripheral TFT have the LDD structure at the same time, the same LDD length dimension and the same LDD impurity concentration are set in order to simplify the process. However, if the LDD impurity concentration is made low and the LDD length dimension is made large in order to prioritize the suppression of the leak current of the peripheral TFT, there is a problem that the on-current of the peripheral TFT decreases and the scanning circuit does not operate. On the contrary, giving priority to the operation stabilization of the peripheral TFT,
A sufficient on-current can be secured by increasing the LDD impurity concentration and shortening the LDD length dimension, but conversely, the pixel T
There is a problem that the leak current of the FT increases and a pixel bright spot defect or the like occurs.

In addition to the LDD structure, Japanese Patent Publication No. 2-61032 discloses a technique for increasing the speed of a TFT circuit. This is a technology with a built-in peripheral drive circuit that enhances the mobility of TFTs by laser annealing the peripheral drive circuit area. However, this laser annealing process requires scanning with a laser beam, and thus the throughput is low and the operating characteristics of the transistors also vary. Therefore, it is actually difficult to perform miniaturization using this technique.

[0010]

In view of the above-mentioned problems of the prior art, the present invention effectively utilizes the LDD structure to form a display pixel portion and a peripheral circuit portion on the same substrate in a monolithic active matrix liquid crystal. The purpose is to increase the definition of the display device. The following measures have been taken in order to achieve this object. That is, a display pixel portion including a plurality of first thin film transistors (pixel TFTs) formed on one main surface, and a plurality of second pixel portions arranged around the display pixel portion.
One substrate having a peripheral circuit portion composed of thin film transistors (peripheral TFTs), another substrate having a counter electrode and arranged to face the one substrate, and a liquid crystal layer held between the both substrates. In the active matrix type liquid crystal display device including the above, both the pixel TFT and the peripheral TFT have a low concentration impurity region of the same conductivity type as the impurity region in at least one of the source impurity region, the drain impurity region and the channel region. It is characterized in that it has a non-single-crystal semiconductor layer (for example, a polycrystalline silicon semiconductor layer), and at least one of the length dimension and the impurity concentration of the low-concentration impurity regions of the pixel TFT and the peripheral TFT, that is, the LDD region, is different from each other. Specifically, LD of peripheral TFT
The D length dimension or the LDD impurity concentration is set with priority given to the increase in the transistor on-current, and the LDD length dimension or the LDD impurity concentration of the pixel TFT is set with priority given to the suppression of the transistor off current. Peripheral TFT is preferable
The LDD region is formed only on the drain impurity region side.

[0011]

Function: The LDD length dimension and the LDD impurity concentration are set to the pixel T.
By making the FT and the peripheral TFT different from each other, the respective operating characteristics can be optimized independently of each other, and the advantages of the LDD structure can be maximized. As a result, the channel lengths of the peripheral TFTs and the pixel TFTs can be effectively shortened, and a high resolution and high definition active matrix type liquid crystal display device can be realized.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic sectional view showing a basic structure of an active matrix type liquid crystal display device according to the present invention. As shown, an insulating substrate 1 made of quartz or the like
The peripheral circuit section 2 and the display pixel section 3 are integrally formed on the main surface of the. In order to simplify the illustration, the display pixel unit 3
Shows one switching pixel TFT 4, and the peripheral circuit section 2 shows only one driving peripheral TFT 5.

The pixel TFT 4 is formed by using a non-single crystal silicon thin film, for example, a polycrystalline silicon thin film 6 as an active layer, and a gate electrode 8 is patterned on the insulating film 7 via an insulating film 7. The gate electrode 8 is connected to the gate line and receives a selection signal from the peripheral circuit section 2. A metal wiring 10 is patterned on the pixel TFT 4 via a first interlayer insulating film 9. The metal wiring 10 constitutes a signal line and receives an image signal supplied from the peripheral circuit section 2. The metal wiring 10 is electrically connected to the source impurity region S of the pixel TFT 4 via the contact hole. A second layer is formed on the first interlayer insulating film 9.
An interlayer insulating film 11 is provided. A pixel electrode 12 is patterned on this, and is electrically connected to the drain impurity region D of the pixel TFT 4 through a contact hole. An LD having a predetermined length dimension and impurity concentration is provided at both ends of the source region S and the drain region D.
A D area is provided.

On the other hand, the peripheral TFT 5 included in the peripheral circuit section 2
Is also composed of the same polycrystalline silicon thin film 6,
A gate electrode 13 is also pattern-formed on the insulating film 7 via the insulating film 7. Source region S of peripheral TFT5
The drain region D and the drain region D are electrically connected to the metal wiring 10 through the contact holes, respectively, and constitute the peripheral circuit section 2 such as the vertical scanning circuit or the horizontal scanning circuit. Also, the peripheral TFT5
Also in the above, LDD regions having predetermined length dimensions and impurity concentrations are provided at both ends of the source region S and the drain electrode D, respectively. Although not shown, the counter substrate having counter electrodes formed thereon is bonded to the insulating substrate 1 having the peripheral circuit section 2 and the display pixel section 3 formed thereon with a predetermined gap. A liquid crystal layer is enclosed and filled in the gap between the two substrates.

As a feature of the present invention, at least one of the LDD length dimension and the LDD impurity concentration of the pixel TFT 4 and the peripheral TFT 5 is set to be different from each other.
Specifically, the LDD length dimension or LDD of the peripheral TFT 5
The impurity concentration is set with priority given to the increase in transistor on-current, and the LDD length dimension or the LDD impurity concentration of the pixel TFT 4 is set with priority given to suppression of transistor off-current. More specifically, the LDD length dimension of the peripheral TFT 5 is set shorter than the LDD length dimension of the pixel TFT 4. Alternatively, the LDD impurity concentration of the peripheral TFT 5 is set higher than the LDD impurity concentration of the pixel TFT 4. With such a structure, the driving capability of the peripheral TFT 5 can be sufficiently ensured, and the leak current of the pixel TFT 4 can be suppressed low. In this way, the channel length of the TFT can be shortened by optimizing and adopting the LDD structure.

FIG. 2 shows the relationship between the LDD length of the TFT and the transistor off current (leakage current). The vertical axis represents the leak current in a logarithmic memory, and three types of drain voltages (Vds) are set as parameters. This TFT has LDDs at the end of the source region and the end of the drain region, respectively.
While having a region, the channel length L is 3 μm and the channel width W is 30 μm. The LDD impurity concentration is set to 1 × 10 ¹³ cm ^-2 as a dose amount. As is clear from the graph of FIG. 2, the leak current can be suppressed by increasing the LDD length dimension. For example, LDD
When the length dimension is set to 1 μm, the leak current is Vds
Even at 15 V, it can be kept as low as 1 × 10 ⁻¹⁰ A or less. On the other hand, since the transistor on-state current can be secured at several hundred μA or more, there is no fear of insufficient writing even if the channel width W is narrowed to 3 μm, which is suitable as a pixel TFT.

FIG. 3 is a graph showing the relationship between the LDD dose of the TFT and the transistor on-current. This TFT has a channel length L set to 5 μm and a channel width W of 3 μm.
Is set to. As is clear from the graph, the transistor on-current also increases as the dose amount increases.
However, when the dose amount becomes 1 × 10 ¹³ cm ^-2 or more, the increasing tendency of the on-current becomes relatively gentle.

Next, a method of manufacturing the active matrix type liquid crystal display device according to the present invention will be described in detail with reference to FIGS. First, in step A, L is placed on the quartz substrate 51.
A poly-Si thin film 52 is formed with a film thickness of about 75 nm by the PCVD method. After that, if necessary, Si ⁺ ions are irradiated by ion implantation to amorphize the poly-Si thin film 52, and subsequently, furnace annealing is performed at a temperature of about 600 ° C. to increase the grain size of the polycrystalline silicon. . Alternatively, the grain size may be increased by previously forming an amorphous silicon thin film at a temperature of about 150 to 250 ° C. by using a plasma chemical vapor deposition method (PCVD method) and then annealing it.

Next, in step B, the poly-Si thin film is patterned to form the semiconductor region 53 for the peripheral TFT and the pixel TF.
The semiconductor regions 54 for T are formed in island shapes, respectively. Subsequently, the surfaces of these semiconductor regions are oxidized to form a gate oxide film with a thickness of about 60 nm. Furthermore, LPCV is formed on this gate oxide film.
About 10-20 silicon nitride film (Si ₃ N ₄ film) by D method
The film is formed with a film thickness of nm. In some cases, the surface of this Si ₃ N ₄ film is oxidized to form a SiO ₂ film with a film thickness of about 1 to ₂ nm. The gate insulating film 55 thus formed is made of SiO 2.
It is called an ONO structure because it is a stack of ₂ / Si ₃ N ₄ / SiO ₂ . By adopting this laminated structure, the gate breakdown voltage can be sufficiently secured and the reliability can be improved. After this,
To control the threshold voltage Vth of the TFT, if necessary, B ⁺
Ions are implanted with a dose amount of about 1 to 8 × 10 ¹² cm ^-2 .

In step C, a low resistance polycrystalline silicon film doped with phosphorus is formed on the gate insulating film 55 to a film thickness of about 350 nm and then patterned to form the gate electrode 5.
6, 57 are formed. The low resistance polycrystalline silicon film for the gate electrode may be formed by forming a non-doped polycrystalline silicon thin film and then diffusing phosphorus by using POCl ₃ gas, or by using a PSG film instead of POCl ₃ gas. Method or a LPCVD method to thermally decompose a mixed gas of SiH ₄ gas and PH ₃ gas to obtain a doped poly-S.
There is a method of forming an i thin film. Although either method may be used, the first method is adopted in this embodiment. In this embodiment, the channel length L and the channel width W of the TFT are
, Two types of L / W = 3 μm / 30 μm and 5 μm / 3 μm were prepared.

Next, in step D, an LDD region is formed. After forming the gate electrodes 56 and 57, the portion forming the peripheral circuit portion is covered with a resist 58. When forming an n-channel type pixel TFT, As ⁺ or P ⁺ ions are implanted only in the display pixel portion at a dose amount of 0.1 to 1.5 × 10 ¹³ cm ^-2 . In the case of forming a p-channel type pixel TFT, B ⁺ ions may be similarly implanted with a dose amount of 0.1 to 2.0 × 10 ¹³ cm ⁻² instead of As ⁺ or P ⁺ ions. Next, in step E, after removing the resist 58, the display pixel portion is newly covered with the resist 59 selectively. When forming an n-channel type peripheral TFT for the exposed peripheral circuit portion, As ⁺ or P ⁺ ions are added to 0.
Implant with a dose amount of about 2 × 10 ^{13 to} 2.0 × 10 ¹⁴ cm ^-2 . B when forming a P-channel type peripheral TFT
⁺ Ions are implanted with a dose amount of about 0.1 to 4.0 × 10 ¹³ cm ^-2 . For example, the dose is 0.5 x 1 for pixel TFT
It is desirable to set it to 0 ¹³ cm ^-2 and set it to about 1 × 10 ¹³ cm ^-2 in the peripheral TFT. After the ion implantation is completed, the resist 59 is peeled off. However, LD of pixel TFT and peripheral TFT
When the D impurity concentration is set to be equal, the resist 58
The ion implantation using the two masks of the resist 59 and the resist 59 is not necessary.

Then, in step F shown in FIG. 5, a source region and a drain region are formed. Gate electrode 56,5
7 from both sides, in the case of a pixel TFT, 0.1 to 1.
A resist 61 is patterned so that the LDD region 60 has a length dimension of 5 μm and a peripheral TFT of 0.05 to 1.5 μm. In the case of pixel TFT, LDD region 6
When the length dimension of 0 is 0.1 μm or less, the leak current increases and causes a pixel bright spot defect. Also, the length dimension is 1.5
If the thickness is set to more than μm, the resistance of the LDD region 60 becomes large, which causes insufficient writing of image signals to the pixels.
In the case of the peripheral TFT, if the LDD region 60 is set to 0.05 μm or less, the leak current becomes large and the on / off ratio becomes insufficient. On the other hand, if the thickness is set to 1.5 μm or more, the ON current cannot be sufficiently large, which is not suitable for the scanning circuit. In this embodiment, the LDD length of the pixel TFT is 1 μm.
And the LDD length dimension of the peripheral TFT is set to 0.5 μm. With the resist 61 patterned, As ⁺ or P ⁺ ions are implanted at a dose of 1 to 3 × 10 ¹⁵ cm ^-2 to form a source region 61 and a drain region 62 of the n-channel TFT. In addition, p-channel type TF
When forming T, B is replaced with As ⁺ or P ⁺ ion.
⁺ Implant ions.

Next, in step G, a first interlayer insulating film 63 made of PSG is formed by LPCVD to a film thickness of about 600 nm. Subsequently, annealing is performed at 1000 ° C. for 10 to 30 minutes in a nitrogen gas atmosphere to activate the source region, the drain region, and the LDD region.

Finally, in step H, the first interlayer insulating film 63 is formed.
A contact hole is formed in the substrate, aluminum to be the metal wiring 64 is formed in a film thickness of about 600 nm, and patterning is performed. A second interlayer insulating film 65 made of PSG is further formed thereon with a film thickness of about 400 nm. Then, a silicon nitride film (P-SiNx film) is formed with a film thickness of about 100 nm by the PCVD method. Although not shown, since this P-SiNx film contains a large amount of hydrogen, it is necessary to anneal it after forming it to form a TFT.
Can be effectively hydrogenated. Hydrogenation can reduce the defect density of polycrystalline silicon and suppress the leak current of TFT due to the defects. After hydrogenation P-S
The iNx film is entirely removed by etching. After that, although not shown, the second interlayer insulating film 65 and the first interlayer insulating film 63 are opened by etching, and then a transparent conductive film such as ITO is formed with a film thickness of, for example, 140 nm and patterned by etching to form pixel electrodes. To form. The completed state of the integrated circuit board manufactured in this way is as already shown in FIG.

FIG. 6 shows another embodiment of the active matrix type liquid crystal display device according to the present invention. Basically, the structure is the same as that of the embodiment shown in FIG. 1, and corresponding parts are designated by corresponding reference numerals or reference symbols to facilitate understanding. The difference is that LD of peripheral TFT5
That is, the D region is formed only on the drain region D side. In the case of the pixel TFT 4, since the liquid crystal layer (not shown) is AC-driven, the source side and the drain side are alternately switched.
It is necessary to provide the LDD regions on both sides of the end of the source region and the end of the drain region. On the other hand, in the case of the peripheral TFT 5, the LDD region may be provided at least only on the drain side. Peripheral TFT
When the LDD region is formed with a resist mask, the LDD region can be selectively formed by covering only the drain side with the resist mask. LD on both sides of the source and drain
Since the LDD resistance can be reduced as compared with the case where the D region is formed, the transistor on-current can be made sufficiently large. With such a structure, it becomes easier to determine the LDD length dimension and the LDD impurity concentration that simultaneously satisfy the required specifications of the peripheral TFT and the pixel TFT. The leakage current is higher than that in the case where the LDD regions are provided at both ends of the source and the drain, but in the case of the peripheral TFT, there is practically no problem.

FIG. 7 shows the LDD length dimension and the transistor on-current of both the TFT having the LDD region only at the drain end (one side LDD) and the TFT having the LDD provided at both ends of the source and the drain (both sides LDD). It is a graph which shows the relationship of. The channel length L of the TFT was set to 3 μm and the channel width W was set to 30 μm. The drain voltage is set to 15V. As is clear from this graph, when the LDD length dimension is set to 0.5 μ, for example, one side LDD can obtain an ON current that is three times or more that of both sides LDD, and the peripheral drive circuit operates at higher speed. It will be possible to do.

In the above-described embodiment, polycrystalline silicon is used as the gate electrode of the TFT and ON is used as the gate insulating film.
Although the O structure is adopted and aluminum is used as the metal wiring material, the present invention is not limited to this. As the gate electrode, for example, silicide or polycide can be used. Alternatively, Ta as a metal gate electrode,
You may use Al, Cr, Mo, Ni, these alloys, etc. As the gate insulating film, for example, silicon nitride or tantalum oxide can be used. Further, as the wiring material, Ta, Cr, Mo, Ni, alloys thereof, or the like can be used. It is needless to say that the present invention can be applied to any of planar type, normal stagger type and reverse stagger type thin film transistors.

[0028]

As described above, according to the present invention, by setting different values for the LDD length dimension and the LDD impurity concentration between the peripheral TFT and the pixel TFT, the TFTs having different required characteristics can be optimized. Can be designed. As a result, it has become possible to realize a miniaturized TFT having a channel length of 3 μm or less. Therefore, the present invention enables higher resolution and higher definition of the active matrix type liquid crystal display device, and its effect is great.

[Brief description of drawings]

FIG. 1 is a sectional view showing a basic configuration of an active matrix type liquid crystal display device according to the present invention.

FIG. 2 is a graph showing a relationship between an LDD length dimension and a leak current of a thin film transistor according to the present invention.

FIG. 3 is a graph showing the relationship between the LDD dose amount and the transistor on-current of the thin film transistor according to the present invention.

FIG. 4 is a process drawing showing the manufacturing method of the active matrix liquid crystal display device according to the present invention.

FIG. 5 is also a manufacturing process drawing.

FIG. 6 is a schematic cross-sectional view showing another embodiment of the active matrix type liquid crystal display device according to the present invention.

FIG. 7 is a graph showing the relationship between the LDD length dimension of a thin film transistor and the transistor on-current according to the present invention.

FIG. 8 is a cross-sectional view showing an example of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Peripheral circuit part 3 Display pixel part 4 Pixel TFT 5 Peripheral TFT 6 Polycrystalline silicon thin film 7 Gate insulating film 8 Gate electrode 9 First interlayer insulating film 10 Metal wiring 11 Second interlayer insulating film 12 Pixel electrode 13 Gate electrode D drain region S source region LDD low concentration impurity region

Claims (5)

[Claims] 1. A peripheral circuit comprising a plurality of first thin film transistors formed on one main surface and a plurality of second thin film transistors arranged around the display pixel portion. A liquid crystal display device comprising: one substrate having a portion; another substrate having a counter electrode, which is opposed to the one substrate; and a liquid crystal layer held between the two substrates. The second thin film transistor has a non-single-crystal semiconductor layer having a low-concentration impurity region of the same conductivity type as the impurity region in at least one of a source impurity region and a drain impurity region, and a channel region,
A liquid crystal display device, wherein at least one of a length dimension and an impurity concentration of low-concentration impurity regions of the first and second thin film transistors is different from each other. 2. The liquid crystal display device according to claim 1, wherein the second thin film transistor has a low concentration impurity region formed only on the drain impurity region side. 3. The length dimension or impurity concentration of the low-concentration impurity region of the second thin film transistor is set by giving priority to an increase in transistor on-current, and the length dimension of the low-concentration impurity region of the first thin film transistor or 2. The liquid crystal display device according to claim 1, wherein the impurity concentration is set by giving priority to suppression of transistor off current. 4. An active matrix display pixel unit in which gate lines and signal lines arranged in a matrix, switching thin film transistors arranged at respective intersections thereof, and liquid crystal pixel electrodes connected to the switching thin film transistors are integratedly arranged. And a thin film transistor in the peripheral circuit part and the switching thin film transistor connected to the active matrix display pixel part and having a peripheral circuit part for supplying a selection signal and an image signal to the gate line and the signal line, respectively. Is composed of a non-single-crystal silicon thin film having an LDD low-concentration impurity region, and at least one of the length dimension and the impurity concentration of the low-concentration impurity region of the thin film transistor in the peripheral circuit portion is the low-concentration impurity region of the switching thin film transistor. Different from the area The liquid crystal display device, characterized in that it was constructed as. 5. The length dimension or the impurity concentration of the low concentration impurity region of the thin film transistor in the peripheral circuit portion is set by giving priority to the increase of the transistor on-current, and the length dimension of the low concentration impurity region of the switching thin film transistor or 5. The liquid crystal display device according to claim 4, wherein the impurity concentration is set with priority given to suppression of transistor off current.