JP3647384B2 - Thin film semiconductor device, manufacturing method thereof, and display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a thin film semiconductor device, and more particularly to improvements for miniaturization, cost reduction, and performance improvement of the device.
[0002]
[Prior art]
In recent years, the development of flat displays typified by liquid crystal display panels has been remarkable.
In a liquid crystal display panel, an active matrix type in which a switching element is arranged for each pixel is widely used.
In other display panels such as a plasma display, an electroluminescence display, and a field emission display, a switching element is arranged for pixel control.
[0003]
As these switching elements, MIM (metal-insulator-metal) and TFT (thin-film-transistor) are used.
Of these, TFTs are excellent in response speed, but due to the complexity of the production, the production cost is high, and the cost reduction is required. Further, in a display panel such as a liquid crystal display device, a region where a switching element is arranged is a non-display region that is not used for pixel display. Therefore, downsizing of a TFT is required for fine display quality. ing. Further, not only in display panels but also in other devices, downsizing of TFTs is required from the viewpoint of high-density mounting on a substrate.
[0004]
A top gate type MIS (metal-insulator-semiconductor) TFT widely used in a liquid crystal display device or the like is shown in FIGS.
A TFT disposed on an insulating substrate 1 made of glass or the like with an undercoat layer 2 interposed therebetween includes a semiconductor thin film 3 made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), or the like. N-type or P-type impurity ions are implanted into the source region 3b and the drain region 3c of the semiconductor thin film 3, respectively. When a voltage is applied to the gate electrode 5a disposed across the insulating film 4 in the channel region (active region) 3a of the semiconductor thin film 3, the source electrode wiring 8b and the drain electrode wiring 8c are electrically connected.
[0005]
The undercoat layer 2 is for preventing impurities from entering the semiconductor thin film 3 from the substrate 1 and is made of, for example, silicon oxide. The gate insulating film 4a is made of, for example, silicon oxide.
The gate electrode 5a is made of a refractory metal such as chromium so that it can withstand heat treatment for activating the semiconductor thin film in the manufacturing process.
[0006]
Such a TFT has been manufactured, for example, as follows.
First, as shown in FIG. 29A, the undercoat layer 2 and the semiconductor thin film 3 are formed on the surface of the substrate 1, and the formed semiconductor thin film 3 is etched into a predetermined pattern using the resist layer 18 as a mask. Process.
Next, the insulating film 4 and the gate electrode 5 a are formed on the semiconductor thin film 3. For example, as shown in FIG. 29B, after forming the insulating film 4 made of silicon oxide and the conductive film 5 made of chromium so as to cover the semiconductor thin film 3, the conductive film 5 is etched by using the resist layer 19 as a mask. Is processed into a predetermined pattern to form the gate electrode 5a.
[0007]
Using the formed gate electrode 5a and insulating film 4 as a mask, P-type or N-type impurity ions are implanted into the semiconductor thin film 3 as shown in FIG. 30A to form a channel region 3a, a source region 3b, and a drain. Region 3c is formed.
In the case of a TFT having a so-called LDD (lightly-doped drain) structure, ions are further implanted into a region separated from the channel region 3a among the source region 3b and the drain region 3c formed as described above. Increase the ion concentration in that region.
[0008]
In the case of a TFT having a so-called offset structure, ion implantation similar to the above is performed using a mask covering the periphery of the gate electrode 5a.
Next, as shown in FIG. 30B, an insulating film 6 made of, for example, silicon oxide is formed so as to cover them, and the source of the semiconductor thin film 3 is formed on the insulating film 6 by etching using the resist layer 21 as a mask. A contact window 6a for connecting the region 3b and the drain region 3c to the external wiring is formed.
After the contact window 6a is formed, a conductive film 8 made of, for example, aluminum is formed so as to cover them as shown in FIG. 30C, and further, the source electrode wiring 8b is etched by etching using the resist layer 20 as a mask. Then, the drain electrode wiring 8c and the like are formed, and the TFT shown in FIGS. 28A and 28B is obtained.
[0009]
In an actual device, in the same manner, other signal wirings such as wiring for connecting the source electrode wiring to a signal source or the like are formed on the upper layer through an insulating film. In general, elements are designed such that errors and variations in the manufacturing process do not cause variations in the characteristics of the finished product. This design margin for stable manufacturing can be cited as one of the factors that hinder downsizing of the device. In the manufacturing of the conventional TFT as described above, it is inevitable to design in consideration of variations in the size of a mask used for etching and ion implantation and misalignment between the mask and a substrate (or a thin film to be processed). . For example, in order to form a contact window, it is necessary to secure a sufficient distance between the gate electrode and a portion where the contact window is arranged in consideration of them. Therefore, the conventional TFT needs to have a longer length in the gate length direction than a functionally desirable design.
[0010]
The design margin as described above becomes a factor of deteriorating the characteristics of the device and the device using the device. For example, the distance between the end of the channel region and the source / drain electrode wiring, that is, the distance between the gate electrode and the contact window greatly affects the magnitude of the source-drain current in the ON state of the element. Even if the impurity concentration of the source / drain region is increased, it is difficult to lower its electrical resistance to the same level as that of metal wiring. In addition, if the impurity concentration of the source / drain region is extremely increased, the reliability of the element is lowered. The margin between the gate electrode and the contact window that increases the electrical resistance between the drains reduces the amount of current in the ON state of the device.
[0011]
[Problems to be solved by the invention]
The present invention is to solve the above problems, and to provide a thin film semiconductor device having a large ON current and a small area suitable for power saving, downsizing and display refinement of equipment. Objective. Another object of the present invention is to provide such an excellent thin film semiconductor element at low cost.
[0012]
[Means for Solving the Problems]
The present invention greatly reduces the area of the source / drain region of the transistor, thereby reducing the area of the device. Also, the ON current of the element is increased by greatly reducing the distance between the gate electrode and the source / drain electrodes (wiring).
Furthermore, the device manufacturing process is greatly simplified.
[0013]
According to the present invention, the processing of the outer shape of the semiconductor thin film and the formation of each region (channel region, source region, and drain region) in the semiconductor thin film are performed by processing using other components such as a gate electrode as a mask. Is called. That is, the gate electrode or the like is processed first, and the semiconductor thin film is processed in a self-aligned manner corresponding to the shape of these components. Therefore, the design margin required for manufacturing the conventional thin film semiconductor device can be reduced to the minimum, and a thin film semiconductor device having a small size and excellent characteristics is realized. In addition, simplification of the manufacturing process such as reduction in the number of masks used is realized.
[0014]
In the present invention, in the manufacture of a thin film semiconductor device, an ion implantation region is formed by implanting impurity ions into a predetermined region of a semiconductor thin film using a gate electrode formed by overlapping an insulating film as a mask. The semiconductor thin film is processed into a predetermined shape by etching using an element such as an electrode formed in advance as a mask. A semiconductor thin film can be processed without using a mask only for processing so that a source region and a drain region into which impurity ions are implanted are arranged opposite to each other with a channel region (active region) interposed therebetween. Become.
[0015]
The thin film semiconductor element is manufactured by, for example, the following method.
First, a semiconductor thin film serving as an active region is formed on an insulating substrate, and a first insulating film, a conductive film, and a second insulating film are stacked thereon.
Next, the conductive film is processed into a predetermined pattern by etching to form a gate electrode. At this time, the second insulating film formed on the conductive film is processed into the same pattern.
For example, after a first resist layer having a predetermined pattern is formed on the surface of the second insulating film, the first conductive film becomes a gate electrode when the second insulating film and the first conductive film are etched using the first resist layer as an etching mask. To be processed. Note that when the first insulating film formed under the conductive film is simultaneously processed, a gate insulating layer between the gate electrode and the semiconductor thin film is also formed. After the etching, the first resist layer is removed.
Next, using the formed gate electrode as a mask, N-type or P-type impurities are implanted into the semiconductor thin film disposed below the gate electrode. Here, the region of the semiconductor thin film whose surface is covered with the gate electrode is processed into a channel region of the transistor. Impurities are implanted into a predetermined region of the semiconductor thin film through the first insulating film or directly using the gate electrode as a mask. In order to prevent a short circuit between the source and the drain of the transistor to be formed, a second resist layer is preferably formed which covers a region to be a side end portion of the channel region in the semiconductor thin film and used as a mask together with the gate electrode. . After the ion implantation, the second resist layer is removed.
[0016]
If the insulating film covering the surface of the semiconductor thin film is removed prior to the implantation of the impurity ions into the semiconductor thin film, the impurity ions can be implanted with low energy and high efficiency compared to the case of implanting the impurity ions through the insulating film. Further, impurity ions can be easily implanted at a high concentration. A variation in implantation amount due to variations in the thickness of the insulating film can be prevented, and a thin film semiconductor device with good uniformity in electrical characteristics can be obtained.
Next, a frame-shaped insulating wall that covers the side wall of the gate electrode is formed. For example, an insulating film is uniformly formed on the surface of the substrate, and then the formed insulating film except for the periphery of the gate electrode is removed by anisotropic etching. The thickness of the insulating film formed at the periphery of the gate electrode is thicker than that in the flat region, that is, the region where the gate electrode is disposed and the region where the first insulating layer (or semiconductor thin film) is exposed. Therefore, the insulator can be left only around the gate electrode by appropriately setting the subsequent etching conditions.
[0017]
After forming the insulating wall, a second conductive film is formed to cover the surface of the insulating substrate on which the semiconductor thin film is formed, and the second conductive film is formed by etching using a resist layer having a predetermined pattern as a mask. A wiring member connected to the source region and the drain region is formed by processing. In this etching, since the gate electrode and the insulating wall also function as a mask, the semiconductor thin film disposed in the lower layer thereof is processed into a predetermined shape having a source region and a drain region.
After forming the source electrode and the drain electrode, a third insulating film is formed on the entire surface. Next, when an opening is formed in the third insulating film in the region covering the gate electrode, and another wiring member such as a scanning signal line connected to the gate electrode is formed in the region including the opening, a semiconductor element is obtained.
[0018]
If impurity ions are implanted after forming the insulating wall, impurity ions are not implanted into the region covered by the insulating wall of the semiconductor thin film, so that a thin film semiconductor element having a so-called offset structure is obtained.
In addition, after the formation of the insulating wall and before the formation of the second conductive film, the same kind of impurity ions as those used for the previous ion implantation are implanted into the semiconductor thin film using the gate electrode and the insulating wall as a mask. If a sub-region having a higher impurity ion concentration is formed in the semiconductor thin film, a semiconductor element having a so-called LDD (lightly-doped drain) structure can be obtained.
A so-called CMOS transistor using a pair of a P-type transistor and an N-type transistor is also manufactured by the same method as described above. That is, at the time of implanting one impurity ion, a mask having a pattern covering a region (or a region already implanted) into which the other impurity ion is to be implanted may be used.
Preferably, after the formation of the third insulating film, the semiconductor thin film is subjected to heat treatment for activation.
[0022]
The manufacturing method of the present invention is also applied to a semiconductor element having a so-called LDD (lightly doped drain) structure. In general, according to etching using a mask, the outer shape on the side adjacent to the mask of the resulting pattern substantially matches that of the mask, but the outer shape on the other side is larger. Therefore, the outer shape of the surface (upper surface) contacting the insulating wall of the semiconductor thin film obtained by forming the frame-shaped insulating wall so as to surround the gate electrode and processing the semiconductor thin film into a predetermined pattern is substantially the same as that of the insulator side wall. Although coincident, the outer shape of the other surface (lower surface) is larger than that of the insulating wall. Using the insulating wall and the gate electrode as a mask, the impurity is implanted and the same impurity as that previously implanted into the semiconductor thin film in the region exposed from the insulating wall is implanted, and the impurity concentration is covered on the insulator side wall. By making it higher than that of the region, an LDD structure can be obtained.
[0023]
After forming an insulating wall covering the side surface of the gate electrode, ions are implanted into the semiconductor thin film using the insulator side wall and the gate electrode as a mask, whereby an offset structure thin film semiconductor element can be obtained.
When P-channel and N-channel semiconductor elements are formed on the same substrate as in a CMOS transistor, second resist layers having different patterns are used for implanting P-type and N-type impurities into the semiconductor thin film. Use it.
[0024]
  The thin film semiconductor element of the present invention is
A channel region that does not include impurity ions, and a source region and a drain region that are formed on both sides of the channel region and into which impurity ions are implanted.A semiconductor thin film;
  Arranged to face the channel region with a gate insulating film interposedA gate electrode;
  A frame-like insulating wall covering the peripheral edge of the gate electrode;
  A source wiring connected to the source region;
  A drain wiring connected to the drain region;Prepared,
  In the projection in the overlapping direction,The gate electrode;SaidInsulation wall,SaidSource wiring andSaidDrain wiringHowever, the side wall surface defining the periphery of the semiconductor thin film is substantially flush with the side wall surface defining the periphery of the semiconductor thin film..
[0027]
The thin film semiconductor element of the present invention is used as a switching element for controlling the operation of a light adjusting means or a light emitting means in a display panel such as a liquid crystal display panel or an organic EL display panel.
[0028]
The present invention is particularly useful for a so-called top gate type semiconductor element in which a gate electrode is arranged in an upper layer than a semiconductor thin film, but a so-called bottom gate type semiconductor in which a gate electrode is arranged in a lower layer than a semiconductor thin film. It is also useful for devices.
Impurities for forming the source / drain regions are implanted into the semiconductor thin film by, for example, a plasma doping method. The source / drain regions can also be formed by a method in which impurities are introduced into the wiring material to be connected to them and then diffused into the semiconductor thin film by heat treatment.
[0029]
For example, phosphorus is used as an impurity in the N-channel transistor. For example, boron is used as an impurity in the P-channel transistor. According to the present invention, since a thin film semiconductor element having excellent response characteristics can be obtained, a large-screen display panel can be manufactured by using the thin film semiconductor element as a switching element.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
Example 1
[0032]
In this embodiment, an example of a thin film transistor (TFT) will be described as a thin film semiconductor element of the present invention.
The TFT of this example is shown in FIGS.
On the surface of the insulating substrate 1, a semiconductor thin film 3 made of, for example, polycrystalline silicon is formed.
The semiconductor thin film 3 has a channel region (active region) 3a not containing impurities, and a source region 3b and a drain region 3c into which P-type or N-type impurities are implanted.
The undercoat layer 2 sandwiched between the insulating substrate 1 and the semiconductor thin film 3 is for suppressing the diffusion of impurities from the insulating substrate 1 to the semiconductor thin film 3 and the generation of lattice defects on the surface of the channel region 3a. .
[0033]
A gate electrode 5a is formed on the upper surface of the semiconductor thin film 3 with a gate insulating film 4a therebetween so as to cover almost the entire surface of the channel region 3a. The length of the channel region 3 a of the semiconductor thin film 3 is substantially equal to that of the gate electrode 5. The upper surface of the gate electrode 5a is covered with an insulating film 6 made of silicon oxide, and its side wall surface is covered with a frame-like insulating wall 13a. The outer diameter of the insulating wall 13a is substantially equal to that of the semiconductor thin film 3 or the gate insulating film 4a disposed therebelow.
The periphery of the semiconductor thin film 3 is covered with a gate electrode 5a, an insulating wall 13a, a source electrode wiring 8b, and a drain electrode wiring 8c. The semiconductor thin film 3 in the region covered with the gate electrode 5a across the gate insulating film 4a constitutes a channel region 3a in which no impurity is implanted. The semiconductor thin film 3 in the region covered with the insulating wall 13a and corresponding to the pair of side portions of the channel region 3a also forms part of the channel region 3a. That is, the source region 3b and the drain region 3c are separated by the high-resistance channel region 3a. Source region 3b is covered with insulating wall 13a or source electrode wiring 8b. Similarly, the drain region 3c is covered with the insulating wall 13a or the drain electrode wiring 8c.
[0034]
Both source electrode wiring 8b and drain electrode wiring 8c are electrically insulated from gate electrode 5a by insulating film 6, insulating wall 13a and the like. The surface of the substrate 1 on which the semiconductor thin film 3 and the like are disposed is covered with an insulating film 9 made of silicon oxide. The signal wiring 10 formed on the insulating film 9 is electrically connected to the gate electrode 5a in a contact window 9a provided in the insulating film 9 above the gate electrode 5a.
[0035]
The TFT of this example is manufactured as follows, for example.
As shown in FIG. 3A, an undercoat layer 2 made of, for example, silicon oxide is formed on an insulating substrate 1, and a semiconductor thin film 3 made of polycrystalline silicon is further formed thereon. Thereafter, an insulating film 4 made of silicon oxide and a conductive film 5 made of molybdenum / tungsten alloy are formed so as to cover the semiconductor thin film 3. An insulating film 6 made of, for example, silicon oxide is formed on the entire surface of the insulating substrate 1 so as to cover them.
Next, a resist layer 11 is formed so as to cover a region where the channel region 3 a is to be disposed on the semiconductor thin film 3. The insulating film 4 and the conductive film 5 are etched using the formed resist layer 11 as a mask. By this etching, the conductive film 5 is processed into the gate electrode 5a of the TFT to be obtained, and the insulating film 4 covering the conductive film 5 is processed into the gate insulating film 4a.
[0036]
After removing the resist layer 11, impurity ions are implanted into a predetermined region (ion implantation region 3 f) of the semiconductor thin film 3. Here, since the gate electrode 5a functions as a mask, impurity ions are not implanted into the semiconductor thin film 3 in the region covered with the surface. The source region 3b and the drain region 3c formed by implanting impurity ions in the TFT to be obtained are arranged with the channel region 3a interposed therebetween. Therefore, prior to ion implantation, in order to prevent a short circuit between the source and drain of the obtained TFT, preferably a pair of mutually parallel edges of the rectangular gate electrode 5a is formed as shown in FIG. A resist layer 12 is formed so as to cover it. For example, phosphine (PH) is applied to the semiconductor thin film 3 using the resist layer 12 and the gate electrode 5a as a mask._Three) Phosphorus as an N-type impurity is implanted by a plasma doping method using a gas.
[0037]
After removing the resist layer 12, as shown in FIG. 3C, an insulating film 13 made of, for example, silicon oxide is formed so as to cover the entire surface of the substrate 1 on which the semiconductor thin film 3 is disposed. In general, when a film is formed on an uneven surface, the thickness of a stepped region of the obtained film is larger than that of a flat region. That is, as shown in FIG. 3C, the thickness of the formed insulating film 13 in the flat region is larger than that around the gate electrode 5a. Therefore, when anisotropic etching (dry etching) is performed in the normal direction of the substrate 1, only the portion around the gate electrode 5 a remains in the insulating film 13, and as shown in FIG. A frame-like insulating wall 13a covering the side surface of the electrode 5a is formed in a self-aligning manner. Further, by this etching, the insulating film 4 in the region where the gate electrode 5a is not disposed is removed, and the gate insulating film 4a is formed.
[0038]
After the formation of the insulating wall 13a, wiring such as the drain electrode wiring 8b and the source electrode wiring 8c is formed. As shown in FIG. 4B, a conductive film 8 made of, for example, titanium is formed so as to cover the surface of the substrate 1 on which the substrate 1 is disposed. After the resist layer 14 is formed so as to cover the region to be processed into the wiring of the formed conductive film 8, the unnecessary region of the conductive film 8 is removed by etching. As a result, as shown in FIG. 4C, the source electrode wiring 8b, the drain electrode wiring 8c, and the like are formed.
By this etching, the semiconductor thin film 3 in a region exposed before the formation of the conductive film 8 and not covered with the resist layer 14 is removed, and the gate electrode 5a, source electrode wiring 8b, drain electrode wiring 8c, insulating wall 13a, and Only the semiconductor thin film 3 in the region covered with the resist layer 14 remains. Therefore, the semiconductor thin film 3 is divided into individual pieces each including a source region 3b and a drain region 3c into which ions are implanted in a self-aligning manner, and a channel region 3a sandwiched between them.
[0039]
After removing the resist layer 14, an insulating film 9 made of silicon oxide is formed so as to cover the surface of the substrate 1.
After the insulating film 9 is formed, for example, the substrate 1 is heat-treated at 400 to 600 ° C., thereby activating the source region 3b and the drain region 3c of the semiconductor thin film 3 into which phosphorus has been implanted, and the source region 3b and the source The contact resistance between the electrode wiring 8b and between the drain region 3c and the drain electrode wiring 8c is reduced.
[0040]
Next, a signal wiring and other signal wirings connected to each electrode such as a scanning signal line and an image signal line are formed.
As shown in FIG. 5, a resist layer 16 having a pattern in which a region for forming a contact between a wiring to be formed and each electrode is formed is formed. By etching using the resist layer 16 as a mask, the exposed insulating film 15 is removed to form a contact window 9a.
Next, for example, a conductive film made of aluminum is formed on the entire surface of the substrate 1, and this conductive film is further processed into a predetermined pattern to form signal wirings 10 such as scanning signal lines and image signal lines. 1 and the TFT shown in FIG. 2 are obtained.
[0041]
As described above, according to this embodiment, the semiconductor thin film is formed in a self-aligned manner. That is, the region processed into the channel region (or the region processed into the source / drain regions) is defined by the shape of the gate electrode. The shape of the semiconductor thin film is defined by the shape of the source / drain electrodes that are processed at the same time. According to the present invention, the constituent elements of these TFTs are formed in a self-aligned manner, so that a semiconductor element with stable characteristics can be manufactured.
[0042]
According to the present invention, since the distance between the gate electrode and the source / drain electrode is defined by the thin insulating wall, the distance between them can be reduced as compared with the conventional device. Further, since the resistance component in the source / drain region when the element is ON can be minimized, the resistance between the source and the drain is small and the ON current is large as compared with the conventional element. Furthermore, since a sufficient contact area can be ensured between the source / drain regions of the semiconductor thin film and the electrode member, the contact resistance between them is lower than that of the conventional element.
[0043]
Furthermore, the area occupied by the element can be made smaller than that of the conventional element. Therefore, it becomes possible to arrange with higher density. Further, the use of the TFT of this embodiment as a switching element for controlling each pixel of a display panel such as a liquid crystal display panel or an organic EL display panel improves the aperture ratio of the pixels of the display panel and enhances the display. Contribute to etc.
Furthermore, according to the present invention, the process of manufacturing the device is greatly simplified. For example, unlike the conventional device, it is not necessary to form a contact window in the insulating film disposed between the source / drain regions of the semiconductor thin film and the electrode member in order to electrically connect them.
[0044]
An example in which the TFT of this embodiment is used as a switching element of a liquid crystal display panel is shown in FIGS.
The transparent pixel electrode 201 arranged for each pixel on the array substrate 200 is integrated with the drain electrode of the TFT. The scanning signal line 202 is connected to the gate electrode of the TFT as the switching element 7. The image signal line 203 functions as a TFT source line. The connection between the source and drain of the TFT is ON / OFF controlled by a signal input to the TFT via a scanning signal line 202 from a scanning signal drive circuit (not shown). When the source-drain connection is turned on, the image signal from the image signal line 203 is input to the transparent pixel electrode 201, and the transparent counter electrode 205 disposed opposite to the transparent pixel electrode 201 and the liquid crystal layer 204 is disposed. A voltage is applied between the two.
[0045]
The electric field formed between the two electrodes changes the orientation of the liquid crystal molecules in the liquid crystal layer 204 and changes the polarization direction of the light emitted from the backlight 206. The light irradiated from the backlight 206 and transmitted through the polarizing plate 207a is rotated depending on the orientation of the liquid crystal molecules when passing through the liquid crystal layer 204, and then the color filter layer 210 disposed on the counter substrate 208 side and the polarized light. The light passes through the plate 207b. By this optical rotation, the luminance of the light displayed on the pixel is adjusted. An alignment film 209 for defining the initial alignment of the liquid crystal material in the liquid crystal layer 204 is formed on the surface of the array substrate 200 and the counter substrate 208 facing the liquid crystal layer 204.
Since the TFT of this embodiment can increase the ON current as compared with the conventional TFT, by using it, the writing time to the pixel can be shortened. Further, it is more effective in a large screen panel in which a large number of pixels are arranged. A region where TFTs serving as non-display regions are arranged can be reduced, which can contribute to an improvement in aperture ratio, which is a problem in the development of liquid crystal display devices.
[0046]
Similarly, an example applied to a switching element of an organic EL display panel will be described with reference to FIG.
On the glass substrate 300, an organic EL material layer 301 and a pair of electrodes 302 and 303 are disposed so as to sandwich the organic EL material layer 301. The TFT as the switching element 7 disposed in each light emitting element is disposed between the electrodes 302 and 303. ON / OFF control of connection of voltage signal to be applied. By using the TFT of this embodiment having a high current supply capability for the switching element 7, the current can be sufficiently supplied to the organic EL material layer 301, and display with high luminance is possible.
Needless to say, the thin film semiconductor element of the present invention can be used not only for liquid crystal display panels and organic EL display panels but also for controlling pixels of other display panels.
Further, it can be used as a drive switch for a circuit portion of another device.
[0047]
Example 2
In this embodiment, an example of an LDD (lightly-doped drain) TFT having a semiconductor thin film arranged in the same manner as that of Embodiment 1 will be described.
The TFT of this example is shown in FIG. The structure of this TFT is almost the same as that of the TFT of Example 1. However, in this TFT, each of the source region 3b and the drain region 3c of the semiconductor thin film 3 includes a high concentration region 3d and a low concentration region 3e having different impurity ion concentrations. The high concentration region 3d is disposed only under the source electrode wiring 8b or the drain electrode wiring 8c, and the low concentration region 3e is disposed only under the insulating wall 13a between the channel region 3a and the high concentration region 3d. Yes. Therefore, the semiconductor thin film 3 is connected to the source electrode wiring 8b and the drain electrode wiring 8 only in the high concentration region 3d.
[0048]
This TFT is manufactured, for example, as follows.
In the same manner as in Example 1, after the gate electrode 5a is formed on the insulating substrate 1, ions are implanted into the semiconductor thin film 3 as shown in FIG. 7A, and an insulating wall 13a is further formed. After forming the insulating wall 13a, as shown in (b), the ion concentration of ions of the same type as those used previously is introduced into the ion implantation region 3f exposed from the gate electrode 5a of the semiconductor thin film 3 and the insulating wall 13a. Inject to be higher. In this further ion implantation, the gate electrode 5a and the insulating wall 13a function as a mask. As shown in FIG. 4B, the ion concentration in the region exposed from the insulating wall 13a of the semiconductor thin film 3 is the region covered with the insulating wall 13a. Higher than that. Therefore, by this further ion implantation, the ion implantation region 3f is divided into a high concentration region 3d exposed to the outside and a low concentration region 3e covered with the insulating wall 13a.
Thereafter, electrodes, wirings and the like are formed in the same manner as in Example 1 to complete the TFT having the LDD structure shown in FIG.
[0049]
The TFT of this example having an LDD structure is more reliable than that of Example 1 because the electric field directly under the gate electrode 5a is relaxed.
According to this embodiment, the gate electrode and the insulating wall formed prior to the formation of the low concentration region and the high concentration region are used as a mask, so that the resist pattern can be used in addition to protecting a part of the region. Need not be used. Therefore, the semiconductor element of this example has a significant variation in element characteristics due to variations in mask alignment accuracy and size in the formation of these regions, compared to the manufacture of semiconductor elements having a conventional LDD structure. Small. That is, according to this embodiment, a thin film semiconductor element having high reliability and stable characteristics can be manufactured stably.
[0050]
Example 3
In this embodiment, an example of an offset structure TFT having a semiconductor thin film arranged in the same manner as that of Embodiment 1 will be described.
[0051]
The TFT of this example is shown in FIG. The structure of this TFT is almost the same as that of the TFT of Example 1. However, in the TFT of this embodiment, the source region 3b and the drain region 3c of the semiconductor thin film 3 are arranged only under the source electrode wiring 8b and the drain electrode wiring 8c, respectively, and impurity ions are formed in the region under the insulating wall 13a. An offset region 3g in which no is implanted is arranged. That is, impurity ions are not implanted into the region covered with the gate electrode 5a and the insulating wall 13a.
[0052]
The TFT of this example is manufactured as follows, for example.
As shown in FIG. 9A, after the conductive film 5 and the like are formed on the substrate 1 in the same manner as in Example 1, these are processed by etching to form the gate electrode 5a. Thereafter, the insulating wall 13a is formed. That is, an insulating film 13 made of, for example, silicon oxide is formed so as to cover the entire surface of the substrate 1 on which the semiconductor thin film 3 is disposed, and the insulating film 13 is further processed by anisotropic etching (dry etching) to form a gate. An insulating wall 13a covering the side surface of the electrode 5a is formed in a self-aligning manner.
[0053]
Impurity ions are implanted into the semiconductor thin film 3 as shown in FIG. 9B by using the formed insulating wall 13a and the gate electrode 5a (or a resist layer as necessary) as a mask.
Thereafter, when the gate electrode 5a, the drain electrode wiring 8c wiring, and the like are formed in the same manner as in Example 1, a TFT having the offset region 3g under the insulating wall 13a is obtained.
[0054]
According to the present embodiment, the offset region can be formed in a self-aligned manner as in the case of forming the low concentration region in the second embodiment. Therefore, it is possible to manufacture a TFT having stable characteristics as compared with a conventional offset TFT in which an offset region is formed using a resist pattern.
[0055]
Example 4
In this embodiment, an example of a complementary metal-oxide semiconductor (CMOS) transistor in which a P-channel transistor and an N-channel transistor are arranged in parallel will be described.
A CMOS transistor can be manufactured by implanting and manufacturing N-type impurities and P-type impurities in predetermined regions of the semiconductor thin film, respectively, by the same method as in the first embodiment.
A CMOS transistor of this embodiment is shown in FIG.
The P-channel transistor 7a and the N-channel transistor 7b are the same except for the impurities implanted in the semiconductor thin film 3. Both of these have substantially the same structure as the TFT of Example 1.
[0056]
Below, an example of the manufacturing method of the CMOS transistor of a present Example is shown.
Similarly to Example 1, for example, as shown in FIG. 11A, an undercoat layer 2, a semiconductor thin film 3, an insulating film 4, a conductive film 5, and an insulating film 6 are formed on an insulating substrate 1, and a resist layer 17 is further formed. The conductive film 5 is processed into the gate electrode 5a by etching using a mask.
[0057]
After forming the gate electrode 5a, an N-type impurity and a P-type impurity are implanted into the semiconductor thin film 3, respectively. For example, as shown in FIG. 11B, a region corresponding to the side portion of the channel region 3a of the N-channel transistor that covers the region where the P-channel transistor is to be formed and is formed as necessary is formed. A resist layer 18 is formed on the substrate 1 so as to cover the substrate, and N-type impurity regions 3n are formed by implanting N-type impurity ions into the semiconductor thin film 3 using the resist layer 18 as a mask. Further, a P-type impurity region 3p is formed in the same manner. That is, a resist is formed on the substrate 1 so as to cover a region where an N-channel transistor is to be formed and also cover a region corresponding to the side portion of the channel region 3c of the P-channel transistor to be formed as necessary. A layer 19 is formed, and using this resist layer 19 as a mask, P-type impurity ions such as boron are implanted into the semiconductor thin film 3 as shown in FIG.
[0058]
After the P-type impurity region 3p and the N-type impurity region 3n are formed in the semiconductor thin film 3, the insulating wall 13a surrounding the gate electrode 5a is formed as shown in FIG. That is, an insulating film made of, for example, silicon oxide is formed so as to cover the entire surface of the substrate 1, and anisotropic etching is performed on the insulating film.
After the formation of the insulating wall 13a, wiring such as the drain electrode wiring 8b and the source electrode wiring 8c is formed as shown in FIG. After forming a conductive film made of, for example, titanium so as to cover the surface of the substrate 1 where they are arranged, unnecessary etching is performed by using a resist layer to form the gate electrode 5a, the insulating wall 13a, and the wiring. The conductive film in the region is removed, and wirings such as a drain electrode wiring 8b and a source electrode wiring 8c are formed. Moreover, the semiconductor thin film 3 is divided into pieces by this etching.
[0059]
Further, after forming the insulating film 9 so as to cover the surface of the substrate 1, for example, the substrate 1 is heat-treated to activate the source region 3b and the drain region 3c of the semiconductor thin film 3, and the source region 3b and the source electrode 5b The contact resistance between the drain region 3c and the drain electrode wiring 8c is reduced.
Next, a contact window 9a is formed in the insulating film 9, and a signal wiring 10 connected to each electrode such as a scanning signal line and an image signal line and other signal wirings are formed, whereby the CMOS transistor shown in FIG. Is obtained.
[0060]
As the N-channel transistor and the P-channel transistor, those having an LDD structure as in the second embodiment and those having an offset structure as in the third embodiment may be used.
[0061]
<< Example 5-1 >>
The thin film semiconductor device of this example is shown in FIGS.
A semiconductor thin film 3 made of polycrystalline silicon is formed on the surface of the insulating substrate 1.
The semiconductor thin film 3 includes a channel region (active region) 3a that does not contain impurities, and a source region 3b and a drain region 3c into which phosphorus is implanted as an N-type impurity.
The undercoat layer 2 sandwiched between the substrate 1 and the semiconductor thin film 3 is for suppressing the diffusion of impurities from the glass substrate 1 to the semiconductor thin film 3 and the generation of lattice defects on the surface of the channel region 3a.
[0062]
A gate electrode 5a is formed on the upper surface of the semiconductor thin film 3 with a gate insulating film 4a therebetween so as to cover almost the entire surface of the channel region 3a. The upper surface of the gate electrode 5a is covered with an insulating film 6, and the side wall surface thereof is covered with an insulating wall 13a made of silicon oxide. The width of the insulating wall 13a is substantially equal to that of the semiconductor thin film 3 or the gate insulating film 4a disposed below the insulating wall 13a.
The source region 3b and the drain region 3c provided at the pair of end portions of the semiconductor thin film 3 are connected to the source electrode wiring 8b and the drain electrode wiring 8c at the inclined end surfaces, respectively. An insulating film 9 is formed so as to cover them. Both the source electrode wiring 8b and the drain electrode wiring 8c are electrically insulated from the gate electrode 5a by the insulating film 6 and the insulating wall 13a. The signal wiring 10 is electrically connected to the gate electrode 5a in a contact window 9a provided above the gate electrode 5a of the insulating film 9.
The length of the channel region 3a of the semiconductor thin film 3 is substantially equal to that of the gate electrode 5a.
[0063]
The TFT of this example is manufactured as follows, for example.
As shown in FIG. 15A, an undercoat layer 2 made of silicon oxide is formed on an insulating substrate 1 made of glass, for example, and a semiconductor thin film 3 made of polycrystalline silicon is further formed thereon. Thereafter, an insulating film 4 made of silicon oxide and a conductive film 5 made of molybdenum / tungsten alloy are formed so as to cover the semiconductor thin film 3. Next, a resist layer 11 is formed so as to cover a region where the channel region (active region) 3a of the TFT is to be disposed. The insulating film 4 and the conductive film 5 are etched using the resist layer 11 as a mask. By this etching, the conductive film 5 is processed into the gate electrode 5a of the TFT to be obtained, and the insulating film 6 covering the conductive film 5 is also processed into a similar shape.
[0064]
After removing the resist layer 11, impurity ions are implanted into a predetermined region of the semiconductor thin film 3. Ions are not implanted into the semiconductor thin film 3 in the region whose surface is covered with the gate electrode 5a because the gate electrode 5a functions as a mask. The region into which ions are implanted (ion implantation region 3f) is processed into a source region 3b and a drain region 3c arranged with the channel region 3a interposed therebetween. Therefore, prior to ion implantation, in order to prevent a short circuit between the source and drain of the obtained TFT, preferably, a pair of parallel edges of the rectangular gate electrode 5a is formed as shown in FIG. A resist layer 12 is formed so as to cover it. Using resist layer 12 and gate electrode 5a as a mask, for example, phosphorus, which is an N-type impurity, is added to semiconductor thin film 3 by phosphine (PH_Three) Implanted by a plasma doping method using a gas.
[0065]
After removing the resist layer 12, as shown in FIG. 15C, an insulating film 13 made of, for example, silicon oxide is formed so as to cover the entire surface of the substrate 1 on the side where the semiconductor thin film 3 is disposed. While the thickness of the flat region of the insulating film 13 to be formed is uniform, the thickness of the portion corresponding to the edge of the gate electrode 5a is thicker than that as shown in FIG. . Therefore, when anisotropic etching (dry etching) is performed in the normal direction of the substrate 1, only the periphery of the gate electrode 5a remains in the insulating film 13, and an insulating wall 13a covering the side surface of the gate electrode 5a is formed. . By this etching, as shown in FIG. 16A, the insulating film 4 in the region where the gate electrode 5a is not disposed is removed to form the gate insulating film 4a, and the semiconductor thin film 3 disposed below the gate insulating film 4a. Is removed. That is, the semiconductor thin film 3 is processed in a shape that substantially matches the outer shape of the insulating wall 13a disposed around the gate electrode 5a in a self-aligning manner. As a result, the semiconductor thin film 3 is divided into pieces each including a source region 3b and a drain region 3c into which ions are implanted, and a channel region 3a sandwiched between them. Here, as shown in FIG. 16A, the end of the processed semiconductor thin film 3 on the bottom side protrudes from the insulating wall 13a. That is, the semiconductor thin film 3 is processed so that the cross section thereof has a substantially trapezoidal shape.
[0066]
After the processing of the semiconductor thin film 3, wirings such as the source electrode wiring 8b and the drain electrode wiring 8c are formed. As shown in FIG. 16B, a conductive film 8 made of, for example, titanium is formed so as to cover the surface of the substrate 1 on which the substrate 1 is disposed. After the resist layer 14 is formed so as to cover the region to be processed in the wiring of the formed conductive film 8, the unnecessary region of the conductive film 8 is removed by etching. As a result, for example, as shown in FIG. 16C, a signal wiring 8a such as a scanning signal line, a source electrode wiring 8b, a drain electrode wiring 8c, and the like are formed. By this etching, the exposed protruding end of the semiconductor thin film 3 is removed. The protruding end portions of the source region 3b and the drain region 3c of the semiconductor thin film 3 are connected to the formed source electrode wiring 8b and drain electrode wiring 8c, respectively. Since the semiconductor thin film 3 has inclined side surfaces, a sufficient contact area is ensured between the source region 3b and the source electrode wiring 8b and between the drain region 3c and the drain electrode wiring 8c, and stable between the two. An electrical connection is obtained.
[0067]
After the resist layer 14 is removed, an insulating film 9 made of silicon oxide is formed on the entire surface so as to cover the surface of the substrate 1 as shown in FIG.
After the insulating film 9 is formed, for example, the substrate 1 is heat-treated at 400 to 600 ° C., thereby activating the source region 3b and the drain region 3c of the semiconductor thin film 3 into which phosphorus has been implanted, and the source region 3b and the source The contact resistance between the electrode wiring 8b and between the drain region 3c and the drain electrode wiring 8c is reduced.
[0068]
Next, other signal wirings such as scanning signal lines and image signal lines are formed.
As shown in FIG. 17A, a resist layer 16 having a pattern in which a region to be connected to the wiring to be formed and each electrode is opened is formed. By etching using the resist layer 16 as a mask, the insulating film 9 in the exposed region is removed to form a contact window 9a.
Next, a conductive film made of, for example, aluminum is formed on the entire surface of the substrate 1, and the conductive film is further processed into a predetermined pattern to form the signal wiring 10.
As described above, the TFT shown in FIGS. 13 and 14 is obtained.
[0069]
Also in this embodiment, the semiconductor thin film is formed in a self-aligned manner. That is, the region processed into the channel region (or the region processed into the source / drain regions) is defined by the shape of the gate electrode. The shape of the semiconductor thin film is defined by the shape of the insulating wall around the gate electrode. The insulating wall is also formed in a self-aligning manner. According to the present invention, since the components of these TFTs are formed in a self-aligned manner, a semiconductor element with stable characteristics can be manufactured.
According to the present invention, since the distance between the gate electrode and the source / drain electrode is defined by the thin insulating wall, the distance between them can be reduced as compared with the conventional device. Further, since the resistance component in the source / drain region when the element is ON can be minimized, the resistance between the source and the drain is small and the ON current is large as compared with the conventional element. In addition, since a sufficient contact area can be ensured between the source / drain regions of the semiconductor thin film and the electrode member, the contact resistance between the two is lower than that of the conventional element.
[0070]
Furthermore, the area occupied by the element can be made smaller than that of the conventional element. Therefore, it becomes possible to arrange with higher density. Further, the use of the TFT of this embodiment as a switching element for controlling each pixel of a display panel such as a liquid crystal display panel or an organic EL display panel improves the aperture ratio of the pixels of the display panel and enhances the display. Contribute to etc.
According to the present invention, the process of manufacturing the device is further greatly simplified. For example, unlike the conventional device, it is not necessary to form a contact window in the insulating film disposed between the source / drain regions of the semiconductor thin film and the electrode member in order to electrically connect them.
[0071]
<< Example 5-2 >>
In this example, a method by which a thin film semiconductor element similar to that of Example 5-1 can be more efficiently manufactured will be described.
In this embodiment, ions are implanted into the semiconductor thin film 3 through an insulating film formed on the upper surface of the semiconductor thin film 3. That is, as shown in FIG. 18A, when the conductive film 5 formed on the insulating substrate 1 is processed into the gate electrode 5a by etching in the same manner as in Example 5-1, the exposed region is insulated. Together with the film 6 and the conductive film 5 disposed thereunder, the insulating film 4 disposed under the conductive film 5 in that region is simultaneously removed. By this etching, the semiconductor thin film 3 in the region not covered with the resist layer 11 is exposed as shown in FIG. Thereafter, ions are directly implanted into the semiconductor thin film 3 without going through the insulating film 4.
[0072]
By implanting ions without going through the insulating film 4, high-concentration ion implantation and high efficiency of ion implantation can be achieved. Further, in Example 5-1, variation in the thickness of the insulating film 4 formed on the upper surface of the semiconductor thin film 3 causes variation in the concentration of ions implanted into the semiconductor thin film 3, whereas in this example. By directly implanting ions into the semiconductor thin film 3, it is possible to stably manufacture a semiconductor element with small variations in characteristics.
[0073]
Example 6
In this embodiment, an example of a TFT in which the source and drain regions of a semiconductor thin film are connected to electrode wirings at their end faces as in the above embodiment and further has an LDD (lightly-doped drain) structure will be described.
A TFT of this example is shown in FIG. The structure of this TFT is almost the same as that of Example 5-1. However, in the TFT of this embodiment, each of the source region 3b and the drain region 3c of the semiconductor thin film 3 is composed of a high concentration region 3d and a low concentration region 3e having different impurity ion concentrations. The high concentration region 3d is disposed only in a region exposed from the insulating wall 13a of the semiconductor thin film 3, and the low concentration region 3e is disposed only under the insulating wall 13a between the channel region 3a and the high concentration region 3d. Yes. The semiconductor thin film 3 is connected to the source electrode wiring 8b and the drain electrode wiring 8 only in the high concentration region 3d.
[0074]
This TFT is manufactured, for example, as follows.
As in Example 5-1, after forming the gate electrode 5a on the substrate 1 and further implanting ions into the semiconductor thin film 3, an insulating wall 13a is formed as shown in FIG.
Next, using the resist layer 11 similar to that used previously for ion implantation, ions of the same type as those used previously are implanted into the region exposed from the insulating wall 13a of the semiconductor thin film 3 by, for example, plasma doping. Ions have already been implanted into the region of the semiconductor thin film 3 exposed from the insulating wall 13a and the region below the insulating wall 13a connected thereto. In this further ion implantation, the insulating wall 13a functions as a mask. As shown in FIG. 20B, ions are newly implanted only into the region exposed from the insulating wall of the semiconductor thin film, and the source region 3b and the drain region 3c. In addition, the high concentration region 3d and the low concentration region 3e are formed.
Thereafter, electrodes, wirings and the like are formed in the same manner as in Example 1, and a semiconductor element having an LDD structure as shown in FIG. 19 is obtained.
[0075]
The MIS transistor of this example having an LDD structure is more reliable than the example 5-1 because the electric field directly under the gate electrode 5 is relaxed.
According to this embodiment, the gate electrode and the insulating wall formed prior to the formation of the low concentration region and the high concentration region are used as a mask, so that the resist pattern can be used in addition to protecting a part of the region. Need not be used. Therefore, the thin film semiconductor device of this example has a variation in device characteristics caused by variations in mask alignment accuracy and size in the formation of these regions, compared with the manufacture of a thin film semiconductor device having a conventional LDD structure. Is much smaller. That is, according to the present embodiment, a semiconductor element having high reliability and stable characteristics can be stably manufactured.
Of course, a gate insulating film may be formed prior to the previous ion implantation as in the embodiment 5-2.
[0076]
Example 7
In this embodiment, another example of a TFT having an LDD structure will be described.
In the present embodiment, the source region and the drain region of the semiconductor elements of Examples 5-1 and 5-2 are set as the low concentration region, and the source electrode wiring and the drain electrode wiring are set as the high concentration region, thereby forming the LDD. Form a structure.
The TFT of this example is shown in FIG. In this TFT, the ion implantation regions 3h into which impurity ions are implanted at both ends of the semiconductor thin film 3 function as low concentration regions in the LDD structure, respectively, and the signal wirings 20b and 20c connected thereto are respectively high concentration regions in the LDD structure. Function as.
[0077]
The TFT of this example is manufactured as follows, for example.
As in Example 5-1, after forming the gate electrode 5a on the substrate 1 and further implanting ions into the semiconductor thin film 3 to form the ion implantation region 3f, an insulating wall is formed as shown in FIG. 13a is formed, and the semiconductor thin film 3 is further divided into pieces.
Thereafter, as shown in FIG. 22B, a semiconductor thin film 23 made of, for example, titanium silicide (TiSi) is formed so as to cover the surface of the substrate 1. Next, using the resist layer 24 formed so as to protect both side walls of the channel region of the semiconductor thin film 3 as a mask, ions of the same type as those used for ion implantation into the semiconductor thin film 3 are applied to the semiconductor thin film 23. For example, implantation is performed by a plasma doping method. Here, the concentration of ions implanted into the semiconductor thin film 23 is set higher than those in the ion implantation region 3 f of the semiconductor thin film 3.
[0078]
The semiconductor thin film 23 into which ions are implanted is processed into signal wirings 20b and 20c and other wirings. Since the signal wirings 20b and 20c are respectively connected to the ion implantation region 3f of the semiconductor thin film 3 having a lower ion concentration, an LDD structure having a high concentration region and a low concentration region is obtained. After the processing of the semiconductor thin film 23, an insulating film is formed in the same manner as in the above embodiment, and further, ions implanted into the wirings 20b and 20c formed in contact with the semiconductor thin film 3 by heat treatment at 400 to 600 ° C. 3 is diffused to the end.
Thereafter, a contact window is formed, and signal wiring is formed in a predetermined pattern, whereby a TFT having an LDD structure is obtained.
[0079]
Example 8
In this embodiment, an example of a TFT having a source / drain region of a semiconductor thin film connected to an electrode wiring at each end face thereof and having an offset structure as in the embodiment 5-1 will be described.
A TFT of this example is shown in FIG. The structure of this TFT is almost the same as that of the TFT of Example 5-1. However, in the TFT of this embodiment, the source region 3b and the drain region 3c of the semiconductor thin film 3 are arranged only at a pair of ends exposed from the insulating walls 13a of the semiconductor thin film, and in the region below the insulating wall 13a, An offset region 3g where impurity ions are not implanted is arranged. That is, impurity ions are not implanted into the region covered with the gate electrode 5a and the insulating wall 13a.
[0080]
The TFT of this example is manufactured as follows, for example.
In the same manner as in Example 5-1, the gate electrode 5a is formed on the substrate 1, and the insulating wall 13a is formed. In the anisotropic etching for forming the insulating wall 13a, the semiconductor thin film 3 is divided into individual pieces. At this time, the end of the divided semiconductor thin film 3 is exposed from the insulating wall 13a as shown in FIG. Impurity ions are implanted into the semiconductor thin film 3 using the insulating wall 13a and the gate electrode 5a (and the resist layer 11 as necessary) as a mask. That is, ions are implanted into the end protruding from the insulating wall.
Thereafter, when gate electrode wiring, drain electrode wiring, and the like are formed in the same manner as in Example 5-1, a TFT having the offset region 3g under the insulating wall 13a is obtained.
[0081]
According to this embodiment, the offset region can be formed in a self-aligning manner. Therefore, it is possible to manufacture a TFT having stable characteristics as compared with a conventional offset TFT in which an offset region is formed using a resist pattern.
[0082]
Example 9
An example of a CMOS transistor using a TFT in which the source and drain regions of the semiconductor thin film of the above embodiment are connected to electrode wirings at the end faces thereof will be described.
[0083]
A CMOS transistor of this example is shown in FIG.
The P-channel transistor 7a and the N-channel transistor 7b are the same except for the impurities implanted in the semiconductor thin film 3. Both of these have substantially the same structure as the TFT of Example 1.
[0084]
Below, an example of the manufacturing method of the CMOS transistor of a present Example is shown.
Similarly to Example 5-1, for example, as shown in FIG. 26A, an undercoat layer 2, a semiconductor thin film 3, an insulating film 4, a conductive film 5, and an insulating film 6 are formed on an insulating substrate 1, and a resist is further formed. The conductive film 5 is processed into the gate electrode 5a by etching using the layer 17 as a mask.
After forming the gate electrode 5a, an N-type impurity and a P-type impurity are implanted into the semiconductor thin film 3, respectively. For example, as shown in FIG. 26 (b), a region corresponding to the side portion of the channel region 3a of the N-channel transistor that covers the region where the P-channel transistor is to be formed and is formed as necessary is formed. A resist layer 18 is formed on the substrate 1 so as to cover the substrate, and N-type impurity regions 3n are formed by implanting N-type impurity ions into the semiconductor thin film 3 using the resist layer 18 as a mask. Further, a P-type impurity region 3p is formed in the same manner. That is, as shown in FIG. 27 (a), a region corresponding to the side portion of the channel region 3c of the P-channel transistor that covers the region where the N-channel transistor is to be formed and that is to be formed as necessary is also included. A resist layer 19 is formed on the substrate 1 so as to cover it, and P-type impurity ions such as boron are implanted into the semiconductor thin film 3 using the resist layer 19 as a mask.
[0085]
After the P-type impurity region 3p and the N-type impurity region 3n are formed in the semiconductor thin film 3, the insulating wall 13a surrounding the gate electrode 5a is formed as shown in FIG. That is, an insulating film made of, for example, silicon oxide is formed so as to cover the entire surface of the substrate 1, and anisotropic etching is performed on the insulating film.
After the formation of the insulating wall 13a, wiring such as the drain electrode wiring 8b and the source electrode wiring 8c is formed as shown in FIG. Etching using a resist layer formed to form the gate electrode 5a, the insulating wall 13a, and the wiring after forming a conductive film made of titanium, for example, so as to cover the surface of the substrate 1 on the side where they are arranged Thus, the conductive film in unnecessary regions is removed, and wirings such as the drain electrode wiring 8b and the source electrode wiring 8c are formed. Moreover, the semiconductor thin film 3 is divided into pieces by this etching.
[0086]
Further, after forming the insulating film 9 so as to cover the surface of the substrate 1, for example, the substrate 1 is heat-treated to activate the source region 3b and the drain region 3c of the semiconductor thin film 3, and the source region 3b and the source electrode 5b The contact resistance between the drain region 3c and the drain electrode wiring 8c is reduced.
Next, a contact window 9a is formed in the insulating film 9, and a signal wiring 10a connected to each electrode such as a scanning signal line and an image signal line and other signal wirings are formed, whereby the CMOS transistor shown in FIG. Is obtained.
[0087]
【The invention's effect】
According to the present invention, it is possible to provide a thin film semiconductor element having a large ON current and a small area suitable for power saving and miniaturization of equipment at a low price. By using this thin film semiconductor element for a display panel such as a liquid crystal display panel, the display quality is greatly improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor element according to an embodiment of the present invention.
FIG. 2 is a schematic longitudinal sectional view showing the semiconductor element.
FIGS. 3A to 3C are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
4 (a), (b) and (c) are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
FIG. 5 is a schematic longitudinal sectional view showing a state of one stage in the manufacturing process of the element.
FIG. 6 is a schematic longitudinal sectional view showing a semiconductor device according to another embodiment of the present invention.
FIGS. 7A and 7B are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element. FIGS.
FIG. 8 is a schematic longitudinal sectional view showing a semiconductor device according to still another embodiment of the present invention.
FIGS. 9A and 9B are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element. FIGS.
FIG. 10 is a schematic longitudinal sectional view showing a semiconductor device according to still another embodiment of the present invention.
FIGS. 11A and 11B are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element. FIGS.
FIGS. 12A, 12B, and 12C are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element. FIGS.
FIG. 13 is a plan view showing a semiconductor device according to still another embodiment of the present invention.
FIG. 14 is a schematic longitudinal sectional view of the semiconductor element.
FIGS. 15A, 15B, and 15C are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element. FIGS.
16 (a), (b) and (c) are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
FIGS. 17A and 17B are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
18 (a) and 18 (b) are schematic longitudinal sectional views showing states of respective stages of a semiconductor device manufacturing process according to still another embodiment of the present invention.
FIG. 19 is a schematic longitudinal sectional view showing a semiconductor device according to still another embodiment of the present invention.
20 (a) and 20 (b) are schematic longitudinal cross-sectional views showing the state of each stage of the manufacturing process of the element.
FIG. 21 is a schematic longitudinal sectional view showing a semiconductor device of still another embodiment of the present invention.
22 (a) and 22 (b) are schematic longitudinal sectional views showing the state of each stage of the manufacturing process of the element.
FIG. 23 is a schematic longitudinal sectional view showing a semiconductor device of still another embodiment of the present invention.
FIG. 24 is a schematic longitudinal sectional view showing a stage in the manufacturing process of the element.
FIG. 25 is a schematic longitudinal sectional view showing a semiconductor device of still another embodiment of the present invention.
26 (a) and 26 (b) are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
FIGS. 27A, 27B, and 27C are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element. FIGS.
FIG. 28A is a plan view showing a conventional TFT, and FIG. 28B is a schematic longitudinal sectional view of the element.
29 (a) and 29 (b) are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
30 (a), (b) and (c) are schematic longitudinal sectional views showing states of respective stages of the manufacturing process of the element.
FIG. 31A is a schematic longitudinal sectional view showing a main part of an active matrix type liquid crystal display panel using TFTs as switching elements, and FIG. 31B is a main part of an array substrate used in the panel; It is a top view which shows a part.
FIG. 32 is a schematic longitudinal sectional view showing a main part of an organic EL display panel using TFTs as switching elements.
[Explanation of symbols]
1 Insulating substrate
2 Undercoat layer
3, 23 Semiconductor thin film
3a channel region
3b Source region
3c drain region
3d high concentration region
3e Low concentration region
3f ion implantation region
3g offset area
3n N-type impurity region
3p P-type impurity region
4, 6, 9, 13, 15 Insulating film
4a Gate insulation film
5, 8, 16 conductive film
5a Gate electrode
6a Contact window
7 Thin film transistor (TFT)
7a P-channel transistor
7b N-channel transistor
8a Signal wiring
8b Source electrode wiring
8c Drain electrode wiring
9a Contact window
10, 20a, 20b, 20c Signal wiring
11, 12, 14, 16, 17, 18, 19, 20, 21, 110, 111, 114 resist layer
13a insulation wall
200 Array substrate
201 Transparent pixel electrode
202 Scanning signal line
203, image signal line
204 Liquid crystal layer
205 Transparent counter electrode
206 Backlight
207a, 207b Polarizing plate
208 Counter substrate
209 Hardening film
210 Color filter layer
300 glass substrate
301 Organic EL material layer
302, 303 electrodes

Claims (18)

A semiconductor thin film including a channel region not including impurity ions and a source region and a drain region implanted with impurity ions formed on both sides of the channel region ;
A gate electrode disposed opposite to the channel region with a gate insulating film interposed therebetween ;
A frame-like insulating wall covering the peripheral edge of the gate electrode;
A source wiring connected to the source region;
A drain wiring connected to the drain region ,
In the projection onto the overlapping direction, said gate electrode, said insulating wall, although Kasaneawashi the source wiring and the drain wiring, substantially plane and the side wall surface defining the periphery of the semiconductor thin film, a side wall surface defining the periphery Thin film semiconductor device that has been integrated . Distance between the drain region and the source region, the direction of the magnitude and equal claim 1 thin film semiconductor device according of the gate electrode. The source region or the drain region, a thin film semiconductor device according to claim 2, further comprising a low concentration region of the impurity ions than other areas opposed to the insulating wall region. Distance between the drain region and the source region, said in the same direction of the insulating wall size equal to Claim 1 thin film semiconductor device according. Each pixel includes a dimming unit or a light emitting unit, and a switching element for controlling the operation of the dimming unit or the light emitting unit.
A semiconductor thin film including a channel region not including impurity ions and a source region and a drain region implanted with impurity ions formed on both sides of the channel region ;
A gate electrode disposed opposite to the channel region with a gate insulating film interposed therebetween ;
A frame-like insulating wall covering the peripheral edge of the gate electrode;
A source wiring connected to the source region;
A drain wiring connected to the drain region ,
In the projection onto the overlapping direction, said gate electrode, said insulating wall, although Kasaneawashi the source wiring and the drain wiring, substantially plane and the side wall surface defining the periphery of the semiconductor thin film, a side wall surface defining the periphery A display panel comprising a thin film semiconductor element. The display panel according to claim 5 , further comprising a liquid crystal layer, wherein the switching element controls ON / OFF of a voltage signal to the electrode pair as the dimming unit. The display panel according to claim 5 , further comprising a light emitting layer that emits light when voltage is applied, wherein the switching element controls ON / OFF of a voltage signal to the light emission. A method of manufacturing a thin film semiconductor device comprising a semiconductor thin film having a source region and a drain region implanted with impurity ions, a gate electrode, and a source wiring and a drain wiring connected to the source region and the drain region, respectively. And
Forming a semiconductor thin film on the surface of the insulating substrate;
Forming a first insulating film covering the semiconductor thin film on a surface of the insulating substrate;
Forming a first conductive film covering the first insulating film on a surface of the insulating substrate;
Forming a second insulating film covering the conductive film on a surface of the insulating substrate;
Processing the first conductive film into a gate electrode by etching using a first mask having a predetermined pattern;
Implanting impurity ions into the semiconductor thin film using the gate electrode as a mask;
Forming a frame-like insulating wall covering the side wall of the gate electrode;
Forming a second conductive film covering a surface of the insulating substrate on which the semiconductor thin film is formed;
The semiconductor thin film is processed into a predetermined shape having a channel region, a source region and a drain region by etching using a second mask having a predetermined pattern, the gate electrode and an insulating wall as a mask, and the second conductive film is formed Processing to form a wiring member connected to the source region and the drain region;
Forming a third insulating film covering a surface of the insulating substrate on the side where the semiconductor thin film is disposed;
Forming an opening in the third insulating film to expose the gate electrode;
Method of manufacturing a thin film semiconductor device including a step of forming another wiring member connected to the gate electrode in a region including the opening. After the step of forming the insulating wall and before the step of forming the second conductive film, the gate electrode and the insulating wall are used as a mask and the semiconductor thin film is used for previous ion implantation. 9. The method of manufacturing a thin film semiconductor device according to claim 8 , further comprising a step of implanting impurity ions of the same type to form a sub-region having a higher concentration of the impurity ions in the semiconductor thin film. 9. The thin film semiconductor according to claim 8 , wherein in the step of implanting impurity ions into the semiconductor thin film, P-type ions and N-type ions are implanted as different ions into different regions of the semiconductor thin film using masks having different patterns. Device manufacturing method. Said insulating wall, wherein an insulating film is formed to cover the gate electrode, claim the formed the insulating film is formed by the remaining only the peripheral portion of the gate electrode are removed by anisotropic etching 8 The manufacturing method of the thin film semiconductor element of description. The method for manufacturing a thin film semiconductor element according to claim 8 , wherein the second conductive film is made of a metal having a melting point of 1,000 ° C. or higher. 9. The method of manufacturing a thin film semiconductor device according to claim 8 , further comprising a step of performing a heat treatment for activation on the semiconductor thin film after the step of forming the third insulating film. A method of manufacturing a thin film semiconductor device comprising a semiconductor thin film having a source region and a drain region implanted with impurity ions, a gate electrode, and a source wiring and a drain wiring connected to the source region and the drain region, respectively. And
Forming a semiconductor thin film on the surface of the insulating substrate;
Forming a first insulating film covering the semiconductor thin film on a surface of the insulating substrate;
Forming a conductive film covering the first insulating film on a surface of the insulating substrate;
Forming a second insulating film covering the conductive film on a surface of the insulating substrate;
Processing the conductive film into a gate electrode by etching using a first mask having a predetermined pattern;
Forming a frame-like insulating wall covering the side wall of the gate electrode;
Implanting impurity ions into the semiconductor thin film using the gate electrode and the insulating wall as a mask;
Forming a second conductive film covering a surface of the insulating substrate on which the semiconductor thin film is formed;
The semiconductor thin film is processed into a predetermined shape having a channel region, a source region and a drain region by etching using a second mask having a predetermined pattern, the gate electrode and an insulating wall as a mask, and the second conductive film is formed Processing to form a wiring member connected to the source region and the drain region;
Forming a third insulating film covering a surface of the insulating substrate on the side where the semiconductor thin film is disposed;
Forming an opening in the third insulating film to expose the gate electrode;
Method of manufacturing a thin film semiconductor device including a step of forming another wiring member connected to the gate electrode in a region including the opening. 15. The thin film semiconductor device according to claim 14 , wherein in the step of implanting impurity ions into the semiconductor thin film, the P-type and N-type impurity ions are implanted into different regions by further using another mask having a predetermined shape. Manufacturing method. Said insulating wall, wherein an insulating film is formed to cover the gate electrode, claim the formed the insulating film is formed by the remaining only the peripheral portion of the gate electrode are removed by anisotropic etching 14 The manufacturing method of the thin film semiconductor element of description. The method of manufacturing a thin film semiconductor element according to claim 14 , wherein the second conductive film is made of a metal having a melting point of 1,000 ° C. or higher. 15. The method of manufacturing a thin film semiconductor element according to claim 14 , further comprising a step of performing a heat treatment for activation on the semiconductor thin film after the step of forming the third insulating film.

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