JP2003075870A - Plane display device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plane display device which is increased in yield by suppressing voltage dependency. SOLUTION: The power consumption can be reduced by lowering a driving voltage by injecting impurities selectively to a lower electrode 38 of a semiconductor of an auxiliary capacitor 24 so as to have the same density as that of the source area 32 and drain area 33 of a thin film transistor 23. After a resist mask for the injection of impurities into the lower electrode 38 is peeled by plasma ashing, dilute hydrofluoric acid processing for removing a damage layer formed in the surface of a 1st insulating film 41 is carried out and then a gate insulating film part 43 in the 1st insulating film 41 has no damage, so the thin film transistor 23 has no characteristic deterioration. On the 1st insulating film 41, a 2nd insulating film 42 is laminated and formed and even if a pinhole is formed in the 1st insulating film 41 during dilute hydrofluoric acid processing, a short circuit can be prevented between a gate electrode 34 of the gate insulating film part 43 and a channel area 35 of a semiconductor layer 31 or in a dielectric part 45.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device having a thin film transistor and a thin film capacitor, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a flat display device of this type,
For example, a liquid crystal display device in which pixels are arranged in a matrix is known. Further, among the liquid crystal display devices, there is an active matrix type in which thin film transistors are provided corresponding to pixels arranged in a matrix. And
This active matrix type liquid crystal display device is a device for displaying an image by writing an arbitrary potential to each pixel by switching operation of a thin film transistor provided corresponding to the pixel and controlling the light transmittance of each pixel. It has excellent characteristics. In recent years, not only a thin film transistor for writing a potential to a pixel but also a driving circuit for driving these thin film transistors are formed on the same substrate.

A liquid crystal display device provided with this drive circuit is required to have low power consumption. On the other hand, a thin film capacitor for storing data is provided for each pixel, and it is effective to reduce the operating voltage of this thin film capacitor to reduce power consumption. MOS (Metal Oxide Semiconducto) that uses polysilicon not doped with impurities
Since it is of the r type, it is necessary to apply a high voltage to form the capacitance, and the operating voltage cannot be lowered.

Further, in order to reduce the voltage of such a MOS type thin film capacitor, it is known to inject a high concentration impurity into the polysilicon forming one electrode so that the characteristic thereof is that of a metal. ing. Then, in order to create a capacitor having a structure in which a high concentration of impurities is injected into polysilicon forming one electrode of this thin film capacitor, an ion doping apparatus is used by using a resist mask having an opening into which impurity ions are injected. Impurities are selectively implanted into only one electrode of the thin film capacitor and the source region and drain region of the thin film transistor, which are generally provided in the same polysilicon layer as the one electrode of the thin film capacitor. In this case, since the resist mask is formed over the semiconductor layer of the thin film transistor or over the gate insulating film formed over the semiconductor layer, between the semiconductor layer and the gate insulating film or between the gate insulating film and the gate electrode, The resist mask is applied and stripped.

[0005]

However, since there is a region that influences the characteristics of the thin film transistor between the semiconductor layer and the gate insulating film or between the gate insulating film and the gate electrode, damage due to the process is not necessary. Must be kept to a minimum. On the other hand, the resist mask used as a mask for ion doping has a hardened surface due to damage by the implanted ions, and cannot be stripped unless a dry ashing device using plasma accelerated with high energy is used. When the resist mask is stripped by this dry ashing, it is unavoidable that the surface from which the resist mask is stripped is seriously damaged, and the characteristics of the thin film transistor may deteriorate.

Further, since damage at the time of dry ashing occurs only on the surface, considering only the characteristics of the thin film transistor, the characteristics can be obtained by removing only the damaged film surface with a dilute hydrofluoric acid after removing the resist mask. Recover.

However, when cleaning with dilute hydrofluoric acid, pin particles are generated when particles are present on the gate oxide film or when there is a weak portion, and the gate electrode and the semiconductor layer formed on the gate electrode are formed. There is a problem that a short circuit may occur between them and the yield may be reduced.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a flat panel display device with suppressed voltage dependence and improved yield, and a manufacturing method thereof.

[0009]

The present invention provides a substrate, a plurality of thin film transistors formed on the substrate, a plurality of display elements connected to the thin film transistors and arranged in a matrix, and the display element. An auxiliary capacitance semiconductor layer electrically connected, an insulating layer formed on the auxiliary capacitance semiconductor layer, and a metal electrode formed on the insulating layer, the auxiliary capacitance semiconductor layer, the In the flat panel display device having an insulating layer and the metal electrode to form a storage capacitor, the thin film transistor includes a semiconductor layer having a channel region and a source region and a drain region into which an impurity is injected with the channel region interposed therebetween. An impurity having a concentration substantially equal to that of the source region and the drain region of the thin film transistor is implanted into the auxiliary capacitance semiconductor layer, The insulating layer is formed by stacking a first insulating film in which impurities are injected in a predetermined concentration and a second insulating film in which an impurity is injected in an intrinsic state or a concentration lower than the predetermined concentration, and is a thin film. Since the impurity is injected into the semiconductor layer for the auxiliary capacitance forming the capacitor at a concentration substantially equal to that of the source region and the drain region of the thin film transistor, it is possible to reduce the driving voltage and power consumption, and it is possible to reduce the power consumption during the manufacturing process. Even if a pinhole or the like is formed in the insulating film of, since the second insulating film is formed on the first insulating film, the gate electrode of the thin film transistor and the channel region of the active layer are insulated by the second insulating film. The characteristic deterioration of the thin film transistor can be avoided, and the yield does not decrease.

Further, according to the present invention, a step of simultaneously forming a semiconductor layer of a thin film transistor and a semiconductor layer for an auxiliary capacitance on a substrate, and a first step of covering the semiconductor layer of the thin film transistor and the semiconductor layer for an auxiliary capacitance. And a resist mask having a shape that covers the source region, the drain region of the thin film transistor, and the entire surface of the semiconductor layer for the auxiliary capacitance, and the step of forming an insulating film A step of forming on the insulating film, a step of implanting an impurity into the source region of the thin film transistor, the drain region, and the entire surface of the auxiliary capacitance semiconductor layer through the resist mask,
A step of removing the resist mask, a step of cleaning the first insulating film, a step of forming a second insulating film on the first insulating film, and a step of forming a metal on the second insulating film. Forming a layer, and patterning the metal layer to form a gate electrode of the thin film transistor and a metal electrode facing the semiconductor layer for the auxiliary capacitance, the semiconductor layer for the auxiliary capacitance of the thin film capacitor. Since impurities can be injected into the thin film transistor similarly to the source region and the drain region of the thin film transistor, the driving voltage can be reduced to reduce power consumption, and a resist mask can be formed over the first insulating film, and the resist mask can be removed. Even if a pinhole or the like is formed in the first insulating film during the etching, the thin film transistor is formed because the second insulating film is formed on the first insulating film after removing the resist mask. Between the channel region of the gate electrode and the semiconductor layer of the data can avoid the property deterioration of the thin film transistor is insulated by the second insulating film, it does not cause a reduction in yield.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a liquid crystal display device 11 as a flat display device has a matrix array substrate 12 and a counter substrate.
13 are provided to face each other, and these matrix array substrates 12
A liquid crystal layer 14 is sandwiched between the counter substrate 13 and a light modulating layer.

First, the matrix array substrate 12 is composed of an insulating substrate 21 made of transparent glass or the like and silicon oxide (Si).
An undercoat layer 22 having a film thickness of O _x ) of 50 nm is formed. On the undercoat layer 22, a thin film transistor (Thin Film Transistor) 23 for a pixel, which is composed of, for example, an N-type thin film transistor as a switching element, and a MOS An auxiliary capacitance 24 as a (Metal Oxide Semiconductor) type thin film capacitor is formed.

In the thin film transistor 23, a semiconductor layer 31 of polycrystalline silicon having a film thickness of 50 nm is formed on the undercoat layer 22, and the semiconductor layer 31 has a source region 32 and a drain region 33 containing impurities of a predetermined concentration. Formed,
A channel region 35 that contains an impurity having a concentration lower than a predetermined concentration or is in an intrinsic state is formed at a position corresponding to the upper gate electrode 34 in a self-aligned manner, and the LDD is provided between the channel region 35 and the source region 32. (Lightly Doped
A drain region 36 is formed, and an LDD region 37 is formed between the channel region 35 and the drain region 33.

A storage capacitor is formed on the undercoat layer 22.
24 lower electrode as a semiconductor layer for auxiliary capacitance which becomes one electrode
38 is formed, and the lower electrode 38 has a high concentration, for example, the source region 32 and the drain region 33 of the thin film transistor 23.
Is formed of a semiconductor layer of polycrystalline silicon that entirely contains an impurity having a concentration approximately equal to that of the impurity contained in.

An insulating layer 40 is formed on the semiconductor layer 31 of the thin film transistor 23 and the lower electrode 38 of the auxiliary capacitor 24. The insulating layer 40 is a first layer of silicon oxide having a film thickness of 70 nm.
The insulating film 41 and the second insulating film 42, which has a lower impurity concentration than the first insulating film 41 and also has a film thickness of 65 nm, are laminated.

As described above, the first insulating film 41 has a gettering action because the impurities are injected at a high concentration.
It is possible to prevent diffusion of impurities such as sodium (Na) contained in glass.

The second insulating film 42 immediately below the gate electrode 34 or the upper electrode 44 serving as the metal electrode of the auxiliary capacitor 24 that affects the breakdown voltage is formed by the gate electrode 34 at the time of impurity implantation at the time of forming the LDD regions 36 and 37. Alternatively, since the upper electrode 44 serves as a mask, it can be made substantially free of impurities, that is, can be in an intrinsic state, and a decrease in breakdown voltage can be suppressed.

Further, the gate electrode 34 is formed of a molybdenum tungsten (MoW) alloy having a film thickness of 300 nm on the channel region 35 with the first insulating film 41 and the second insulating film 42 interposed therebetween. The scanning lines are formed so as to project in a direction orthogonal to the longitudinal direction of the scanning lines (not shown), and the scanning lines are provided in parallel. Then, the first insulating film 41
The portion of the second insulating film 42 between the gate electrode 34 and the channel region 35 functions as a gate insulating film portion 43.

In addition, the first insulating film 41 and the second insulating film
Like the gate electrode 34, an upper electrode 44 of molybdenum-tungsten alloy having a film thickness of 300 nm is formed on the lower electrode 38 via 42.
The upper electrode 44 is formed in a longitudinal shape parallel to a scanning line (not shown) and is continuously formed for each row as an auxiliary capacitance wiring. Then, a portion of the first insulating film 41 and the second insulating film 42 between the upper electrode 44 and the lower electrode 38 functions as a dielectric portion 45.

Further, the gate electrode of the thin film transistor 23
A film thickness of 400 n is formed on the upper electrode 44 of the storage capacitor 34 and the auxiliary capacitor 24.
An interlayer insulating film 46 of silicon oxide of m is formed.

Further, a film thickness of 100 nm for forming display elements in a matrix is formed on the interlayer insulating film 46 above the auxiliary capacitance 24.
An ITO (Indium Tin Oxide) pixel electrode 47 is formed.

Further, the interlayer insulating film 46 and the first insulating film
41 and the second insulating film 42 to penetrate the thin film transistor 23.
A contact hole 48 reaching the source region 32 and a contact hole 49 reaching the drain region 33 are respectively formed.

In the contact hole 48, aluminum (Al) having a film thickness of 600 nm that contacts the source region 32 is formed.
Source electrode 51 such as a simple substance or a laminated film or an alloy film
The source electrode 51 is integrally provided with a signal line (not shown), and a plurality of the signal lines are provided in a direction orthogonal to the upper electrode 44 serving as a scanning line and an auxiliary capacitance line. Therefore, the thin film transistor 23 is arranged at each intersection of the signal line and the scanning line.

The contact hole 49 has a film thickness of 600 nm for connecting the drain region 35 and the pixel electrode 47 to each other.
There is provided a drain electrode 52 made of a single substance such as aluminum or a laminated film or an alloy film.

Further, a silicon nitride (SiN _x ) passivation film 53 having a film thickness of 400 nm is formed on the interlayer insulating film 46 including the source electrode 51, the drain electrode 52 and the pixel electrode 47, and this passivation film 53 is formed. An opening 54 is formed to expose the pixel electrode 47.

On the passivation film 53 including the pixel electrode 47, an alignment film 55 is formed by rubbing a low temperature cure type polyimide by printing.

On the other hand, the counter substrate 13 is located above the thin film transistor 23 on an insulating substrate 61 such as transparent glass and shields the light to the thin film transistor 23 and also functions as a black matrix in a lattice or stripe form. -Shaped light-shielding film 62 is formed, and blue, red, and green color filters are formed on the insulating substrate 61 with the light-shielding film 62 as a boundary.
64 are formed, and a film thickness of 10 is formed on these color filters 64.
A counter electrode 65 of ITO having a thickness of 0 nm is formed.
An alignment film 66 that has been rubbed is formed on the 65.

A sealing material (not shown) is arranged around the matrix array substrate 12 and the counter substrate 13, and a liquid crystal layer 14 is provided between the matrix array substrate 12 and the counter substrate 13.
Are sealed and sandwiched, and polarizing plates (not shown) are attached to the outer surfaces of the matrix array substrate 12 and the counter substrate 13, respectively.

Next, a method of manufacturing the liquid crystal display device 11 will be described.

First, as shown in FIG. 2, plasma CVD (Plasma Chemical Vapor Depositio) is performed on the insulating substrate 21.
n) method, an undercoat layer 22 of silicon oxide and an amorphous silicon thin film are stacked to have a film thickness of about 50 nm, and the amorphous silicon thin film is heated and crystallized by a laser annealing method using an excimer laser or the like. Then, a polycrystalline silicon thin film 71 which is polysilicon is formed.

Here, on the entire surface of the polycrystalline silicon thin film 71,
You may dope P type impurities, such as boron.

Next, as shown in FIG. 3, the polycrystalline silicon thin film 71 is patterned to form a semiconductor layer of the thin film transistor 23.
31 and a portion of the auxiliary capacitor 24 that will become the lower electrode 38 and the like are left, and other unnecessary portions are removed by photoetching.

Then, as shown in FIG. 4, a first insulating film 41 of silicon oxide having a thickness of 70 nm is formed on the undercoat layer 22 including the semiconductor layer 31 of the thin film transistor 23 and the lower electrode 38 of the auxiliary capacitor 24 by the plasma CVD method. To form a film.

Further, a photoresist layer is formed on the entire surface of the first insulating film 41, and the photoresist layer is photoetched to form the source region 32 and the drain region of the semiconductor layer 31 of the thin film transistor 23 as shown in FIG. A resist mask 72 is selectively formed on portions other than 33. Impurities are implanted into the source region 32 and the drain region 33 of the thin film transistor 23, and at the same time, the impurities are implanted so as to reduce the resistance of the portion of the auxiliary capacitor 24 which will be the lower electrode 38.

For example, as shown in FIG. 6, through the resist mask 72, the lower electrode 38 of the auxiliary capacitor 24, the source region 32 and the drain region of the semiconductor layer 31 of the thin film transistor 23 are formed.
N-type impurities such as phosphorus (P) are implanted into 33 at a high concentration, for example, an accelerating voltage of 50 keV and a dose amount of 1.0E15 cm ⁻² .

Further, as shown in FIG. 7, a resist mask
72 is peeled off by the plasma ashing method. Note that the plasma ashing method causes damage to the surface of the first insulating layer 41 to form the damaged layer 73.

Then, as shown in FIG. 8, the first insulating film is formed.
The damaged layer 73 on the surface of 41 is removed by a dilute hydrofluoric acid treatment of cleaning with dilute hydrofluoric acid of 0.3% for 15 seconds, for example.

Next, as shown in FIG. 9, the first insulating film 41
The second insulating film 42 is formed on the entire surface of the substrate by the plasma CVD method.
Then, a silicon oxide film having a thickness of 65 nm is formed.

Further, as shown in FIG. 10, the second insulating film
A molybdenum-tungsten alloy film 74 having a film thickness of about 300 nm is deposited on the entire surface of 42 by sputtering.

Then, as shown in FIG. 11, the molybdenum-tungsten alloy film 74 is patterned into a predetermined shape by a photolithography process, and a portion which becomes the source region 32 and the drain region 33 of the semiconductor layer 31 is formed above the semiconductor layer 31. Thin film transistors located slightly inside
An upper electrode 44, which is slightly larger than the lower electrode 38, is formed above the gate electrode 34 and the lower electrode 38 of 23, and the other portions are removed.

After that, as shown in FIG. 12, N-type impurities such as phosphorus are implanted at a low concentration, for example, at an accelerating voltage of 80 keV and a dose amount of 3E13 cm ^{−2 using} the gate electrode 34 of the thin film transistor 23 as a mask.
The DD regions 36 and 37 are formed, the channel region 35 is formed in self alignment with the gate electrode 34, and an annealing process is performed to activate the implanted impurities.

Next, as shown in FIG. 13, a silicon oxide film is formed on the entire surface of the second insulating film 42 including the gate electrode 34 of the thin film transistor 23 and the upper electrode 44 of the auxiliary capacitor 24 by using the plasma CVD method. An interlayer insulating film 46 is deposited. Further, an ITO film having a film thickness of 100 nm is formed on the interlayer insulating film 46 by the sputtering method, and the pixel electrode 47 is formed on the ITO film by the photo etching method, and the other portions are removed.

Then, the interlayer insulating film 46, the first insulating film 41 and the second insulating film 42 are photoetched to reach the contact hole 48 reaching the source region 32 of the thin film transistor 23 and the drain region 33 of the thin film transistor 23. The contact hole 49 is opened.

Next, a simple substance such as aluminum or a laminated film or an alloy film of 400 nm in thickness is deposited on the interlayer insulating film 46 and in the contact holes 48 and 49 by a sputtering method, and is formed into a predetermined shape by a photoetching method. By patterning, the source electrode 51 of the thin film transistor 23 and the signal line and the drain electrode 52 integrated with the source electrode 51 are formed.

Further, the source electrode of the thin film transistor 23
51, a signal line integrated with the source electrode 51 and a drain electrode 52
And plasma CV on the interlayer insulating film 46 including the pixel electrode 47
A passivation film 53 of silicon nitride is formed to a thickness of 400 nm by the D method. Then, the opening 54 is formed above the pixel electrode 47 by the photoetching method.

Next, as shown in FIG. 1, an alignment film 55 is formed on the passivation film 53 including the pixel electrodes 47 to form the matrix array substrate 12.

Then, the counter substrate 13 is opposed to the matrix array substrate 12 with a gap therebetween to form a cell, and liquid crystal is injected into the gap between the matrix array substrate 12 and the counter substrate 13 and sealed to form a liquid crystal layer 14. To do.

Then, by attaching a polarizing plate (not shown) to the outer surfaces of the matrix array substrate 12 and the counter substrate 13, the liquid crystal display device 11 is formed.

According to the above embodiment, the source region 32 of the thin film transistor 23 is selectively formed on the lower electrode 38 of the auxiliary capacitor 24.
Also, since the impurities are implanted at a high concentration approximately equal to that of the drain region 33, the drive voltage can be reduced and the power consumption can be reduced.

Further, after the resist mask 72 at the time of implanting impurities into the lower electrode 38 is removed by plasma ashing, a dilute hydrofluoric acid treatment for removing the damaged layer 73 on the surface of the first insulating film 41 is performed. By doing so, since the gate insulating film portion 43 in the first insulating film 41 is not damaged, the characteristic deterioration of the thin film transistor 23 does not occur. Further, the first insulating film
Since the second insulating film 42 is laminated and formed on the first insulating film 41, even if a pinhole is formed in the first insulating film 41 during the dilute hydrofluoric acid treatment, the second insulating film 42 is formed. The gate electrode 34 of the gate insulating film portion 43 and the channel region 35 of the semiconductor layer 31
Since or short-circuit can be prevented by the dielectric part 45, it is possible to suppress a decrease in yield. Further, as compared with the first insulating film 41, when impurities are injected into the lower electrode 38 of the auxiliary capacitor 24, the source region 32 and the drain region 33 of the semiconductor layer 31 of the thin film transistor 23, the impurities are simultaneously injected. The characteristic change of the thin film transistor 23 can be suppressed by the gettering action of mobile ions due to impurities. On the other hand, merely injecting impurities into the insulating layer 40 may lower the insulating property of the insulating film 40, but since the second insulating film 42 containing substantially no impurities is laminated, the insulating film 40 It is possible to suppress the deterioration of the insulating property.

In the above embodiment, the semiconductor layer 31
Although the polycrystalline silicon thin film of 1 was prepared by the laser annealing method, it may be formed by solid phase growth of amorphous silicon.

The electrodes such as the gate electrode 34 and the signal lines are formed of a metal thin film formed by a sputtering method, and aluminum or an alloy thin film thereof is used. However, any conductive material may be used, and impurities are added. A silicon thin film may be used.

Further, N using phosphorus as an impurity to be implanted is used.
Although the description has been made using the N-type thin film transistor of the P-type semiconductor device, it can be applied to the P-type semiconductor device.

Furthermore, plasma C is formed on the interlayer insulating film 46.
Although silicon oxide, which is an oxide film formed by the VD method, is used, it may be formed by a thermal CVD method or a sputtering method, and not only an oxide film but any insulating film can be used.

Although the liquid crystal display device has been described as an example in the above-mentioned embodiment, the present invention is not limited to this, and display elements having a light emitting layer as a light modulation layer are arranged in matrix between opposed electrodes. It can also be applied to a self-luminous display device such as an organic EL display device.

[0057]

The present invention can suppress the voltage dependence and improve the yield.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one manufacturing process of a matrix array substrate of the above liquid crystal display device.

3 is a cross-sectional view showing the next manufacturing step of FIG. 2 of the matrix array substrate of the liquid crystal display device.

FIG. 4 is a cross-sectional view showing the next manufacturing step of FIG. 3 for the matrix array substrate of the above liquid crystal display device.

FIG. 5 is a cross-sectional view showing the next manufacturing step of FIG. 4 of the matrix array substrate of the liquid crystal display device.

6 is a cross-sectional view showing the next manufacturing step of FIG. 5 of the matrix array substrate of the liquid crystal display device.

FIG. 7 is a cross-sectional view showing the next manufacturing step of FIG. 6 for the matrix array substrate of the liquid crystal display device.

8 is a cross-sectional view showing the next manufacturing step of FIG. 7 for the matrix array substrate of the liquid crystal display device.

9 is a cross-sectional view showing the next manufacturing step of FIG. 8 for the matrix array substrate of the same liquid crystal display device.

10 is a cross-sectional view showing the next manufacturing step of FIG. 9 of the matrix array substrate of the liquid crystal display device.

FIG. 11 is a cross-sectional view showing the next manufacturing step of FIG. 10 for the matrix array substrate of the liquid crystal display device.

FIG. 12 is a cross-sectional view showing the next manufacturing step of FIG. 11 for the matrix array substrate of the liquid crystal display device.

FIG. 13 is a cross-sectional view showing the next manufacturing step of FIG. 12 for the matrix array substrate of the liquid crystal display device.

[Explanation of symbols]

11 Liquid crystal display device as a flat display device 21 Insulating substrate 23 Thin film transistor 24 auxiliary capacity 31 Semiconductor layer 32 Source area 33 drain region 34 Gate electrode 35 channel region 38 Lower electrode as semiconductor layer for auxiliary capacitance 40 insulating layer 41 First insulating film 42 Second insulating film 44 Upper electrode as metal electrode 47 Pixel electrode forming a display element 72 Resist mask

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2H092 JA24 JB56 JB63 JB66 MA07                       MA15 MA17 MA22 MA27 NA13                       NA16 NA29                 5C094 AA22 AA23 AA42 AA43 BA03                       BA43 CA19 DA15 EA04 EA07                       FB15 GB10                 5F110 AA12 BB01 CC02 DD02 DD13                       EE06 EE09 EE44 FF02 FF07                       FF09 FF30 FF36 GG02 GG13                       GG25 GG32 GG35 HJ01 HJ13                       HJ23 HL03 HL23 HM15 NN02                       NN03 NN04 NN23 NN24 NN34                       NN35 NN72 NN73 PP03

Claims (3)

[Claims] 1. A substrate, a plurality of thin film transistors formed on the substrate, a plurality of display elements connected to the thin film transistors and arranged in a matrix, and an auxiliary capacitor electrically connected to the display element. Semiconductor layer,
An insulating layer formed on the semiconductor layer for auxiliary capacitance and a metal electrode formed on the insulating layer are provided, and an auxiliary capacitance is formed by the semiconductor layer for auxiliary capacitance, the insulating layer, and the metal electrode. In the flat panel display device, the thin film transistor includes a semiconductor layer having a channel region and a source region and a drain region in which impurities are injected with the channel region interposed therebetween, and the semiconductor layer for auxiliary capacitance is the source of the thin film transistor. An impurity having a concentration approximately equal to that of the region and the drain region is implanted, and the insulating layer has a first insulating film in which the impurity is implanted in a predetermined concentration and an intrinsic state or a region in which an impurity of a concentration lower than the predetermined concentration is implanted. 2. A flat panel display device characterized by being formed by laminating two insulating films. 2. The flat panel display device according to claim 1, wherein the second insulating film is thicker than the first insulating film. 3. A step of simultaneously forming a semiconductor layer of a thin film transistor and a semiconductor layer for auxiliary capacitance on a substrate, and a first insulating film so as to cover the semiconductor layer of the thin film transistor and the semiconductor layer for auxiliary capacitance. A step of forming, and a resist mask having a shape that covers a portion to be a channel region of the thin film transistor and exposes the source region, the drain region of the thin film transistor, and the entire surface of the semiconductor layer for auxiliary capacitance on the first insulating film. A step of forming, a step of implanting an impurity into the source region, the drain region of the thin film transistor, and the entire surface of the auxiliary capacitance semiconductor layer through the resist mask; a step of removing the resist mask; Cleaning the insulating film, forming a second insulating film on the first insulating film, Forming a metal layer on the insulating film, and patterning the metal layer to form a gate electrode of the thin film transistor and a metal electrode facing the semiconductor layer for auxiliary capacitance. Method for manufacturing flat display device.