JP2003131590A - Planar display device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a planar display device of which the voltage dependency is suppressed. SOLUTION: After an auxiliary capacitance semiconductor layer 37 and then a resist mask are formed, impurity ions are injected into the auxiliary capacitance semiconductor layer 37. The part of the resist altered by injecting the impurity ions is dry-ashed without exposing semiconductor layers 31, 41, 45, and the remaining resist is removed by wet-etching. A gate insulating film 51 is formed after the impurity ions are injected into the auxiliary capacitance semiconductor layer 37 so that no impurities are present in a gate insulating film 51. Since the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24 contains the impurities at a high concentration, a leakage current is lowered to suppress the rate of dot defect generation. Since no impurities are present in the di-electric layer of the auxiliary capacitance semiconductor layer 37, deterioration in the characteristics of thin film transistors 23 for pixels, thin film transistors 25 for a p-type driving circuit, and thin film transistors 26 for an N-type driving circuit does not occur.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device having display elements arranged in a matrix and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, a typical flat display device is, for example, a liquid crystal display device, and this liquid crystal display device is required to have high function and high definition display while having high density and large capacity. Since a high-quality image can be obtained in a large area, an active switching element is arranged corresponding to each of the display elements arranged in a matrix, and an active matrix type in which the display element is controlled by this switching element is used. Mainstream. Further, one of the characteristics of the active matrix type is a memory holding operation for holding a drive voltage supplied via a switching element for a predetermined period, and has an auxiliary capacity for memory holding corresponding to each display element. ing. As described above, the auxiliary capacitance is used to obtain a high-quality image, and in particular, in order to simplify the manufacturing process, the MO layer in which the dielectric layer is sandwiched between the semiconductor layer and the metal electrode is used.
The auxiliary capacitance of the S (Metal Oxide Semiconductor) structure is often used.

Further, impurity ions are not implanted into the semiconductor layer of the auxiliary capacitance of the conventional MOS structure, or impurity ions are implanted only at a low concentration. When the impurity ions are not implanted or the semiconductor layer having a low impurity ion concentration is used, if the voltage V _cs applied to the metal electrode is sufficiently higher than the voltage V _sig applied to the semiconductor layer, the auxiliary Although the capacitance forms a sufficient capacitance, when the voltage V _cs applied to the metal electrode is lower than the voltage V _sig applied to the semiconductor layer, the auxiliary capacitance hardly forms a capacitance, and as shown in FIG. The voltage V _cs applied to the semiconductor layer has a voltage dependence of the voltage V _sig applied to the semiconductor layer. Also,
In order to obtain a sufficient auxiliary capacitance, the voltage V _cs applied to the metal electrode-the voltage V _sig applied to the semiconductor layer needs to be 6 V or more.

Therefore, for example, when the driving voltage range of the voltage V _sig applied to the semiconductor layer is 1 V to 9 V, the voltage V _cs applied to the metal electrode needs to be 15 V, and the voltage applied to the metal electrode at this time. V _{cs −The} voltage V _sig applied to the semiconductor layer is driven in a high voltage range of 6 V to 14 V.

With such a high applied voltage, the dielectric layer sandwiched between the semiconductor layer and the metal electrode is deteriorated, and an increase in leak current or a short circuit occurs between the semiconductor layer and the metal electrode. There is a possibility that the number of point defects in the initial state may deteriorate, or the quality may decrease, or the number of point defects may increase during driving, which may reduce reliability.

On the other hand, in order to obtain a sufficient storage capacity, it is necessary to implant high-concentration impurity ions into the semiconductor layer of the storage capacity. In this high-concentration impurity ion implantation step, for example, a semiconductor layer is formed, a gate oxide film is formed on this semiconductor layer, a resist is patterned on this gate oxide film, and impurity ions are implanted in the semiconductor layer in this state. Methods of implanting and stripping the resist are known.

However, in such a method, since impurity ions are implanted into the semiconductor layer through the gate oxide film,
There is damage to the gate oxide film and undesired loss of impurity ions in the gate oxide film, which requires a large dose amount, which is not preferable in terms of productivity.

Therefore, bare doping in which impurity ions are implanted before the formation of the gate insulating film can be considered, but a semiconductor layer in which impurity ions are implanted at a high concentration is subjected to CVD (Chemical).
When the gate insulating film is formed on the semiconductor layer by being inserted into a vapor deposition device or the like, impurity ions are diffused and the inside of the CVD device is contaminated, and the quality is deteriorated.

[0009]

When manufactured by the above-mentioned method, there are problems that the quality is deteriorated and the productivity is unfavorable.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a flat panel display device having improved quality without lowering productivity and a manufacturing method thereof.

[0011]

According to the present invention, a substrate and a plurality of display elements arranged in a matrix on the substrate are provided.
A plurality of thin film transistors connected to the plurality of display elements, an auxiliary capacitance semiconductor layer electrically connected to the display element, a dielectric layer formed on the auxiliary capacitance semiconductor layer, and a dielectric layer on the dielectric layer. And a metal electrode formed on
In a flat display device in which an auxiliary capacitance is formed by the auxiliary capacitance semiconductor layer, the dielectric layer, and the metal electrode, the thin film transistor includes a channel region, and a source region and a drain region into which impurity ions are implanted with the channel region interposed therebetween. A semiconductor layer having an impurity concentration of substantially the same concentration as the source region and the drain region of the thin film transistor are implanted into the auxiliary capacitance semiconductor layer in the same step, and the dielectric layer is in an intrinsic state. Since the auxiliary capacitance semiconductor layer is doped with impurity ions having a concentration approximately equal to that of the source region and the drain region of the thin film transistor, an appropriate auxiliary capacitance can be formed without increasing the voltage more than necessary and the auxiliary capacitance dielectric Since the body layer is in an intrinsic state, there is no fear that the characteristics will deteriorate.

A substrate, a plurality of display elements arranged in a matrix on the substrate, a semiconductor layer formed on the substrate, a gate insulating film of a dielectric layer formed on the semiconductor layer, and In a flat display device including a plurality of thin film transistors formed of gate electrodes of metal electrodes formed on the dielectric layer and connected to the plurality of display elements, a source region and a drain region of the thin film transistor are implanted. The concentration of impurity ions is 1 × 10 ²⁰
at atoms / cm ³ or more, the dielectric layer is formed by stacking on the semiconductor layer, and the layer on the semiconductor side is in an intrinsic state,
The metal electrode side layer contains carbon of 1 × 10 ²⁰ atoms / cm ³ or more, and the metal electrode side layer of the dielectric layer is 1
Since carbon of not less than × 10 ²⁰ atoms / cm ³ is contained and the layer on the semiconductor side is in an intrinsic state, there is no fear of deteriorating the characteristics.

Furthermore, the present invention provides a thin film transistor formed on a substrate, a display element connected to the thin film transistor, an auxiliary capacitance semiconductor layer electrically connected to the display element, and the auxiliary capacitance semiconductor layer. Of a flat display device having a dielectric layer formed on the dielectric layer and a metal electrode formed on the dielectric layer, the storage capacitor comprising the storage capacitor semiconductor layer, the dielectric layer, and the metal electrode. In the manufacturing method, on the substrate, a step of simultaneously forming the semiconductor layer of the thin film transistor and the auxiliary capacitance semiconductor layer, covering a portion which will be a channel region of the thin film transistor, a source region of the thin film transistor, a drain region, and Forming a resist mask having a shape exposing the entire surface of the auxiliary capacitance semiconductor layer on the semiconductor layer; Through a mask, implanting impurity ions into the source region, the drain region of the thin film transistor, and the entire surface of the auxiliary capacitance semiconductor layer, removing the resist mask, and the semiconductor layer of the thin film transistor and the auxiliary capacitance semiconductor. Forming the dielectric layer so as to cover the layer, forming a metal layer on the dielectric layer, and patterning the metal layer to face the gate electrode of the thin film transistor and the auxiliary capacitance semiconductor layer. And a step of forming a metal electrode,
Since the impurity ions are implanted into the auxiliary capacitance semiconductor layer, an appropriate auxiliary capacitance can be formed without increasing the voltage more than necessary, and there is no fear that impurity ions are implanted into the dielectric layer and the characteristics deteriorate.

Still further, according to the present invention, a plurality of display elements arranged in a matrix on a substrate, a semiconductor layer formed on the substrate, and a gate insulating film of a dielectric layer formed on the semiconductor layer. And a method for manufacturing a flat display device comprising a plurality of thin film transistors formed of a gate electrode of a metal electrode formed on the dielectric layer and connected to the plurality of display elements, wherein the thin film transistor of the thin film transistor is formed on the substrate. Forming a semiconductor layer, forming a resist mask on the semiconductor layer, the resist mask having a shape that covers the channel region of the thin film transistor and exposes the entire source and drain regions of the thin film transistor; Via the step of implanting impurity ions into the source region and the drain region of the thin film transistor via Removing the resist mask,
Oxidizing the surface of the semiconductor layer of the thin film transistor to form an oxide film, forming the dielectric layer so as to cover the oxide film, and forming a metal layer on the dielectric layer, This metal layer is patterned to form a gate electrode of the thin film transistor, and the thin film transistor is operated at an appropriate voltage without raising the voltage more than necessary because impurity ions are implanted in the semiconductor layer. In addition to being able to operate, there is no possibility that impurity ions will be injected into the dielectric layer and the characteristics will not deteriorate.By forming the dielectric layer after oxidizing the surface of the semiconductor layer, the impurity ions in the semiconductor layer do not diffuse. Prevent pollution and improve productivity.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a liquid crystal display device 11 has a pixel portion 12 having a rectangular shape in plan view.
A drive circuit unit 14 for driving the pixel unit 12 is formed in the frame portion around the side.

In the liquid crystal display device 11, a counter substrate 16 is provided so as to face the matrix array substrate 15, and a liquid crystal layer 17 is sandwiched between the matrix array substrate 15 and the counter substrate 16 as a light modulation layer. Has been done.

First, in the matrix array substrate 15, an undercoat layer 22 having a film thickness of 50 nm is formed on an insulating substrate 21 such as transparent glass, and on the undercoat layer 22,
A thin film transistor for a pixel (Thin Film Tr
an anistor) 23, an auxiliary capacitor 24, a P-type drive circuit thin film transistor 25, and an N-type drive circuit thin film transistor 26 are formed.

In the pixel thin film transistor 23, a semiconductor layer 31 of polycrystalline silicon having a film thickness of 50 nm to be an active layer is formed on the undercoat layer 22, and the semiconductor layer 31 is formed.
Is a channel region 32 which is formed at a position corresponding to the gate electrode 30 and which contains an impurity having a concentration lower than a predetermined concentration or does not contain an impurity, for example, the channel region 32 in an intrinsic state in which the impurity concentration is below the detection limit, and an impurity having a predetermined concentration LDD (Lightly Doped Drai) disposed between the source region 33 and the drain region 34 including the channel region 32 and the source region 33.
n) a region 35 and an LDD region 36 arranged between the channel region 32 and the drain region 34, respectively.

Further, as one electrode of the auxiliary capacitor 24, an auxiliary of polycrystalline silicon containing a high concentration of impurities, for example, an impurity having a concentration substantially equal to that of the impurities contained in the source / drain regions 33 and 34 of the pixel thin film transistor 23 is used. Capacitive semiconductor layer 37
Are formed.

Further, a thin film transistor for a P-type drive circuit
25 is a film thickness of 50 n which becomes an active layer on the undercoat layer 22.
m semiconductor layer 41 is formed, and the semiconductor layer 41 is formed at a position corresponding to the gate electrode 40 and contains an impurity having a concentration lower than a predetermined concentration or does not contain an impurity, for example, an intrinsic concentration having an impurity concentration equal to or lower than a detection limit. A channel region 42 in such a state, a drain region 43 containing a predetermined concentration of impurities, and a source region 44 are provided.

Further, a thin film transistor for N-type drive circuit
26, the semiconductor layer 45 is formed on the undercoat layer 22,
The semiconductor layer 45 includes a channel region 46 formed at a position corresponding to the gate electrode 52 and having an impurity concentration lower than a predetermined concentration or being in an intrinsic state, and a drain region 47 and a source region 48 containing an impurity having a predetermined concentration. An LDD region 49 arranged between the channel region 46 and the drain region 47, and an LDD region 50 arranged between the channel region 46 and the source region 48.

Further, the semiconductor layer 31 of the pixel thin film transistor 23, the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, the semiconductor layer 41 having a film thickness of 50 nm which becomes the active layer of the P-type drive circuit thin film transistor 25, and the N-type drive circuit thin film transistor. On the semiconductor layer 45 of 26, a gate insulating film 51 of silicon oxide (SiO _x ) which is a dielectric layer of TEOS (TetraEthyl OrthoSilicate) which also functions as a dielectric of the auxiliary capacitance 24 is formed. The gate insulating film 51 has a region containing a low concentration of impurities and a region in an intrinsic state. this house,
The region in the intrinsic state is, for example, the gate electrodes 30, 40,
Channel regions 32, 42, 46 and metal electrode 54 corresponding to 52
Is an area corresponding to.

Further, on the channel region 32 of the semiconductor layer 31 of the pixel thin film transistor 23 via the gate insulating film 51, a gate electrode 30 of molybdenum tungsten (MoW) alloy having a film thickness of 300 nm is formed. The gate electrode 30 is formed so as to project in a direction orthogonal to the longitudinal direction of the scanning line (not shown), and the scanning lines are provided in parallel.

A metal electrode 54 of molybdenum-tungsten alloy having a film thickness of 300 nm is formed on the auxiliary capacitance semiconductor layer 37 via the gate insulating film 51. The metal electrode 54 has a longitudinal shape parallel to a scanning line (not shown). Is.

Further, the channel region of the semiconductor layer 41 of the P-type drive circuit thin film transistor 25 via the gate insulating film 51.
A molybdenum-tungsten alloy gate electrode 40 having a film thickness of 300 nm is formed on 42, and a 300 nm film thickness is formed on the channel region 46 of the semiconductor layer 45 of the N-type drive circuit thin film transistor 26 via the gate insulating film 51. A gate electrode 52 of molybdenum-tungsten alloy is formed.

Further, on the gate electrode 30 of the pixel thin film transistor 23, the metal electrode 54 of the auxiliary capacitance semiconductor layer 37, the gate electrode 40 of the P-type driving circuit thin film transistor 25 and the gate electrode 52 of the N-type driving circuit thin film transistor 26. An interlayer insulating film 57 of silicon oxide having a film thickness of 600 nm is formed.

Further, the interlayer insulating film 57 and the gate insulating film
The source region 33 of the pixel thin film transistor 23 is penetrated through 51.
Reaching contact hole 61, thin film transistor for pixel
A contact hole 62 reaching the drain region 34 of 23 and a contact hole reaching the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24.
63, drain region of thin film transistor 25 for P-type drive circuit
A contact hole 64 reaching 43 and a contact hole reaching the source region 44 of the P-type drive circuit thin film transistor 25.
65, drain region of thin film transistor 26 for N-type drive circuit
A contact hole 66 that reaches 47 and a contact hole 67 that reaches the source region 48 of the N-type drive circuit thin film transistor 26 are formed.

The contact hole 66 has a source electrode in contact with the source region 33 of the pixel thin film transistor 23.
71 is provided, and a signal line (not shown) is integrally provided with the source electrode 71. The signal line is a scanning line and a metal electrode.
Multiple pieces are provided in a direction orthogonal to 54. Therefore, the pixel thin film transistors 23 are arranged at the respective intersections of the signal lines and the scanning lines.

Further, the contact hole 62 and the contact hole 63 are provided with a drain electrode 73 which also serves to connect the drain region 34 of the pixel thin film transistor 23 and the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24 to each other, and the contact hole 64. Is connected to the drain electrode 74 connected to the drain region 43 of the P-type drive circuit thin film transistor 25, the contact hole 65 and the contact hole 66 are connected to the source region 44 of the P-type drive circuit thin film transistor 25, and is connected to the N-type drive circuit thin film transistor. A common electrode 75 connected to the drain region 47 of 26 and a common electrode 75 connected to the source region 48 of the N-type drive circuit thin film transistor 26 are provided in the contact hole 67. In addition, these source electrode 71, drain electrode 73, drain electrode 74, common electrode
The 75 and the source electrode 77 are formed of a simple substance such as aluminum (Al) or a laminated film or an alloy film with a film thickness of 600 nm.

Further, the source electrode 71, the drain electrode 73, the drain electrode 74, the common electrode 75 and the source electrode 77.
A protective insulating film 78 made of silicon nitride (SiN _x ) is formed on the protective insulating film 78.
A contact hole 79 exposing the drain electrode 73 of 23 is formed.

On the protective insulating film 78, a color filter layer 80 having a film thickness of 2 μm, which is an organic insulating film in which pigmented red, green or blue colored layers of three colors are formed in stripes, is formed. A contact hole 81 exposing the drain electrode 73 of the pixel thin film transistor 23 is also formed in the color filter layer 80.

Further, on the color filter layer 80,
I having a film thickness of 1 μm as a display electrode constituting a display element
A pixel electrode 82 of TO (Indium tin Oxide) is formed, and this pixel electrode 82 is electrically connected to the drain electrode 73 of the pixel thin film transistor 23.

Further, a color filter layer including the pixel electrode 82
An alignment film 83 that has been rubbed by printing and applying low temperature cure type polyimide is formed on the surface 80.

On the other hand, the counter substrate 16 comprises an ITO counter electrode 93 having a thickness of 100 nm on an insulating substrate 91 such as transparent glass.
And a rubbing-treated alignment film 94 is formed on the counter electrode 93.

A liquid crystal layer 17 is sealed and sandwiched between the matrix array substrate 15 and the counter substrate 16, and polarizing plates 96 and 97 are attached to the opposite surfaces of the matrix array substrate 15 and the counter substrate 16, respectively. Has been done.

Next, a method of manufacturing the liquid crystal display device 11 will be described.

First, as shown in FIG. 2, plasma CVD (Plasma Chemical Vapor Depositio) is performed on the insulating substrate 21.
n) method, the undercoat layer 22 of a silicon oxide film, the semiconductor layer 31 of the pixel thin film transistor 23, the auxiliary capacitance
The amorphous silicon thin film 101 to be the auxiliary capacitance semiconductor layer 37 of 24, the semiconductor layer 41 of the P-type drive circuit thin film transistor 25, and the semiconductor layer 45 of the N-type drive circuit thin film transistor 26 is
The film is formed with a film thickness of about 0 nm.

Here, as shown in FIG. 3, this amorphous silicon thin film 101 was subjected to an ion doping method at an acceleration voltage of 10 keV and a dose of 4 × 10 ¹¹ atoms / cm 3.
² , B ₂ H ₆ / H ₂ as source gas, boron (B)
P-type impurity ions such as may be implanted at a low concentration.

Next, ELA (excimer laser annealing)
Method is used to polycrystallize the amorphous silicon thin film 101 into a polycrystalline silicon film, a resist is applied to the polycrystalline silicon film, and as shown in FIG. 4, the resist is formed into an island-shaped resist mask 102 by a photolithography process. Etching is performed on the semiconductor layer 31 of the pixel thin film transistor 23, the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, the semiconductor layer 41 of the P-type drive circuit thin film transistor 25, and the N-type drive circuit thin film transistor 26 by using the resist mask 102 as a mask. The semiconductor layer 45 of is formed.

Thereafter, as shown in FIG. 5, the resist mask 102 is peeled off, a resist is further applied, and the resist mask 103 patterned into a desired shape by a photolithography process is used as a mask, and the auxiliary capacitor semiconductor layer of the auxiliary capacitor 24 is used. 37, a source region 33 and a drain region 34 of the semiconductor layer 31 of the pixel thin film transistor 23, and a drain region 47 and a source region 48 of the semiconductor layer 45 of the N-type drive circuit thin film transistor 26, an acceleration voltage of 10 keV, 2 × 10 ¹⁴ at
N 3 -type impurity ions such as phosphorus (P) are implanted at a high concentration using PH ₃ / H ₂ as a source gas at a dose amount of oms / cm ² .

After implanting the impurity ions, as shown in FIG. 6, the surface layer including the altered layer of the resist mask 103 is removed by dry ashing using a dry etching apparatus. The dry ashing is preferably performed for 25% to 50% of the time for the full ashing. If it is less than 25%, the deteriorated layer on the surface of the resist mask 103 cannot be removed, and if it is more than 50%, a region where the semiconductor layers 31, 41, 45 are partially exposed is generated, and the pixel thin film transistor 23 and the P-type drive circuit. The characteristics of the thin film transistor 25 and the N-type driving circuit thin film transistor 26 deteriorate.

After removing the surface layer by dry ashing, as shown in FIG. 7, the resist mask 103 is removed by wet etching with a resist stripping solution (eg, N321 manufactured by Nagase & Co., TOK104 manufactured by Tokyo Ohka Kogyo).

Then, as shown in FIG. 8, normal pressure (AP)
The semiconductor layer 31 of the pixel thin film transistor 23, the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, the semiconductor layer 41 of the P-type drive circuit thin film transistor 25, and the semiconductor layer 45 of the N-type drive circuit thin film transistor 26 are formed by the CVD method or the plasma CVD method. A gate insulating film 51, which also functions as a dielectric layer of the auxiliary capacitor 24 of silicon oxide, is formed on the entire surface of the undercoat layer 22 including the film with a thickness of 80 nm to 140 nm.

Next, as shown in FIG. 9, the gate insulating film 51 is formed.
A molybdenum-tungsten alloy film 104 having a film thickness of about 300 nm is deposited on the entire upper surface by a sputtering method.

Then, as shown in FIG. 10, the molybdenum-tungsten alloy film 104 is patterned into a predetermined shape by a photolithography process to form the gate electrode 40 of the P-type drive circuit thin film transistor 25. Then, using this gate electrode 40 as a mask, an acceleration voltage of 50 keV to 7
0keV, B ₂ at a dose of 2 × 10 ¹⁵ atoms / cm ²
P-type impurity ions such as boron are implanted at a high concentration using H ₆ / H ₂ as a source gas to form the drain region 43 and the source region 44 of the P-type drive circuit thin film transistor 25.

Further, as shown in FIG. 11, the molybdenum-tungsten alloy film 104 is patterned into a predetermined shape to form the gate electrode 30 of the pixel thin film transistor 23, the gate electrode 52 of the N-type drive circuit thin film transistor 26 and the auxiliary capacitor 24. The metal electrode 54 is formed. At this time, the metal electrode 54 of the auxiliary capacitance 24 sufficiently covers the auxiliary capacitance semiconductor layer 37, and the side edge in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 is a metal electrode in plan view.
Patterning is performed so as to be positioned inside the longitudinal side edge of 54.

After that, in the LDD forming step, a pixel thin film is formed.
Gate electrode 30 of transistor 23 and thin for N-type drive circuit
Acceleration using the gate electrode 52 of the film transistor 26 as a mask
Voltage 50 keV to 70 keV, 5 × 10¹³atoms /
cm²PH at the dose amount of₃/ H ₂Due to N-type
A thin film transistor for pixels, which is implanted with pure ions at a low concentration
23 LDD regions 35, 36 and thin film transistor for N-type drive circuit
The LDD regions 49, 50 of the transistor 26 are formed. After this, 50
Anneal for 1 hour at 0 ℃ to 600 ℃,
Activate the entered impurities.

Next, as shown in FIG. 12, in the interlayer insulating film forming step, the gate electrode 30 of the pixel thin film transistor 23, the metal electrode 54 of the auxiliary capacitance 24, the gate electrode 40 of the P-type drive circuit thin film transistor 25 are formed. And a gate insulating film 51 including the gate electrode 52 of the N-type drive circuit thin film transistor 26.
A film thickness of 600 nm is formed on the entire surface by using the plasma CVD method.
The silicon oxide interlayer insulating film 57 is deposited.

Subsequently, as shown in FIG. 13, in the contact hole forming step, the interlayer insulating film 57 and the gate insulating film are formed.
A contact hole 61 reaching the source region 33 of the pixel thin film transistor 23, a contact hole 62 reaching the drain region 34 of the pixel thin film transistor 23, a contact hole 63 reaching the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, by photoetching at 51. Contact holes 64 reaching the drain region 43 of the P-type drive circuit thin film transistor 25, P
Contact hole 65 reaching the source region 44 of the N-type driving circuit thin film transistor 25, contact hole 66 reaching the drain region 47 of the N-type driving circuit thin film transistor 26, and the source region of the N-type driving circuit thin film transistor 26
A contact hole 67 reaching 48 is formed.

Next, as shown in FIG. 14, the interlayer insulating film 57 is formed.
Top and contact holes 61, 62, 63, 64, 65, 66, 67
A single or laminated film of aluminum or the like, or an alloy film 105 is deposited therein to a thickness of about 500 nm.

Then, as shown in FIG. 15, the alloy film 105 is patterned into a predetermined shape by a photoetching method, and the source electrode 71 of the pixel thin film transistor 23, the signal line and the drain electrode 73 integrated with the source electrode 71, The drain electrode 74 and the common electrode 75 of the P-type drive circuit thin film transistor 25, and the common electrode 75 and the source electrode 77 of the N-type drive circuit thin film transistor 26 are formed.

Further, as shown in FIG. 16, the source electrode 71 of the pixel thin film transistor 23, the signal line and drain electrode 73 integrated with the source electrode 71, the drain electrode 74 and the common electrode 75 of the P-type drive circuit thin film transistor 25, A protective insulating film 78 of silicon nitride is formed by plasma CVD on the interlayer insulating film 57 including the common electrode 75 and the source electrode 77 of the N-type drive circuit thin film transistor 26.

Then, as shown in FIG. 17, a contact hole 79 for exposing the drain electrode 73 of the pixel thin film transistor 23 is formed in the protective insulating film 78 by photoetching.
To form.

Next, as shown in FIG. 18, a transparent organic insulating film of three color layers of red, green and blue in which pigments are dispersed is applied to the entire surface in a stripe shape with a thickness of 2 μm to form a color filter. Form layer 80.

Further, as shown in FIG. 19, a contact hole 81 exposing the drain electrode 73 of the pixel thin film transistor 23 is formed in the color filter layer 80.

Then, as shown in FIG. 20, ITO is formed into a film having a thickness of about 100 nm by a sputtering method and patterned into a predetermined shape by a photo etching method to form a pixel electrode 82.

Finally, low temperature cure type polyimide is printed and applied on the protective insulating film 78 including the pixel electrodes 82, and the alignment film 83 is formed by rubbing treatment to form the matrix array substrate 15.

On the other hand, the counter substrate 16 is formed on the insulating substrate 91 by I
TO is deposited to a film thickness of about 100 nm by the sputtering method,
The counter electrode 93 is formed.

On the counter electrode 93, polyimide is applied by printing, and a rubbing treatment is performed to form an alignment film 94, whereby the counter substrate 16 is formed.

Matrix array substrate formed in this way
The liquid crystal layer 17 is formed by injecting liquid crystal into the gap between the matrix array substrate 15 and the counter substrate 16 and sealing them by making 15 and the counter substrate 16 face each other through a gap to form a cell.

Then, by attaching the polarizing plates 96 and 97 to the outer surfaces of the matrix array substrate 15 and the counter substrate 16, the liquid crystal display device 11 is formed.

According to the above embodiment, the impurity concentration of the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24 is 10 ²⁰ atoms / min.
Since it is cm ³ or more, the voltage dependence can be reduced to lower the potential between the auxiliary capacitance semiconductor layer 37 and the metal electrode 54, and a flat display device with low power consumption and good display quality can be realized. Further, it is possible to suppress the leak current generated due to the high driving voltage and suppress the occurrence rate of point defects. Further, since there is no impurity in the portion of the gate insulating film 51 corresponding to the channel of the thin film transistor, that is, in the intrinsic state, the characteristics of the pixel thin film transistor 23, the P-type drive circuit thin film transistor 25, and the N-type drive circuit thin film transistor 26 are characteristic. No deterioration will occur.

Further, since the impurity is ion-implanted into the auxiliary capacitance semiconductor layer 37 before the gate insulating film 51 is formed, the impurity is added to the auxiliary capacitance semiconductor layer 37 in the auxiliary capacitance 24 as shown in FIG. 21A. It exists only in 37, and there are no impurities in the dielectric layer. In the case of the conventional example, as shown in FIG. 21B, the impurities are present so as to have a peak in the dielectric layer.

Further, since the impurity ions are implanted before the gate insulating film 51 is formed, the dose amount can be reduced to about 1/10 of the case where the impurity ions are implanted after the gate insulating film 51 is formed. It is possible to inject a high concentration of impurities into the auxiliary capacitance semiconductor layer 37 while shortening the process time. In addition, damage to the gate insulating film 51 at the time of implanting impurity ions can be prevented.

If the resist mask 103 is completely removed by ashing, the semiconductor layers 31, 41, 45 are exposed in the ashing device, and the channel regions 32, 42, 46 of the semiconductor layers 31, 41, 45 are exposed. A resist mask 10 that contains defects that are exposed to plasma, so-called electric charges, and that contains high-concentration impurities
Impurities in the device due to ashing of 3 cause impurities to adhere to the surface, reducing field-effect mobility, shifting in the negative direction of the threshold voltage, and increasing the S value. Such an adverse effect can be prevented by not ashing all 103.

Next, another embodiment will be described with reference to FIGS. 22 and 23.

The liquid crystal display device 11 shown in FIG. 22 is basically the same as the above-mentioned liquid crystal display device 11 shown in FIGS. 1 to 20, except that the dielectric layers are formed on the surfaces of the semiconductor layers 31, 41 and 45. The gate insulating films 111, 112, and 113 are formed below the oxide film forming the oxide film, and the oxide film 114 is formed on the surface of the auxiliary capacitance semiconductor layer 37. Then, the lower gate insulating film 111, 1
12, 113 are the semiconductor layers 31, 41, 45 side and the gate insulating film 51 is the upper side which is the gate electrodes 30, 40, 52 side, and the lower gate insulating films 111, 112, 113 and the gate insulating film 51 are It is in a state of being laminated in two layers. In addition, any of the gate insulating films 51, 11
1, 112, 113 do not contain impurity ions, for example, below the detection limit, and the gate insulating films 111, 112, 113 do not contain carbon (C), and similarly, for example, below the detection limit, the gate The insulating film 51 contains carbon (C) of 1 to 2 × 10 ²⁰ at
oms / cm ³ or more, for example, 1 × 10 ²⁰ atoms /
cm ^{3 is} included.

Next, a method of manufacturing the liquid crystal display device shown in FIG. 22 will be described. The method of manufacturing the liquid crystal display device shown in FIG. 22 is basically the same as that of the above-described liquid crystal display device 11 shown in FIGS. 1 to 20, but after the step shown in FIG. After the resist mask 103 is wet-etched, the surfaces of the semiconductor layers 31, 41, 45 are washed with ozone to form oxide gate insulating films 111, 112, 113 on the surfaces of the semiconductor layers 31, 41, 45. It is a thing. Then, after that, similarly, the steps of FIGS.
The liquid crystal display device 11 shown in FIG. 22 is formed.

The liquid crystal display device 11 shown in FIG.
Also has basically the same actions and effects as those of the liquid crystal display device 11 described above, but further includes gate insulating films 111, 112, 113 of oxide films and auxiliary capacitance semiconductor layers on the surfaces of the semiconductor layers 31, 41, 45. By forming the oxide film 114 on the surface of 37, these gate insulating films 111, 112, 113 and the oxide film 114 serve as capping layers, respectively. Therefore, for example, when the gate insulating film 51 is formed in the subsequent steps. Even if it is processed by a device such as CVD, the impurity ions do not diffuse from the semiconductor layers 31, 41, 45 into the device, so that process contamination does not occur and the productivity is further improved.

In the above-described embodiments, the liquid crystal display device is used as an example for description, but the present invention is not limited to this, and the display elements having the light emitting layer as the light modulation layer between the opposing electrodes are arranged in a matrix. For example, it can be applied to a self-luminous display device such as an organic EL display device.

[0072]

According to the present invention, quality such as characteristics can be improved without lowering productivity.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one manufacturing process of a matrix array substrate of the above liquid crystal display device.

3 is a cross-sectional view showing the next manufacturing step of FIG. 2 of the matrix array substrate of the liquid crystal display device.

FIG. 4 is a cross-sectional view showing the next manufacturing step of FIG. 3 for the matrix array substrate of the above liquid crystal display device.

FIG. 5 is a cross-sectional view showing the next manufacturing step of FIG. 4 of the matrix array substrate of the liquid crystal display device.

6 is a cross-sectional view showing the next manufacturing step of FIG. 5 of the matrix array substrate of the liquid crystal display device.

FIG. 7 is a cross-sectional view showing the next manufacturing step of FIG. 6 for the matrix array substrate of the liquid crystal display device.

8 is a cross-sectional view showing the next manufacturing step of FIG. 7 for the matrix array substrate of the liquid crystal display device.

9 is a cross-sectional view showing the next manufacturing step of FIG. 8 for the matrix array substrate of the same liquid crystal display device.

10 is a cross-sectional view showing the next manufacturing step of FIG. 9 of the matrix array substrate of the liquid crystal display device.

FIG. 11 is a cross-sectional view showing the next manufacturing step of FIG. 10 for the matrix array substrate of the liquid crystal display device.

FIG. 12 is a cross-sectional view showing the next manufacturing step of FIG. 11 for the matrix array substrate of the liquid crystal display device.

FIG. 13 is a cross-sectional view showing the next manufacturing step of FIG. 12 for the matrix array substrate of the liquid crystal display device.

14 is a cross-sectional view showing the next manufacturing step of FIG. 13 of the matrix array substrate of the liquid crystal display device.

15 is a cross-sectional view showing the next manufacturing step of FIG. 14 for the matrix array substrate of the liquid crystal display device.

16 is a cross-sectional view showing the next manufacturing step of FIG. 15 for the matrix array substrate of the same liquid crystal display device.

FIG. 17 is a cross-sectional view showing the next manufacturing step of FIG. 16 of the matrix array substrate of the liquid crystal display device.

FIG. 18 is a cross-sectional view showing the next manufacturing step of FIG. 17 for the matrix array substrate of the liquid crystal display device.

FIG. 19 is a cross-sectional view showing the next manufacturing step of FIG. 18 for the matrix array substrate of the liquid crystal display device.

FIG. 20 is a cross-sectional view showing the next manufacturing step of FIG. 19 for a matrix array substrate of the same liquid crystal display device.

FIG. 21 is a graph showing the impurity concentration of the storage capacitor of the above liquid crystal display device. (A) Auxiliary capacity of the embodiment (b)
Conventional example

FIG. 22 is a sectional view showing a liquid crystal display device of another embodiment of the above.

FIG. 23 is a cross-sectional view showing the manufacturing process between the matrix array substrate of the liquid crystal display device and the process shown in FIGS.

FIG. 24 is a graph showing CV characteristics of MOS and MIM.

[Explanation of symbols]

21 Insulating substrate Thin film transistor for 23 pixels 24 auxiliary capacity 30 gate electrode 31 Semiconductor layer 32-channel area 33 Source area 34 drain region 37 Storage capacitor semiconductor layer 51,111,112,113 Gate insulating film that is a dielectric layer 54 Metal electrode 82 Pixel electrodes that make up display elements 102, 103 resist mask 114 oxide film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 617U F term (reference) 2H092 JA23 JA49 JB68 KA07 MA06 5C094 AA42 AA43 BA03 BA43 CA19 EA04 EA07 5F110 AA09 AA26 BB02 BB04 CC02 DD02 DD13 EE06 EE44 FF02 FF07 FF09 FF22 FF29 FF30 GG02 GG13 GG25 GG32.

Claims (8)

[Claims] 1. A substrate, a plurality of display elements arranged in a matrix on the substrate, a plurality of thin film transistors connected to the plurality of display elements, and an auxiliary capacitor electrically connected to the display element. A semiconductor layer; a dielectric layer formed on the auxiliary capacitance semiconductor layer; and a metal electrode formed on the dielectric layer. The auxiliary capacitance semiconductor layer, the dielectric layer, and the metal electrode assist the semiconductor layer. In the flat-panel display device forming a capacitor, the thin film transistor includes a channel region, and a semiconductor layer having a source region and a drain region into which impurity ions are respectively sandwiched sandwiching the channel region, and the auxiliary capacitance semiconductor layer is provided with the semiconductor layer. Impurity ions of approximately the same concentration as the source region and the drain region of the thin film transistor are implanted in the same step, and the dielectric layer is Flat display device which is a sex condition. 2. The plane according to claim 1, wherein the concentration of impurity ions implanted into the source region and the drain region of the thin film transistor and the auxiliary capacitance semiconductor layer is 1 × 10 ²⁰ atoms / cm ³ or more. Display device. 3. The dielectric layer is formed by laminating on a semiconductor layer, the layer on the semiconductor side is in an intrinsic state, and the layer on the metal electrode side contains carbon of 1 × 10 ²⁰ atoms / cm ³ or more. The flat panel display device according to claim 1 or 2. 4. A substrate, a plurality of display elements arranged in a matrix on the substrate, a semiconductor layer formed on the substrate, a gate insulating film of a dielectric layer formed on the semiconductor layer, and In a flat display device including a plurality of thin film transistors formed of a gate electrode of a metal electrode formed on the dielectric layer and connected to the plurality of display elements, a source region and a drain region of the thin film transistor are implanted. The concentration of impurity ions is 1 × 10 ²⁰ ato
ms / cm ³ or more, the dielectric layer is formed by stacking on the semiconductor layer, the semiconductor side layer is in an intrinsic state, and the metal electrode side layer is 1 × 10 ²⁰
A flat display device characterized by containing carbon of atoms / cm ³ or more. 5. A thin film transistor formed on a substrate, a display element connected to the thin film transistor, and an auxiliary capacitance semiconductor layer electrically connected to the display element,
A dielectric layer formed on the auxiliary capacitance semiconductor layer and a metal electrode formed on the dielectric layer. An auxiliary capacitance is formed by the auxiliary capacitance semiconductor layer, the dielectric layer, and the metal electrode. In the method of manufacturing a flat panel display device, the step of simultaneously forming a semiconductor layer of the thin film transistor and the auxiliary capacitance semiconductor layer on the substrate, covering a portion that will be a channel region of the thin film transistor, and a source of the thin film transistor. A region, a drain region, and a resist mask having a shape that exposes the entire surface of the auxiliary capacitance semiconductor layer on the semiconductor layer; A step of implanting impurity ions on the entire surface of the capacitive semiconductor layer, and a step of removing the resist mask A step of forming the dielectric layer so as to cover the semiconductor layer of the thin film transistor and the auxiliary capacitance semiconductor layer; and forming a metal layer on the dielectric layer and patterning the metal layer to form a thin film of the thin film transistor. A step of forming a metal electrode facing the gate electrode and the auxiliary capacitance semiconductor layer, and a method of manufacturing a flat panel display device. 6. The step of removing the resist mask includes the steps of dry ashing the resist mask until the auxiliary capacitance semiconductor layer is not exposed, and removing the remaining resist mask by wet etching. The method for manufacturing a flat panel display device according to claim 5, wherein 7. The method for manufacturing a flat panel display device according to claim 5, further comprising the step of oxidizing the surface of the semiconductor layer of the thin film transistor to form an oxide film. 8. A plurality of display elements arranged in a matrix on a substrate, a semiconductor layer formed on the substrate, a gate insulating film of a dielectric layer formed on the semiconductor layer, and the dielectric layer. A method of manufacturing a flat display device, comprising: a plurality of thin film transistors formed of a gate electrode of a metal electrode formed above and connected to the plurality of display elements, wherein a semiconductor layer of the thin film transistor is formed on the substrate. A step of forming a resist mask on the semiconductor layer, the resist mask having a shape that covers a portion of the thin film transistor that becomes a channel region and exposes the entire surface of the source region and the drain region of the thin film transistor; and via the resist mask, Implanting impurity ions into the source region and the drain region of the thin film transistor, and using the resist mask A step of removing, a step of oxidizing the surface of the semiconductor layer of the thin film transistor to form an oxide film, a step of forming the dielectric layer so as to cover the oxide film, and a metal layer on the dielectric layer. And forming a gate electrode of the thin film transistor by patterning the metal layer to form a gate electrode of the thin film transistor.