JP2001125510A - Active matrix type el display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure which solves the problems of a shading film shielding a thin film transistor from light and which has a high function as an active matrix type display device. SOLUTION: The active matrix type EL display device has the following features. A thin film transistor including a source region 108, a drain region 111, a channel forming region 109, a gate insulating film 104 on the channel region, and a gate electrode 105 on the gate insulating film are formed on a substrate 101, and a resin film is formed on the thin film transistor to form a flat surface above the thin film transistor. A pixel electrode is formed above the resin film and connected to either the source region or the drain region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure which can be used for a flat panel display represented by an active matrix type liquid crystal display device or an EL type display device.

[0002]

2. Description of the Related Art Conventionally, an active matrix type liquid crystal display device has been known as a flat panel display. This has a configuration in which a switching thin film transistor is arranged in each of a large number of pixels arranged in a matrix, and electric charges flowing into and out of each pixel electrode are controlled by the thin film transistors.

In such a configuration, it is necessary to arrange a light shielding means so that light does not enter the thin film transistor arranged in the pixel region.

At present, a metal film is used as a light shielding means from the viewpoint of impurity diffusion and stability. In general, the light-shielding means of the thin-film transistor is also arranged as a black matrix that covers an edge area around the pixel electrode.

In such a configuration, the following problems occur. First, as a first problem, there is a problem that a capacitance is formed between the light-shielding film and the thin film transistor, which adversely affects the operation of the thin film transistor.

As a second problem, since the light-shielding film is generally formed on a substrate having irregularities, there is a problem that the light-shielding function cannot be sufficiently obtained due to the irregularities.

[0007] The problem of the light blocking function can be similarly applied to a black matrix arranged so as to overlap the edge of a pixel.

[0008]

SUMMARY OF THE INVENTION An object of the invention disclosed in this specification is to solve the problem relating to a light shielding film for shielding a thin film transistor and to provide a structure having a high function as an active matrix type display device. I do.

[0009]

According to the structure of the invention disclosed in this specification, a thin film transistor whose output is connected to a pixel electrode, an interlayer insulating film made of a resin material disposed above the thin film transistor, and A light-shielding film for shielding the thin-film transistor disposed on the interlayer insulating film,
It is characterized by having.

In another aspect of the invention, an interlayer insulating film made of a resin material is formed on the thin film transistor, and a light shielding film for shielding the thin film transistor from light is formed on the interlayer insulating film made of the resin material. It is characterized by the following.

According to another aspect of the present invention, there is provided a semiconductor device having a plurality of pixel electrodes arranged in a matrix and a black matrix covering at least a part of an edge region of the pixel electrode, wherein the black matrix is made of a resin material. Characterized by being disposed on an interlayer insulating film.

[0012]

[Embodiment 1] FIGS. 1 and 2 show a manufacturing process of a pixel portion of an active matrix type liquid crystal display device shown in this embodiment.

First, as shown in FIG.
A silicon oxide film 102 is formed as a base film to a thickness of 3000.degree.

Next, an amorphous silicon film (not shown) is formed as a starting film of a thin film semiconductor constituting an active layer of the thin film transistor. Here, an amorphous silicon film (not shown) is formed to a thickness of 500 ° by a plasma CVD method.

And heat treatment or laser light irradiation,
Alternatively, the amorphous silicon film is crystallized using a method in which heat treatment and laser light irradiation are combined to obtain a crystalline silicon film (not shown).

The crystalline silicon film (not shown) is patterned to obtain an active layer 103 of the thin film transistor.

Next, as shown in FIG.
Oxide film 104 covering the gate and functioning as a gate insulating film
Is formed to a thickness of 1000 ° by a plasma CVD method. Thus, the state shown in FIG.

Next, an aluminum film (not shown) containing scandium at 0.1% by weight is formed to a thickness of 4000 ° by sputtering. This aluminum film forms a gate electrode later.

After forming the aluminum film, a dense anodic oxide film (not shown) is formed on the surface to a thickness of 100 °. This anodic oxidation is performed by using an ethylene glycol solution containing tartaric acid of 3% neutralized with aqueous ammonia as an electrolytic solution, and using an aluminum film in the electrolytic solution as an anode.

Further, a resist mask (not shown) is arranged and patterning is performed. By performing this patterning, a gate electrode 105 is formed.

After the formation of the gate electrode 105, anodic oxidation is performed again with a resist mask (not shown) remaining.
This anodization is performed by using a 3% oxalic acid aqueous solution as the electrolytic solution.

In this anodic oxidation, anodic oxidation is selectively performed only on the side surfaces of gate electrode 105 because a resist mask (not shown) remains. The anodic oxide film formed in this step has a porous structure.

Thus, an anodic oxide film 106 having a porous film quality is formed on the side surface of the gate electrode 105.

This porous anodic oxide film can be grown to a thickness of about several μm. The control of the growth distance can be controlled by the anodic oxidation time.

Here, the thickness of the anodic oxide film 106 is set to 600
0 °.

Next, the ethylene glycol solution containing 3% tartaric acid is again neutralized with aqueous ammonia, and anodized with an electrolytic solution. In this anodic oxidation step, since the electrolytic solution penetrates into the porous anodic oxide film 106, a dense anodic oxide film 107 is formed around the gate electrode 105 as shown by 107.

The thickness of the dense anodic oxide film 107 is 50
0 °. The main role of the dense anodic oxide film 107 is to cover the surface of the gate electrode so that hillocks and whiskers are not generated in a later step.

Further, when the porous anodic oxide film 106 is removed later, it also has a role of protecting the gate electrode 105 so that the gate electrode 105 is not etched at the same time.

Further, it also has a role of contributing to the formation of an offset gate region formed by using the porous anodic oxide film 106 later as a mask.

Thus, the state shown in FIG. 1B is obtained.

In this state, impurity ions are implanted. Here, P (phosphorus) ions are implanted in order to obtain an N-channel thin film transistor.

When impurity ions are implanted in the state shown in FIG. 1B, impurity ions are selectively implanted into regions 108 and 111. That is, the regions 108 and 111 become high concentration impurity regions.

The region 109 immediately below the gate electrode 105
The gate electrode 105 serves as a mask, and impurity ions are not implanted. This region 109 becomes a channel formation region.

In the region 110, the porous anodic oxide film 105 and the dense anodic oxide film 107 serve as a mask, so that impurity ions are not implanted. The region indicated by 107 serves as an offset gate region that does not function as a source / drain region and does not function as a channel formation region.

The offset gate region functions particularly to reduce the intensity of the electric field formed between the channel forming region and the drain region. By the presence of the offset gate region, the OFF current value of the thin film transistor can be reduced, and the deterioration can be further suppressed.

Thus, the source region indicated by 108,
A channel formation region indicated by 109, an offset gate region indicated by 110, and a drain region indicated by 111 are formed in a self-aligned manner.

After the implantation of the impurity ions is completed, the porous anodic oxide film 106 is selectively removed. Then, an annealing process by laser light irradiation is performed. At this time, the vicinity of the interface between the high-concentration impurity region and the offset gate region can be irradiated with laser light, so that the junction portion damaged by the implantation of the impurity ions can be sufficiently annealed.

After obtaining the state shown in FIG. 1B, a silicon oxide film 112 is formed to a thickness of 2000 ° as a first interlayer insulating film. As the first interlayer insulating film, a silicon nitride film or a stacked film of a silicon oxide film and a silicon nitride film may be used.

Next, a contact hole is formed in the first interlayer insulating film 112, and a source electrode 113 which contacts a source region of the thin film transistor is formed. Thus, the state shown in FIG. 1C is obtained.

Next, a second interlayer insulating film 114 is formed using a transparent polyimide resin or acrylic resin. The surface of the interlayer insulating film 114 made of this resin material is made flat. Thus, the state shown in FIG. 1D is obtained.

Next, as shown in FIG. 2A, a light-shielding film 115 made of a chromium film also serving as a light-shielding film of a thin-film transistor and a black matrix is formed, and then patterned to form a light-shielding film 115.

Here, a resin material constituting the second interlayer insulating film 114 is selected to have a relative dielectric constant of 3 or less. Further, the film thickness is increased to several μm. In addition, in the case of a resin material, even if the thickness is increased, the manufacturing process time does not become long, which is useful for such a purpose.

With this configuration, it is possible to suppress the formation of a capacitance between the light-shielding film 115 made of chromium and the thin film transistor thereunder.

When the second interlayer insulating film 114 is made of a resin material, its surface can be easily flattened, so that the problem of light leakage due to unevenness can be suppressed.

After the state shown in FIG. 2A is obtained, a resin material, or a silicon oxide film or a silicon nitride film is formed as third interlayer insulating film 116. Here, the third interlayer insulating film 116
The same resin material as that of the second interlayer insulating film 114 is used.

The use of a resin material as the third interlayer insulating film can solve the problem that a capacitance is formed between a pixel electrode to be formed later and the light shielding film 115, and furthermore, a pixel electrode is formed. This is useful in that the underlayer can be flattened.

Thus, the state shown in FIG. 2B is obtained. Next, a contact hole is formed, an ITO electrode for forming a pixel electrode is formed by a sputtering method, and further, patterning is performed to form a pixel electrode 117.

Thus, the structure shown in FIG. 2C is completed. The structure shown in FIG. 2C can reduce the relative dielectric constant of the interlayer insulating film disposed between the thin film transistor (particularly, the source electrode 113) and the light-shielding film (and / or the black matrix) 115, and can reduce the thickness thereof. Can be made thicker, so that formation of unnecessary capacitance can be suppressed.

It is industrially easy to increase the thickness of the resin film as described above, and the process time does not increase, so that the above-described configuration can be realized.

[Embodiment 2] The present embodiment is characterized in that the configuration shown in Embodiment 1 is further improved to provide a configuration having higher reliability.

As described above, a metal material such as chromium is used for the light shielding film and the black matrix. However, in consideration of long-term reliability, there is a concern about the problem of diffusion of impurities from the metal material and the problem of short-circuit between other electrodes and wiring.

In particular, in the state shown in FIG. 2C, when a pinhole is present in the interlayer insulating film 116, a short circuit occurs between the light shielding film (or black matrix) 115 and the pixel electrode 117. That is a problem.

In order to eliminate the influence of the pinhole existing in the interlayer insulating film 116, a method of forming the interlayer insulating film 116 into a special multilayer film can be considered.

However, such a method is not preferable because it causes an increase in production steps and an increase in production cost.

Therefore, in the structure shown in the present embodiment, an anodic oxidizable material is used as a light shielding film for shielding the thin film transistor from the structure shown in the first embodiment, and an anodic oxide film is formed on the surface.

Aluminum or tantalum can be used as the anodizable material. Particularly when aluminum is used, the anodic oxidation film used in industrial products such as aluminum sashes can be used, so that the anodic oxide film can be colored black or a dark color close thereto, so that it is suitable as a light shielding film. It becomes something.

FIG. 3 shows an outline of the manufacturing process of this embodiment.
First, according to the steps shown in FIGS.
The state shown in (D) is obtained. Next, a light-shielding film 115 is formed as shown in FIG.

Here, aluminum is used for the light shielding film 115. Then, by performing anodic oxidation in the electrolytic solution, an anodic oxide film 301 is formed on the surface of the light shielding film 115 as shown in FIG.

In the figure, the light shielding film 301 is described as a light shielding film for shielding the thin film transistor. However, it usually extends further to form a black matrix.

Once the state shown in FIG.
3B, the third interlayer insulating film 116 is formed using a silicon oxide film, a silicon nitride film, or a resin material.

Further, as shown in FIG.
17 is formed of ITO. Here, the interlayer insulating film 11
Even if a pinhole exists in 6, a short circuit between the pixel electrode 117 and the light-shielding film 115 can be prevented due to the presence of the anodic oxide film 301.

Since the anodic oxide film 115 is chemically stable, it is possible to suppress diffusion of impurities from the light-shielding film 115 to the surroundings in consideration of long-term reliability. .

[Embodiment 3] This embodiment relates to a configuration in which the aperture ratio of a pixel is further increased. In general, it is desired that the pixel has a configuration in which the aperture ratio is increased as much as possible. In order to increase the aperture ratio of the pixel, it is necessary to arrange the pixel electrode in an area as large as possible.

However, when the pixel electrode overlaps the thin film transistor or the wiring, a capacitance is formed therebetween, so that there is generally a great limitation in this point.

The present embodiment provides a configuration in which the problem that this capacitance is formed is reduced.

FIG. 4 shows a manufacturing process of the structure shown in this embodiment. 4A and 4B are the same as the steps shown in FIGS. 3A and 3B.

First, as shown in FIG. 4A, a light-shielding film 115 made of aluminum is formed. Then, an anodic oxide film indicated by 301 is formed on the surface of the light shielding film 115.

Further, as shown in FIG. 4B, a third interlayer insulating film 116 is formed. Here, the interlayer insulating film 116 is formed using a resin material.

Then, as shown in FIG. 4C, the pixel electrode 117 is formed of ITO. Here, the pixel electrode 117
Overlap the thin film transistor. By doing so, the aperture ratio of the pixel can be maximized.

In the case where the structure as shown in FIG. 4C is employed, the dielectric constant of the interlayer insulating films 114 and 116 is low (meaning lower than that of a silicon oxide film or a silicon nitride film).
Since the resin material can be used and its thickness can be further increased, the above-mentioned problem of the capacity can be reduced.

The area of the pixel electrode can be increased, and the aperture ratio of the pixel can be increased.

[Embodiment 4] In the above embodiment, the structure of the thin film transistor is of the top gate type. In this embodiment, a manufacturing process of a bottom gate type thin film transistor in which the gate electrode is on the substrate side of the active layer will be described.

FIG. 5 shows a manufacturing process of this embodiment. First, as shown in FIG. 5A, a silicon oxide film 202 is formed over a glass substrate 201 as a base film by a sputtering method. Then 2
A gate electrode indicated by 03 is formed of aluminum.

At this time, scandium is added to aluminum.
0.18% by weight. In addition, efforts are made to reduce the concentration of other impurities as much as possible. These contrivances are to suppress the formation of protrusions called hillocks and whiskers due to abnormal growth of aluminum in a later step.

Next, a silicon oxide film 204 functioning as a gate insulating film is formed to a thickness of 500 ° by a plasma CVD method.

Further, an unillustrated amorphous silicon film (which will later become a crystalline silicon film 205) serving as a starting film constituting an active layer of the thin film transistor is formed by a plasma CVD method. A low pressure thermal CVD method may be used in addition to the plasma CVD method. Next, the amorphous silicon film (not shown) is crystallized by irradiating a laser beam. Thus, a crystalline silicon film 205 is obtained. Thus, the state shown in FIG.

After obtaining the state shown in FIG. 5A, the active layer 206 is formed by patterning. Next, a silicon nitride film (not shown) is formed, and exposure is performed from the back surface side of the substrate 201 using the gate electrode 203, thereby forming a mask pattern 207 made of a silicon nitride film. The formation of the mask pattern 207 is performed as follows.

First, a resist mask pattern is formed by exposure from the back side of the substrate 201 using the pattern of the gate electrode 203. Further, ashing is performed to retreat the pattern of the resist mask. Then, a pattern 207 is obtained by patterning the silicon nitride film using the recessed resist mask pattern (not shown). Thus, the state shown in FIG. 5B is obtained.

Next, doping of impurities using the mask pattern 207 is performed. Here, the dopant is P
(Phosphorus) is used, and a plasma doping method is used as a doping means. In this step, 208 and 2
The region 09 is doped with P. The region 210 is not doped with P.

After the end of the doping, laser light irradiation is performed from above to activate the region to be doped and anneal damage due to the impact of dopant ions. Thus, a region 208 is formed as a source region as shown in FIG. Further, 209 is formed as a drain region. Also, 210 defines a channel region.

Next, a first interlayer insulating film 2 made of a silicon nitride film
As 11, the silicon nitride film was formed by plasma CVD to 20
A film is formed to a thickness of 00 °. As the first interlayer insulating film used here, in addition to the silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked film of a silicon oxide film and a silicon nitride film (either of which may be stacked first). Can be used.

Next, a contact hole for the source region 208 is formed in the first interlayer insulating film 211, and a source electrode 212 for contacting the source region 208 is formed.
Thus, the state shown in FIG. 5C is obtained.

Next, as shown in FIG. 5D, a second interlayer insulating film 213 having a flat surface is formed of a transparent polyimide resin or acrylic resin. As a film forming method, for example, a spin coating method may be adopted.

Next, a chromium film is formed on the surface of the second interlayer insulating film 213 and is patterned to form a light-shielding film 214 which also functions as a light-shielding film of a thin film transistor and a black matrix. Then, as the third interlayer insulating film 215, the same resin material film as the second interlayer insulating film 213 is formed.

A contact hole reaching the drain region 209 is formed in the first to third interlayer insulating films 211, 213, and 215 by etching. Next, an ITO film is formed on the surface of the third interlayer insulating film 215 and is patterned to form a pixel electrode 216 in contact with the drain region 209 of the thin film transistor.

Through the above steps, the thin film transistor shown in FIG. 5D is completed.

[0087]

By utilizing the invention disclosed in this specification, an effective arrangement of a light-shielding film can be obtained in a pixel structure of an active matrix type display device. Thus, a structure having high functions as an active matrix display device can be obtained. The invention disclosed in this specification can be applied to not only an active matrix type liquid crystal display device but also an active matrix type EL type display device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a pixel portion of an active matrix circuit.

FIG. 2 is a diagram showing a manufacturing process of a pixel portion of an active matrix circuit.

FIG. 3 is a diagram showing a manufacturing process of a pixel portion of an active matrix circuit.

FIG. 4 is a diagram showing a manufacturing process of a pixel portion of an active matrix circuit.

FIG. 5 is a diagram showing a manufacturing process of a pixel portion of an active matrix circuit.

[Explanation of symbols]

Reference Signs List 101 glass substrate (or quartz substrate) 102 base film (silicon oxide film) 103 active layer (crystalline silicon film) 104 gate insulating film (silicon oxide film) 105 gate electrode (aluminum electrode) 106 porous anodic oxide film 107 Dense anodic oxide film 108 Source region (high concentration impurity region) 109 Channel formation region 110 Offset gate region 111 Drain region (high concentration impurity region) 112 First interlayer insulating film (silicon oxide film or silicon nitride film) 113 Source electrode 114 Second interlayer insulating film (resin material) 115 Light shielding film (black matrix) 116 Third interlayer insulating film (for example, resin material) 117 Pixel electrode (ITO electrode)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05B 33/14 H05B 33/26 Z 33/22 G02F 1/136 500 33/26 H01L 29/78 619A

Claims (10)

[Claims] 1. A thin film transistor including a source region, a drain region, a channel forming region, a gate insulating film on the channel region, and a gate electrode on the gate insulating film is provided above a substrate, and a resin is provided above the thin film transistor. An active matrix, wherein a flat surface is provided above the thin film transistor by providing a film, and a pixel electrode is provided above the resin film and connected to one of the source region and the drain region. Type EL display device. 2. A thin film transistor including a source region, a drain region, a channel forming region, a gate insulating film on the channel region, and a gate electrode on the gate insulating film is provided above the substrate, and the thin film transistor is transparent above the thin film transistor. By providing a resin film, a flat surface is provided above the thin film transistor, and a pixel electrode is provided above the transparent resin film and connected to one of the source region and the drain region. Active matrix type EL display device. 3. A thin film transistor including a source region, a drain region, a channel forming region, a gate insulating film on the channel region, and a gate electrode on the gate insulating film, is provided above the substrate, wherein the silicon nitride film or the silicon oxide is provided. A film is provided above the gate electrode; a resin film is provided on the silicon nitride or silicon oxide film to provide a flat surface above the thin film transistor; a pixel electrode is provided above the resin film; An active matrix EL display device connected to one of the source region and the drain region. 4. A thin film transistor including a gate electrode, a gate insulating film on the gate electrode, a source region, a drain region, and a channel forming region on the gate insulating film,
A flat surface is provided above the thin film transistor by providing a resin film above the thin film transistor provided above the substrate, and a pixel electrode is provided above the resin film, and one of the source region and the drain region is provided. An active matrix EL display device characterized by being connected to a device. 5. A thin film transistor including a gate electrode, a gate insulating film on the gate electrode, a source region, a drain region, and a channel forming region on the gate insulating film,
A transparent resin film is provided above the thin film transistor to provide a flat surface above the thin film transistor; a pixel electrode is provided above the transparent resin film; the source region and the drain region An active matrix EL display device is connected to one of the above. 6. A thin film transistor including a gate electrode, a gate insulating film on the gate electrode, a source region, a drain region, and a channel forming region on the gate insulating film,
A silicon nitride film or a silicon oxide film is provided above the substrate, the silicon nitride film or the silicon oxide film is provided above the channel formation region, and a resin film is provided on the silicon nitride or the silicon oxide film to provide a flat surface above the thin film transistor An active matrix type EL display device, wherein a pixel electrode is provided above the resin film and connected to one of the source region and the drain region. 7. The active matrix type EL display device according to claim 1, wherein the resin film is a polyimide resin film. 8. An active matrix EL display device according to claim 1, wherein said transparent resin film is a polyimide resin film. 9. The active matrix EL display device according to claim 2, wherein the resin film is an acrylic resin film. 10. The active matrix EL display device according to claim 2, wherein the transparent resin film is a polyimide resin film.