JPH01155025U

JPH01155025U -

Info

Publication number: JPH01155025U
Application number: JP4538788U
Authority: JP
Priority date: 1988-04-04
Filing date: 1988-04-04
Publication date: 1989-10-25
Anticipated expiration: 2003-04-04
Also published as: JPH082656Y2

Description

[Brief explanation of drawings]

第１図は、本実施例のＴＦＴパネルの一部の平
面図、第２図ａは、本実施例のＴＦＴパネル内の
欠陥補償用薄膜トランジスタの断面図、第２図ｂ
は、本実施例のＴＦＴパネル内の画素表示用薄膜
トランジスタの断面図、第３図は、本実施例のＴ
ＦＴパネルの製造工程図、第４図は、本実施例の
ＴＦＴパネルの一部分の概念図、第５図は、従来
のＴＦＴパネルの一部分の概念図である。１３，２１′……ゲート電極、１４……ゲート
絶縁膜、１４′……絶縁膜、１５，１５′……半
導体膜、１７，１７′……ドレイン電極、１８，
１８′……ソース電極、１９，１９′……透明絶
縁膜、２０，２３，２７―３６……画素電極、２
１……遮光金属膜、２２……補償ライン、２７ａ
〜３６ａ……画素表示用薄膜トランジスタ、２３
ｂ，２７ｂ，２９ｂ，３１ｂ，３３ｂ，３５ｂ…
…欠陥補償用薄膜トランジスタ。 FIG. 1 is a plan view of a part of the TFT panel of this embodiment, FIG. 2a is a sectional view of a thin film transistor for defect compensation in the TFT panel of this embodiment, and FIG. 2b
is a cross-sectional view of the pixel display thin film transistor in the TFT panel of this example, and FIG. 3 is a cross-sectional view of the TFT panel of this example.
FIG. 4 is a conceptual diagram of a part of the TFT panel of this embodiment, and FIG. 5 is a conceptual diagram of a part of a conventional TFT panel. 13, 21'... Gate electrode, 14... Gate insulating film, 14'... Insulating film, 15, 15'... Semiconductor film, 17, 17'... Drain electrode, 18,
18'... Source electrode, 19, 19'... Transparent insulating film, 20, 23, 27-36... Pixel electrode, 2
1... Light-shielding metal film, 22... Compensation line, 27a
~36a...Thin film transistor for pixel display, 23
b, 27b, 29b, 31b, 33b, 35b...
...Thin film transistor for defect compensation.

Claims

[Scope of utility model registration request]

A plurality of first electrodes arranged in a row direction on an insulating substrate.
a gate line, a plurality of drain lines arranged in the column direction, a gate electrode provided at each intersection of the first gate line and the drain line, a gate electrode connected to the first gate line, and a drain electrode connected to the first gate line. a plurality of first thin film transistors connected to the drain electrode;
A plurality of pixel electrodes arranged at locations surrounded by the first gate line and the drain line and each connected to a source electrode of the first thin film transistor, and a pixel in which the drain electrode and the source electrode are adjacent to each other. A thin film transistor panel comprising: a plurality of second thin film transistors each having a gate electrode connected to the electrode and supplied with a signal for defect compensation of the first thin film transistor.