JPS61106979U - - Google Patents
Info
- Publication number
- JPS61106979U JPS61106979U JP19325184U JP19325184U JPS61106979U JP S61106979 U JPS61106979 U JP S61106979U JP 19325184 U JP19325184 U JP 19325184U JP 19325184 U JP19325184 U JP 19325184U JP S61106979 U JPS61106979 U JP S61106979U
- Authority
- JP
- Japan
- Prior art keywords
- line
- drain
- insulating film
- display device
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011229 interlayer Substances 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
第１図は本考案の表示装置の一実施例の要部断
面図、第２図ａ，ｂは従来装置の平面図、及びそ
の―線断面図、第３図ａ，ｂは既提案装置の
平面図、及びその′―′線断面図、第４図は
既提案装置に於ける要部の平面パターン図、第５
図は本考案装置の要部の断面図である。
１０……第１のガラス基板、１１……透明電極
、１４……ドレインライン、１６……ゲートライ
ン、１７……ゲート電極、１９，１９′……バイ
パスライン、１００……層間絶縁膜。
Fig. 1 is a cross-sectional view of essential parts of an embodiment of the display device of the present invention, Fig. 2 a and b are a plan view of a conventional device and a cross-sectional view taken along the line 1-2, and Fig. 3 a and b are of the previously proposed device. A plan view and a sectional view along the line '--', Figure 4 is a plane pattern diagram of the main parts of the proposed device, Figure 5 is
The figure is a sectional view of the main parts of the device of the present invention. 10...First glass substrate, 11...Transparent electrode, 14...Drain line, 16...Gate line, 17...Gate electrode, 19, 19'...Bypass line, 100...Interlayer insulating film.
Claims (1)
ートライン上に層間絶縁膜を介して並列配置され
た複数本のドレインラインとが交差し、このマト
リクス状の各交差点にてＦＥＴからなるスイツチ
ングトランジスタを構成してなり、該各トランジ
スタのソース側に表示セグメント電極を結合した
表示装置に於いて、ゲートラインとの間で絶縁膜
を介して独立した状態で上記ドレインラインに沿
つて潜在した短冊状のバイパスラインを備え、該
バイパスラインと上記ドレインラインとを互いに
結合した事を特徴とする表示装置。 A plurality of gate lines arranged in parallel intersect with a plurality of drain lines arranged in parallel on the gate lines via an interlayer insulating film, and a switching transistor consisting of an FET is formed at each intersection in the matrix. In a display device in which a display segment electrode is connected to the source side of each transistor, a rectangular strip hidden along the drain line is separated from the gate line with an insulating film interposed therebetween. 1. A display device comprising a bypass line, the bypass line and the drain line being coupled to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19325184U JPH059707Y2 (en) | 1984-12-19 | 1984-12-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19325184U JPH059707Y2 (en) | 1984-12-19 | 1984-12-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61106979U true JPS61106979U (en) | 1986-07-07 |
| JPH059707Y2 JPH059707Y2 (en) | 1993-03-10 |
Family
ID=30750670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19325184U Expired - Lifetime JPH059707Y2 (en) | 1984-12-19 | 1984-12-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH059707Y2 (en) |
-
1984
- 1984-12-19 JP JP19325184U patent/JPH059707Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH059707Y2 (en) | 1993-03-10 |
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