JPS61155881U - - Google Patents
Info
- Publication number
- JPS61155881U JPS61155881U JP3922385U JP3922385U JPS61155881U JP S61155881 U JPS61155881 U JP S61155881U JP 3922385 U JP3922385 U JP 3922385U JP 3922385 U JP3922385 U JP 3922385U JP S61155881 U JPS61155881 U JP S61155881U
- Authority
- JP
- Japan
- Prior art keywords
- line
- gate
- display device
- drain
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011229 interlayer Substances 0.000 claims 1
- 239000011159 matrix material Substances 0.000 claims 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
第1図は本考案の表示装置の一実施例の要部部
分平面図、第2図a、及びbは従来装置の要部平
面図、及びそのX―X線断面図、第3図はライン
パターンの平面膜式図、第4図は既提案装置の要
部部分平面図である。
14……ドレインライン、15……ソース電極
、16……ゲートライン、17……ゲート電極、
19′,19″……迂回バイパスライン。
FIG. 1 is a plan view of a main part of an embodiment of the display device of the present invention, FIGS. FIG. 4 is a plan view of the main part of the proposed device. 14...Drain line, 15...Source electrode, 16...Gate line, 17...Gate electrode,
19', 19''...Detour bypass line.
Claims (1)
ートライン上に層間絶縁膜を介して並列配置され
た複数本のドレインラインとが交差し、このマト
リクス状の各交差点にてFETからなるスイツチ
ングトランジスタを構成してなり、該各トランジ
スタのソース側に表示セグメント電極を結合した
表示装置に於いて、ドレインラインと交差するゲ
ートライン箇所をゲートラインの延在線上から外
れて振り分けられた2本の迂回バイパスラインに
て構成した事を特徴とする表示装置。 A plurality of gate lines arranged in parallel intersect with a plurality of drain lines arranged in parallel on the gate lines via an interlayer insulating film, and a switching transistor consisting of an FET is formed at each intersection in the matrix. In a display device in which a display segment electrode is connected to the source side of each transistor, two detours are distributed so that the gate line intersects with the drain line is separated from the extension line of the gate line. A display device characterized by being configured with a bypass line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3922385U JPS61155881U (en) | 1985-03-19 | 1985-03-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3922385U JPS61155881U (en) | 1985-03-19 | 1985-03-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61155881U true JPS61155881U (en) | 1986-09-27 |
Family
ID=30546978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3922385U Pending JPS61155881U (en) | 1985-03-19 | 1985-03-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61155881U (en) |
-
1985
- 1985-03-19 JP JP3922385U patent/JPS61155881U/ja active Pending
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