JPS6136825U - display device - Google Patents
display deviceInfo
- Publication number
- JPS6136825U JPS6136825U JP12111384U JP12111384U JPS6136825U JP S6136825 U JPS6136825 U JP S6136825U JP 12111384 U JP12111384 U JP 12111384U JP 12111384 U JP12111384 U JP 12111384U JP S6136825 U JPS6136825 U JP S6136825U
- Authority
- JP
- Japan
- Prior art keywords
- line
- display device
- parallel
- switching transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の表示装置の一実施例部分平面図、第2
図a, bは夫々本考案装置の要部断面図、第3図a,
bは従来の表示装置の部分平面図及び断面図、第4図
はラインパターンの平面図である。
11・・・透明iEi、1 3・・・アモルファスシリ
コン膜、14−・・ドレインライン、15・・・ソース
電極、11・・・ゲートライン、16′・・・補助ゲー
トライン、17・・・ゲート電極、19・・・ブリッジ
部。FIG. 1 is a partial plan view of one embodiment of the display device of the present invention, and FIG.
Figures a and b are sectional views of the main parts of the device of the present invention, and Figures 3a and 3 are respectively
4b is a partial plan view and a sectional view of a conventional display device, and FIG. 4 is a plan view of a line pattern. DESCRIPTION OF SYMBOLS 11... Transparent iEi, 1 3... Amorphous silicon film, 14-... Drain line, 15... Source electrode, 11... Gate line, 16'... Auxiliary gate line, 17... Gate electrode, 19... bridge part.
Claims (1)
ン上に層間絶縁膜を介して並列配置ざれた複数本のドレ
インラインとが交差し、このマトリクス状の各交差点(
とてFETからなるスイッチングトランジスタを構成し
てなり、該トランジスタのソース側に表示セグメント電
極を結合した表示装置に於いて、上記スイッチングトラ
ンジスタ箇所のゲートライン又はドレ才ンラインに対し
て独立に並列配置された補助ライン、及び該補助ライン
の両端部とゲートライン又はドレインラインとを絶縁膜
を介して連結するブリッジ部とを設けた事を特徴とする
表示装置。A plurality of gate lines arranged in parallel intersect with a plurality of drain lines arranged in parallel on the gate lines via an interlayer insulating film, and each intersection point (
In a display device comprising a switching transistor consisting of a FET and a display segment electrode coupled to the source side of the transistor, the switching transistor is arranged independently in parallel with the gate line or drain line of the switching transistor location. 1. A display device comprising: an auxiliary line; and a bridge portion connecting both ends of the auxiliary line to a gate line or a drain line via an insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12111384U JPS6136825U (en) | 1984-08-07 | 1984-08-07 | display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12111384U JPS6136825U (en) | 1984-08-07 | 1984-08-07 | display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6136825U true JPS6136825U (en) | 1986-03-07 |
Family
ID=30679910
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12111384U Pending JPS6136825U (en) | 1984-08-07 | 1984-08-07 | display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6136825U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63228189A (en) * | 1987-03-17 | 1988-09-22 | 富士通株式会社 | Active matrix type display device |
-
1984
- 1984-08-07 JP JP12111384U patent/JPS6136825U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63228189A (en) * | 1987-03-17 | 1988-09-22 | 富士通株式会社 | Active matrix type display device |
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