JPS5991756U - lcd matrix panel - Google Patents

lcd matrix panel

Info

Publication number
JPS5991756U
JPS5991756U JP18875082U JP18875082U JPS5991756U JP S5991756 U JPS5991756 U JP S5991756U JP 18875082 U JP18875082 U JP 18875082U JP 18875082 U JP18875082 U JP 18875082U JP S5991756 U JPS5991756 U JP S5991756U
Authority
JP
Japan
Prior art keywords
matrix panel
lcd matrix
line
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18875082U
Other languages
Japanese (ja)
Other versions
JPH0514521Y2 (en
Inventor
武貞　肇
光洋 山崎
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP18875082U priority Critical patent/JPS5991756U/en
Publication of JPS5991756U publication Critical patent/JPS5991756U/en
Application granted granted Critical
Publication of JPH0514521Y2 publication Critical patent/JPH0514521Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、液晶マトリクスパネルの一般的構成を示す分
解斜視図、第２図はその一部回路図、第３図は具体的構
造を示す断面図、第３Ａ図及び第３Ｂ図はそれぞれ第３
図におけるＡ−Ａ’断面図、Ｂ−Ｂ’断面図、第４Ａ図
及び第４Ｂ図は本考案実施例を説明するための断面図で
ある。 １．５・・・・・・透明基板、２・・・・・・共通電極
、３・・・・・・液晶層、６・・・・・・表示電極、７
・・・・・・絶縁層、８・・・・・・絶縁酸化被膜、Ｘ
・・・・・・ゲートライン、Ｙ・・・・・・ドレインラ
イン。FIG. 1 is an exploded perspective view showing the general configuration of a liquid crystal matrix panel, FIG. 2 is a partial circuit diagram thereof, FIG. 3 is a sectional view showing the specific structure, and FIGS. 3A and 3B are respective diagrams. 3
The AA' sectional view, the BB' sectional view, FIGS. 4A and 4B in the figures are sectional views for explaining the embodiment of the present invention. 1.5...Transparent substrate, 2...Common electrode, 3...Liquid crystal layer, 6...Display electrode, 7
...Insulating layer, 8...Insulating oxide film, X
...Gate line, Y...Drain line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板上に形成されその酸化物が絶縁体を形成するゲ
ートライン、該ゲートラインと絶縁層を介して形成され
たドレインライン（若しくはソースライン）を有する電
界効果型トランジスタにおいて、上記ゲートラインの少
なくとも上記ドレインラインとの交差点に位置する部分
は、その表面゛　が絶縁酸化被膜にて被覆されたことを
特徴とする電界効界型トランジスタ。In a field effect transistor having a gate line formed on an insulating substrate and whose oxide forms an insulator, and a drain line (or source line) formed through the gate line and an insulating layer, at least A field effect transistor characterized in that the surface of the portion located at the intersection with the drain line is covered with an insulating oxide film.
JP18875082U 1982-12-13 1982-12-13 lcd matrix panel Granted JPS5991756U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18875082U JPS5991756U (en) 1982-12-13 1982-12-13 lcd matrix panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18875082U JPS5991756U (en) 1982-12-13 1982-12-13 lcd matrix panel

Publications (2)

Publication Number Publication Date
JPS5991756U true JPS5991756U (en) 1984-06-21
JPH0514521Y2 JPH0514521Y2 (en) 1993-04-19

Family

ID=30407113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18875082U Granted JPS5991756U (en) 1982-12-13 1982-12-13 lcd matrix panel

Country Status (1)

Country Link
JP (1) JPS5991756U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6086863A (en) * 1983-10-19 1985-05-16 Fujitsu Ltd Insulating gate type thin film transistor
JPS63164A (en) * 1986-06-19 1988-01-05 Matsushita Electric Ind Co Ltd Thin-film transistor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54157272A (en) * 1978-05-31 1979-12-12 Siemens Ag Method of producing conductive path laminated crossing
JPS5638008A (en) * 1979-09-06 1981-04-13 Canon Inc Display cell
JPS5665176A (en) * 1979-10-31 1981-06-02 Canon Kk Display device
JPS5669864A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Thin-film transistor
JPS57153427A (en) * 1981-03-17 1982-09-22 Fujitsu Ltd Manufacture of thin film device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54157272A (en) * 1978-05-31 1979-12-12 Siemens Ag Method of producing conductive path laminated crossing
JPS5638008A (en) * 1979-09-06 1981-04-13 Canon Inc Display cell
JPS5665176A (en) * 1979-10-31 1981-06-02 Canon Kk Display device
JPS5669864A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Thin-film transistor
JPS57153427A (en) * 1981-03-17 1982-09-22 Fujitsu Ltd Manufacture of thin film device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6086863A (en) * 1983-10-19 1985-05-16 Fujitsu Ltd Insulating gate type thin film transistor
JPS63164A (en) * 1986-06-19 1988-01-05 Matsushita Electric Ind Co Ltd Thin-film transistor

Also Published As

Publication number Publication date
JPH0514521Y2 (en) 1993-04-19

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