JPH0514521Y2 - - Google Patents

Description

[Detailed description of the invention] Industrial application field This invention is a field-effect transistor (FET)
This invention relates to a liquid crystal matrix panel using. Recently, a gate line (scanning line) has been added to one substrate of an LCD panel.
A large number of drain lines (signal lines) are insulated from each other and crossed at right angles, and a thin film FET (TFT) is placed as a switching element at the intersection of each of these lines, which is opened and closed to connect to the display electrode provided at each intersection. Attempts have been made to develop a liquid crystal matrix panel that displays images on a television or the like by applying a signal to drive the liquid crystal in this area.
The present invention relates to, for example, a liquid crystal matrix panel using such a switching element.

Prior Art Figure 1 shows the overall structure of a matrix panel using FETs as switching elements, in which 1 is a front glass transparent substrate, 2 is a common electrode made of an ITO film coated on the entire inner surface of this transparent substrate 1, and 3 is a liquid crystal display. Layer 4 is a spacer made of glass frit, resin, etc. and also serves as a sealant. 5 is a back glass transparent substrate with multiple gate lines X on its inner surface.
and a drain line Y (which may also be a source line; the same applies hereinafter) are insulated from each other and arranged orthogonally. 6, 6... are amorphous silicon FETs at each intersection of gate line X and drain line Y
The display electrodes are connected through the . It takes
The circuit configuration of one liquid crystal cell in a matrix panel using an FET array is shown in Figure 2. C is a capacitor inserted in parallel with the liquid crystal panel (LCD) as an additional volume.

Figure 3, Figure 3A and Figure 3B show one
The specific structure of the FET is shown, and X and Y are the aforementioned gate line and drain line, which are separated by an insulating layer 7. A gate line X and a drain line Y are formed on the surface of the glass substrate 5. The gate G of the FET is formed on the gate line X. An amorphous silicon layer (AS) is formed above the gate G with an insulating layer 7 interposed therebetween.
A source S and a drain D are formed at both end portions so as to sandwich the gate G. A part of the drain line Y also serves as the drain D. Reference numeral 6 denotes the display electrode described above, which is connected to the source S. Normally, the gate line X and display electrode 6 are formed of an ITO film, and the source S and drain line Y are formed of aluminum. Further, the insulating layer 7
A vaporized film of silicon nitride Si ₃ N ₄ formed by CVD method is used.

In an FET with such a structure, as shown in FIG. 3B, the gate line X and the drain line Y
There is a portion where they intersect only through the insulating layer 7. The number of intersections is the same as the number of pixels, for example,
Assuming that the number of gate lines and drain lines Y are 220 and 240, respectively, the number reaches 52,800. Therefore, a small number of these intersections are shot through pinholes formed in the insulating layer 7. Even if this short is only one point, two defective lines, one gate line and one drain line, will be generated, resulting in a large defect in the display.

Purpose of the invention The present invention aims to improve the reliability of these device structures by preventing shoots caused by pinholes that occur at the intersections of gate lines and drain lines, and also prevents shoots in the FET itself, thereby improving the reliability of these device structures. The purpose is to prevent display defects.

Structure of the invention In the liquid crystal matrix panel of the invention, in the display electrode substrate, the gate line and the gate electrode are integrally provided with the same metal material, and a self-oxidation film is formed on the entire surface of the gate line and the gate electrode. Further, the insulating layer is provided on the self-oxidized film, and the drain line is provided to intersect with the gate line via the self-oxidized film and the insulating layer.

Example Figure 4A and Figure 4B are Figures 3A and 3B.
This is a sectional view of an embodiment of the present invention corresponding to the figure, and the same parts as in the figure are given the same numbers. 8 is
A self-oxidation film formed on the entire surface of gate G and gate line
is made of the same material aluminum, its oxide is alumina Al ₂ O ₃ . This self-oxidized film 8 is formed by thermal oxidation or anodic oxidation of the gate line X made of aluminum. After the gate line X and the gate G have been subjected to oxidation treatment, an insulating layer 7 is formed over the surface by vapor deposition of silicon nitride, and a drain line Y is further deposited on this insulating layer 7. In this way, the self-oxidized film 8 and the insulating layer 7 are formed separately by oxidation and plasma CVD, respectively. Therefore,
The gate insulating layer on the gate electrode G of the FET consists of a self-oxidized film 8 made of alumina, which is a surface insulating film of the gate electrode G, and an insulating layer 7 made of silicon nitride or the like.
It will be composed of a laminate of Furthermore, the interlayer insulating film at the intersection between the gate line Become. Therefore, even if a pinhole were to occur in the insulating layer 7 at the intersection of the gate line can be set to almost zero. Of course, at the FET position, as is clear from FIG. 4A, the gate electrode G, the amorphous silicon layer which is the semiconductor layer, and the drain electrode D
Alternatively, since the laminate of the self-oxidized film 8 and the insulating layer 7 is interposed between the source electrode S and the source electrode S, the probability of inter-electrode shorts due to pinholes can be drastically reduced, as in the case of the line intersection described above.

Effects of the invention The liquid crystal matrix panel of the invention can eliminate short-circuit accidents caused by pinholes between transistors and electrodes at line intersections on the display electrode substrate, thereby eliminating display operation defects in the liquid crystal matrix panel. Ru. Particularly in liquid crystal matrix panels in which the number of transistors and intersections is on the order of several million, the effect of contributing to improving the yield is significant.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view showing the general structure of a liquid crystal matrix panel, FIG. 2 is a partial circuit diagram thereof, FIG. 3 is a cross-sectional view showing the specific structure, and FIGS. 3A and 3B are respective diagrams. A-A' sectional view in Figure 3,
BB' sectional view, FIGS. 4A and 4B are sectional views for explaining the embodiment of the present invention. 1, 5...Transparent substrate, 2...Common electrode, 3...
Liquid crystal layer, 6... Display electrode, 7... Insulating layer, 8...
Self-oxidized film, X...gate line, Y...drain line.

Claims (1)

[Claims for Utility Model Registration] A liquid crystal in which liquid crystal is filled between a display electrode substrate in which a large number of display electrodes are arranged in rows and columns together with transistors for supplying potential thereto, and a common electrode substrate facing the substrate. In the matrix panel, the display electrode substrate includes an insulating substrate, a gate line formed on the insulating substrate, a gate electrode of a transistor connected to the gate line, and an entire surface covering the gate line and gate electrode. an insulating layer formed on the insulating layer, a semiconductor layer of a transistor formed on the insulating layer, a source electrode formed on the semiconductor layer, a drain line crossing the gate line through the insulating layer, and the drain A drain electrode connected to the line and a display electrode connected to the source electrode are provided, the gate line and the gate electrode are integrally formed of the same metal material, and a self-oxidation film is formed on the entire surface of the gate line and the gate electrode. The liquid crystal is further provided with the insulating layer on the self-oxidized film, and the drain line is provided to intersect with the gate line via the self-oxidized film and the insulating layer. matrix panel.