JPH04265945A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH04265945A
JPH04265945A JP3027529A JP2752991A JPH04265945A JP H04265945 A JPH04265945 A JP H04265945A JP 3027529 A JP3027529 A JP 3027529A JP 2752991 A JP2752991 A JP 2752991A JP H04265945 A JPH04265945 A JP H04265945A
Authority
JP
Japan
Prior art keywords
electrode
picture element
active matrix
element electrode
additional capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3027529A
Other languages
Japanese (ja)
Other versions
JP2702294B2 (en
Inventor
Hisafumi Saito
尚史 斉藤
Hirohisa Tanaka
田仲 広久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2752991A priority Critical patent/JP2702294B2/en
Publication of JPH04265945A publication Critical patent/JPH04265945A/en
Application granted granted Critical
Publication of JP2702294B2 publication Critical patent/JP2702294B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To offer the active matrix substrate which is so structured that short circuit is hardly generated between a picture element electrode and an additional capacity electrode which constitute additional capacitance. CONSTITUTION:The picture element electrode 19 is formed on a protection film 20 formed on the entire surface of a substrate 11 while covering a TFT 1 and then connected to the drain electrode 18 of the TFT 1 electrically through a contact hole 26. In this constitution, the picture element electrode 19 is not formed on a gate insulating film 15 where a source bus conductor is formed, and the gate insulating film 15 and protection film 20 are sandwiched between the additional capacitance electrode 14 and picture element electrode 19 which constitute additional capacitance. The picture element electrode and additional capacitance electrode are hardly short-circuited and the picture element electrode can be formed without being restrained by the source bus conductor. The area of the picture element electrode can be increased.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、液晶等の表示媒体と組
み合わせてアクティブマトリクス表示装置を構成するた
めのアクティブマトリクス基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate for constructing an active matrix display device in combination with a display medium such as a liquid crystal.

【0002】0002

【従来の技術】従来より、液晶等の表示媒体を用いた表
示装置には、アクティブマトリクス方式が用いられてい
る。図5に従来のアクティブマトリクス表示装置の等価
回路図を示す。この表示装置では、絶縁性基板上にゲー
トバス配線5が等間隔で平行に配され、ゲートバス配線
5に直交してソースバス配線4が平行に配されている。 ゲートバス配線5とソースバス配線4とのそれぞれの交
差点近傍には、薄膜トランジスタ(以下では「TFT」
と称する)1が形成されている。TFT1のゲート電極
はゲートバス配線5に接続され、TFT1のソース電極
はソースバス配線4に接続されている。TFT1のドレ
イン電極には、絵素電極と対向電極との間に形成される
絵素容量2と、絵素電極と付加容量電極との間に形成さ
れる付加容量3とが接続されている。
2. Description of the Related Art Conventionally, an active matrix method has been used in display devices using display media such as liquid crystals. FIG. 5 shows an equivalent circuit diagram of a conventional active matrix display device. In this display device, gate bus lines 5 are arranged in parallel at regular intervals on an insulating substrate, and source bus lines 4 are arranged in parallel orthogonal to the gate bus lines 5. A thin film transistor (hereinafter referred to as "TFT") is located near each intersection of the gate bus wiring 5 and the source bus wiring 4.
) 1 is formed. The gate electrode of the TFT 1 is connected to the gate bus wiring 5, and the source electrode of the TFT 1 is connected to the source bus wiring 4. A picture element capacitor 2 formed between the picture element electrode and the counter electrode, and an additional capacitor 3 formed between the picture element electrode and the additional capacitor electrode are connected to the drain electrode of the TFT 1.

【0003】この表示装置では、1本のゲートバス配線
5が選択されると、その選択されたゲートバス配線5接
続されたTFT1がオン状態となる。オン状態となった
TFT1にはソースバス配線4から映像信号が入力され
、この映像信号は絵素容量2及び付加容量3に蓄積され
、表示が行われる。付加容量3は、絵素容量2に蓄積さ
れた映像信号を、次の映像信号が入力されるまでの1フ
レームの間、保持する機能を果たしている。
In this display device, when one gate bus line 5 is selected, the TFT 1 connected to the selected gate bus line 5 is turned on. A video signal is input from the source bus wiring 4 to the TFT 1 in the on state, and this video signal is stored in the pixel capacitor 2 and the additional capacitor 3 for display. The additional capacitor 3 functions to hold the video signal stored in the pixel capacitor 2 for one frame until the next video signal is input.

【0004】このような表示装置に用いられるアクティ
ブマトリクス基板の平面図を図6に示す。図6のA−A
線に沿ったこの表示装置の断面図を図7に示す。この表
示装置では、絶縁性基板11上にスパッタリング法等及
びエッチング法を用いて、ゲートバス配線5及び付加容
量配線13が形成され、ゲートバス配線5上にはゲート
バス配線5の上面を陽極酸化することによって陽極酸化
膜25が形成されている。付加容量配線13上には透明
導電膜からなる付加容量電極14がパターン形成されて
いる。更に、付加容量電極14及び陽極酸化膜25を覆
って基板11上の全面に、ゲート絶縁膜15が形成され
ている。ゲート絶縁膜15上のゲートバス配線5上方に
は、アモルファスシリコン(以下では「a−Si」と称
する)からなるチャネル層16が形成され、チャネル層
16上の両側方にはソース電極17及びドレイン電極1
8がそれぞれ形成されている。以上によりTFT1が完
成する。
FIG. 6 shows a plan view of an active matrix substrate used in such a display device. A-A in Figure 6
A cross-sectional view of this display device along a line is shown in FIG. In this display device, a gate bus wiring 5 and an additional capacitance wiring 13 are formed on an insulating substrate 11 using a sputtering method or the like and an etching method, and the upper surface of the gate bus wiring 5 is anodized on the gate bus wiring 5. By doing so, an anodic oxide film 25 is formed. On the additional capacitor wiring 13, an additional capacitor electrode 14 made of a transparent conductive film is patterned. Furthermore, a gate insulating film 15 is formed on the entire surface of the substrate 11, covering the additional capacitance electrode 14 and the anodic oxide film 25. A channel layer 16 made of amorphous silicon (hereinafter referred to as "a-Si") is formed above the gate bus wiring 5 on the gate insulating film 15, and a source electrode 17 and a drain are formed on both sides of the channel layer 16. Electrode 1
8 are formed respectively. Through the above steps, TFT1 is completed.

【0005】ゲート絶縁膜15上には、透明導電膜から
なる絵素電極19がパターン形成され、絵素電極19の
端部はドレイン電極18に電気的に接続されている。ま
た、絵素電極19は付加容量電極14上にも重畳され、
絵素電極19と付加容量電極14との間には、前述のゲ
ート絶縁膜15が挟まれている。付加容量3は付加容量
電極14と絵素電極19との間に形成されている。TF
T1、絵素電極19及び付加容量3を覆って基板11上
の全面に、保護膜20が形成されている。基板11に対
向する基板21上には対向電極22及び遮光用のブラッ
クストライプ23が形成されている。基板11及び21
の間には液晶層24が封入され、液晶表示装置が完成す
る。
A picture element electrode 19 made of a transparent conductive film is patterned on the gate insulating film 15 , and the end of the picture element electrode 19 is electrically connected to the drain electrode 18 . Further, the picture element electrode 19 is also superimposed on the additional capacitance electrode 14,
The aforementioned gate insulating film 15 is sandwiched between the picture element electrode 19 and the additional capacitance electrode 14. The additional capacitor 3 is formed between the additional capacitor electrode 14 and the picture element electrode 19. TF
A protective film 20 is formed on the entire surface of the substrate 11, covering T1, the picture element electrode 19, and the additional capacitor 3. A counter electrode 22 and a black stripe 23 for shielding light are formed on a substrate 21 facing the substrate 11. Substrates 11 and 21
A liquid crystal layer 24 is sealed in between, completing a liquid crystal display device.

【0006】[0006]

【発明が解決しようとする課題】このような従来の表示
装置に用いられるアクティブマトリクス基板では、絵素
電極19と付加容量電極14との間に短絡が生じること
がある。このような短絡が生じると、表示画面には絵素
欠陥が生じることとなる。
In the active matrix substrate used in such a conventional display device, a short circuit may occur between the picture element electrode 19 and the additional capacitance electrode 14. If such a short circuit occurs, pixel defects will occur on the display screen.

【0007】本発明は、このような問題点を解決するも
のであり、本発明の目的は、付加容量を構成する絵素電
極と付加容量電極との間に、短絡が生じ難い構造を有す
るアクティブマトリクス基板を提供することである。
The present invention solves these problems, and an object of the present invention is to provide an active electrode having a structure in which short circuits are unlikely to occur between the picture element electrode and the additional capacitor electrode that constitute the additional capacitor. An object of the present invention is to provide a matrix substrate.

【0008】[0008]

【課題を解決するための手段】本発明のアクティブマト
リクス基板は、絶縁性基板上にマトリクス状に配列され
た絵素電極と、該絵素電極との間で付加容量を形成する
ための付加容量電極と、該付加容量電極間を電気的に接
続する付加容量配線と、を有するアクティブマトリクス
基板であって、該絵素電極と該付加容量電極との間に第
1の絶縁膜及び第2の絶縁膜が挟まれており、そのこと
によって上記目的が達成される。
[Means for Solving the Problems] The active matrix substrate of the present invention has pixel electrodes arranged in a matrix on an insulating substrate and an additional capacitor for forming an additional capacitance between the pixel electrodes. An active matrix substrate having an electrode and an additional capacitor wiring electrically connecting the additional capacitor electrodes, the active matrix substrate having a first insulating film and a second insulating film between the picture element electrode and the additional capacitor electrode. An insulating film is sandwiched therebetween, thereby achieving the above object.

【0009】また、更に薄膜トランジスタを備え、前記
第1の絶縁膜が該薄膜トランジスタのゲート絶縁膜であ
る構成とすることもできる。
[0009] Furthermore, the device may further include a thin film transistor, and the first insulating film may be a gate insulating film of the thin film transistor.

【0010】また、薄膜トランジスタ上を覆う保護膜を
更に有し、前記第2の絶縁膜が該保護膜であり、前記絵
素電極が該第2の絶縁膜に形成されたコンタクトホール
を介して該薄膜トランジスタに接続されている構成とす
ることができる。
[0010] The invention further includes a protective film covering the thin film transistor, wherein the second insulating film is the protective film, and the picture element electrode is connected to the thin film transistor through a contact hole formed in the second insulating film. It can be configured to be connected to a thin film transistor.

【0011】[0011]

【実施例】本発明の実施例について以下に説明する。[Examples] Examples of the present invention will be described below.

【0012】図1に本発明のアクティブマトリクス基板
の一実施例を用いた液晶表示装置の断面図を示す。図1
の表示装置を構成するアクティブマトリクス基板の平面
図を図2に示す。図1は図2のアクティブマトリクス基
板を用いた表示装置の、図2に於けるA−A線に沿った
断面図である。また、図2のアクティブマトリクス基板
の製造工程を図3(a)〜(d)に示す。
FIG. 1 shows a sectional view of a liquid crystal display device using an embodiment of the active matrix substrate of the present invention. Figure 1
FIG. 2 shows a plan view of the active matrix substrate constituting the display device. FIG. 1 is a cross-sectional view of a display device using the active matrix substrate of FIG. 2, taken along line A--A in FIG. Moreover, the manufacturing process of the active matrix substrate of FIG. 2 is shown in FIGS. 3(a) to 3(d).

【0013】本実施例を製造工程に従って説明する。ま
ず、ガラス等の絶縁性基板11上にスパッタリング法を
用いてTa、Mo等の金属膜を形成し、この金属膜をエ
ッチングすることにより、ゲートバス配線5及び付加容
量配線13を形成した。ゲートバス配線5の一部が、後
に形成されるTFT1のゲート電極として機能する。ゲ
ートバス配線5上にはゲートバス配線5の表面を陽極酸
化することによって陽極酸化膜25が形成されている。 次に、付加容量配線13上にはITO(Indiumt
in oxide)等の透明導電膜からなる付加容量電
極14がパターン形成される(図3(a))。
This embodiment will be explained according to the manufacturing process. First, a metal film such as Ta or Mo was formed on an insulating substrate 11 made of glass or the like using a sputtering method, and this metal film was etched to form the gate bus wiring 5 and the additional capacitance wiring 13. A part of the gate bus wiring 5 functions as a gate electrode of the TFT 1 that will be formed later. An anodic oxide film 25 is formed on the gate bus line 5 by anodizing the surface of the gate bus line 5. Next, ITO (Indium) is placed on the additional capacitance wiring 13.
An additional capacitance electrode 14 made of a transparent conductive film such as (in oxide) is patterned (FIG. 3(a)).

【0014】更に、付加容量電極14及び陽極酸化膜2
5を覆って基板11上の全面に、第1の絶縁膜であるゲ
ート絶縁膜15が形成される。ゲート絶縁膜15上のゲ
ートバス配線5上方には、a−Siからなるチャネル層
16が形成され(図3(b))、チャネル層16上の両
側方にはソース電極17及びドレイン電極18がそれぞ
れ形成される(図3(c))。ソース電極17及びドレ
イン電極18はソースバス配線と同時にパターン形成さ
れる。ソース電極17、ドレイン電極18及びソースバ
ス配線は、Ta、Mo、Al等の金属からなる。以上に
よりTFT1が完成する。
Furthermore, additional capacitance electrode 14 and anodic oxide film 2
A gate insulating film 15, which is a first insulating film, is formed on the entire surface of the substrate 11, covering the gate insulating film 5. A channel layer 16 made of a-Si is formed above the gate bus wiring 5 on the gate insulating film 15 (FIG. 3(b)), and a source electrode 17 and a drain electrode 18 are formed on both sides of the channel layer 16. (FIG. 3(c)). The source electrode 17 and drain electrode 18 are patterned simultaneously with the source bus wiring. The source electrode 17, drain electrode 18, and source bus wiring are made of metal such as Ta, Mo, and Al. Through the above steps, TFT1 is completed.

【0015】次に、TFT1が形成された基板11上の
全面に、第2の絶縁膜である保護膜20が形成される。 次に、ドレイン電極18上の保護膜20にはコンタクト
ホール26が形成される。更に、保護膜20上の全面に
透明導電膜が形成され、図2に示す絵素電極19の形状
にパターン化される(図3(d))。本実施例では、絵
素電極19は前述の図6の従来例より大きな面積で形成
されており、図2に示すように、絵素電極19とソース
バス配線4とは互いに平面視では接するように形成され
ている。このように絵素電極19の面積を大きくしても
、絵素電極19とソースバス配線4とは保護膜20によ
って電気的に離隔されている。また、絵素電極19の端
部はコンタクトホール26上にも形成され、従って、絵
素電極19はドレイン電極18にコンタクトホール26
を介して電気的に接続されている。更に、絵素電極19
は付加容量電極14上にも重畳され、絵素電極19と付
加容量電極14との間には、前述のゲート絶縁膜15及
び保護膜20が挟まれている。付加容量3は付加容量電
極14と絵素電極19との間に形成されている。以上に
より、本実施例のアクティブマトリクス基板が完成する
Next, a protective film 20, which is a second insulating film, is formed over the entire surface of the substrate 11 on which the TFT 1 is formed. Next, a contact hole 26 is formed in the protective film 20 on the drain electrode 18. Furthermore, a transparent conductive film is formed on the entire surface of the protective film 20, and is patterned into the shape of the picture element electrode 19 shown in FIG. 2 (FIG. 3(d)). In this embodiment, the picture element electrode 19 is formed to have a larger area than the conventional example shown in FIG. 6, and as shown in FIG. is formed. Even if the area of the picture element electrode 19 is increased in this way, the picture element electrode 19 and the source bus wiring 4 are electrically separated by the protective film 20. Further, the end of the picture element electrode 19 is also formed on the contact hole 26, so that the picture element electrode 19 is connected to the drain electrode 18 through the contact hole 26.
electrically connected via. Furthermore, the picture element electrode 19
is also superimposed on the additional capacitor electrode 14, and the aforementioned gate insulating film 15 and protective film 20 are sandwiched between the picture element electrode 19 and the additional capacitor electrode 14. The additional capacitor 3 is formed between the additional capacitor electrode 14 and the picture element electrode 19. Through the above steps, the active matrix substrate of this example is completed.

【0016】基板11に対向する基板21上には対向電
極22及び遮光用のブラックストライプ23が形成され
ている。基板11及び21の間には液晶層24が封入さ
れ、液晶表示装置が完成する。この液晶表示装置の等価
回路図は、前述の図5と同様である。
A counter electrode 22 and a black stripe 23 for shielding light are formed on a substrate 21 facing the substrate 11. A liquid crystal layer 24 is sealed between the substrates 11 and 21, and a liquid crystal display device is completed. The equivalent circuit diagram of this liquid crystal display device is similar to FIG. 5 described above.

【0017】本実施例のアクティブマトリクス基板では
、絵素電極19と付加容量電極14との間に、ゲート絶
縁膜15及び保護膜20の2層の絶縁膜が形成されてい
るので、絵素電極19と付加容量電極14との間に短絡
が生じ難くなっている。
In the active matrix substrate of this embodiment, two insulating films, the gate insulating film 15 and the protective film 20, are formed between the pixel electrode 19 and the additional capacitance electrode 14, so that the pixel electrode 19 and the additional capacitance electrode 14 are less likely to be short-circuited.

【0018】また、本実施例では、図2に示すように、
絵素電極19はソースバス配線4に平面視で接するよう
に形成されているので、本実施例のアクティブマトリク
ス基板を用いた表示装置の開口率は大きくなっている。 図4に本実施例のアクティブマトリクス基板を用いた表
示装置の開口部を示す。比較のために、前述の図6の基
板を用いた表示装置の開口部を図8に示す。図6及び図
8に於て、斜線を施していない部分が開口部である。そ
れぞれの開口部は対向基板21上に形成されたブラック
ストライプ23の開口部によって規定される。ブラック
ストライプ23の開口部は、アクティブマトリクス基板
及び対向基板の貼り合わせの際の位置ずれを考慮して、
絵素電極19より小さく形成されている。本実施例では
絵素電極19の面積が大きいので、ブラックストライプ
23の開口部の面積も大きくすることができる。図6及
び図8の比較から、本実施例のアクティブマトリクス基
板を用いた表示装置の開口率は、従来の表示装置の開口
率より大きくなっていることが分かる。
Furthermore, in this embodiment, as shown in FIG.
Since the picture element electrode 19 is formed so as to be in contact with the source bus wiring 4 in plan view, the aperture ratio of the display device using the active matrix substrate of this embodiment is large. FIG. 4 shows an opening of a display device using the active matrix substrate of this example. For comparison, FIG. 8 shows an opening of a display device using the substrate of FIG. 6 described above. In FIGS. 6 and 8, the portions that are not shaded are openings. Each opening is defined by the opening of the black stripe 23 formed on the counter substrate 21. The opening of the black stripe 23 is designed in consideration of positional deviation when bonding the active matrix substrate and the counter substrate.
It is formed smaller than the picture element electrode 19. In this embodiment, since the area of the picture element electrode 19 is large, the area of the opening of the black stripe 23 can also be made large. From a comparison between FIGS. 6 and 8, it can be seen that the aperture ratio of the display device using the active matrix substrate of this example is larger than that of the conventional display device.

【0019】[0019]

【発明の効果】本発明のアクティブマトリクス基板では
、付加容量を構成する絵素電極と付加容量電極との間に
2層の絶縁膜が形成されているので、絵素電極と付加容
量電極との間に短絡が生じ難くなる。
[Effects of the Invention] In the active matrix substrate of the present invention, a two-layer insulating film is formed between the picture element electrode and the additional capacitance electrode that constitute the additional capacitance, so the connection between the picture element electrode and the additional capacitance electrode is Short circuits are less likely to occur between the two.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明のアクティブマトリクス基板の一実施例
を用いたアクティブマトリクス表示装置の断面図である
FIG. 1 is a sectional view of an active matrix display device using an embodiment of an active matrix substrate of the present invention.

【図2】図1のアクティブマトリクス表示装置を構成す
るアクティブマトリクス基板の平面図である。
FIG. 2 is a plan view of an active matrix substrate constituting the active matrix display device of FIG. 1;

【図3】図2のアクティブマトリクス基板の製造工程を
示す図である。
3 is a diagram showing a manufacturing process of the active matrix substrate of FIG. 2. FIG.

【図4】図2のアクティブマトリクス基板を用いたアク
ティブマトリクス表示装置の開口部を示す平面図である
4 is a plan view showing an opening of an active matrix display device using the active matrix substrate of FIG. 2; FIG.

【図5】本発明及び従来のアクティブマトリクス表示装
置の等価回路図である。
FIG. 5 is an equivalent circuit diagram of the present invention and a conventional active matrix display device.

【図6】従来のアクティブマトリクス基板の平面図であ
る。
FIG. 6 is a plan view of a conventional active matrix substrate.

【図7】図6のアクティブマトリクス基板を用いたアク
ティブマトリクス表示装置の断面図である。
7 is a sectional view of an active matrix display device using the active matrix substrate of FIG. 6. FIG.

【図8】図7のアクティブマトリクス表示装置の開口部
を示す平面図である。
8 is a plan view showing an opening of the active matrix display device of FIG. 7. FIG.

【符号の説明】[Explanation of symbols]

1  TFT 2  絵素容量 3  付加容量 4  ソースバス配線 5  ゲートバス配線 11,21  絶縁性基板 13  付加容量配線 14  付加容量電極 15  ゲート絶縁膜 16  チャネル層 17  ソース電極 18  ドレイン電極 19  絵素電極 20  保護膜 22  対向電極 23  ブラックストライプ 24  液晶層 1 TFT 2 Pixel capacity 3 Additional capacity 4 Source bus wiring 5 Gate bus wiring 11, 21 Insulating substrate 13 Additional capacitance wiring 14 Additional capacitance electrode 15 Gate insulation film 16 Channel layer 17 Source electrode 18 Drain electrode 19 Picture element electrode 20 Protective film 22 Counter electrode 23 Black stripe 24 Liquid crystal layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板上にマトリクス状に配列された
絵素電極と、該絵素電極との間で付加容量を形成するた
めの付加容量電極と、該付加容量電極間を電気的に接続
する付加容量配線と、を有するアクティブマトリクス基
板であって、該絵素電極と該付加容量電極との間に第1
の絶縁膜及び第2の絶縁膜が挟まれているアクティブマ
トリクス基板。
1. Picture element electrodes arranged in a matrix on an insulating substrate, an additional capacitance electrode for forming an additional capacitance between the picture element electrodes, and an electrical connection between the additional capacitance electrodes. an active matrix substrate having an additional capacitance wiring for connection, the active matrix substrate having a first connection between the picture element electrode and the additional capacitance electrode;
an active matrix substrate in which an insulating film and a second insulating film are sandwiched.
JP2752991A 1991-02-21 1991-02-21 Active matrix substrate Expired - Lifetime JP2702294B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2752991A JP2702294B2 (en) 1991-02-21 1991-02-21 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2752991A JP2702294B2 (en) 1991-02-21 1991-02-21 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPH04265945A true JPH04265945A (en) 1992-09-22
JP2702294B2 JP2702294B2 (en) 1998-01-21

Family

ID=12223647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2752991A Expired - Lifetime JP2702294B2 (en) 1991-02-21 1991-02-21 Active matrix substrate

Country Status (1)

Country Link
JP (1) JP2702294B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483082A (en) * 1992-12-28 1996-01-09 Fujitsu Limited Thin film transistor matrix device
US5621556A (en) * 1994-04-28 1997-04-15 Xerox Corporation Method of manufacturing active matrix LCD using five masks
US5682211A (en) * 1994-04-28 1997-10-28 Xerox Corporation Integrated dark matrix for an active matrix liquid crystal display with pixel electrodes overlapping gate data lines
US5867242A (en) * 1994-04-28 1999-02-02 Xerox Corporation Electrically isolated pixel element in a low voltage activated active matrix liquid crystal display and method
US6310669B1 (en) 1997-05-26 2001-10-30 Mitsubishi Denki Kabushiki Kaisha TFT substrate having connecting line connect to bus lines through different contact holes
US7545449B2 (en) 2003-03-07 2009-06-09 Casio Computer Co., Ltd. Liquid crystal display device having auxiliary capacitive electrode
JP2009180981A (en) * 2008-01-31 2009-08-13 Mitsubishi Electric Corp Active matrix substrate, and manufacturing method therefor
JP2011186424A (en) * 2010-03-10 2011-09-22 Samsung Mobile Display Co Ltd Array substrate for liquid crystal display device and method for manufacturing the same
US8576346B2 (en) 2001-05-16 2013-11-05 Samsung Display Co., Ltd. Thin film transistor array substrate for liquid crystal display

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JPS58203486A (en) * 1982-05-24 1983-11-26 株式会社日立製作所 Display panel
JPS6097385A (en) * 1983-11-01 1985-05-31 セイコーインスツルメンツ株式会社 Thin film transistor substrate for liquid crystal display
JPH01140129A (en) * 1987-11-27 1989-06-01 Hitachi Ltd Liquid crystal display device and driving method thereof
JPH0210333A (en) * 1988-06-29 1990-01-16 Sharp Corp Active liquid crystal display device
JPH02151835A (en) * 1988-12-05 1990-06-11 Toshiba Corp Thin-film transistor array
JPH02250038A (en) * 1989-03-23 1990-10-05 Seiko Instr Inc Thin film transistor array

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Publication number Priority date Publication date Assignee Title
JPS58203486A (en) * 1982-05-24 1983-11-26 株式会社日立製作所 Display panel
JPS6097385A (en) * 1983-11-01 1985-05-31 セイコーインスツルメンツ株式会社 Thin film transistor substrate for liquid crystal display
JPH01140129A (en) * 1987-11-27 1989-06-01 Hitachi Ltd Liquid crystal display device and driving method thereof
JPH0210333A (en) * 1988-06-29 1990-01-16 Sharp Corp Active liquid crystal display device
JPH02151835A (en) * 1988-12-05 1990-06-11 Toshiba Corp Thin-film transistor array
JPH02250038A (en) * 1989-03-23 1990-10-05 Seiko Instr Inc Thin film transistor array

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483082A (en) * 1992-12-28 1996-01-09 Fujitsu Limited Thin film transistor matrix device
US5580796A (en) * 1992-12-28 1996-12-03 Fujitsu Limited Method for fabricating thin film transistor matrix device
US5621556A (en) * 1994-04-28 1997-04-15 Xerox Corporation Method of manufacturing active matrix LCD using five masks
US5682211A (en) * 1994-04-28 1997-10-28 Xerox Corporation Integrated dark matrix for an active matrix liquid crystal display with pixel electrodes overlapping gate data lines
US5867242A (en) * 1994-04-28 1999-02-02 Xerox Corporation Electrically isolated pixel element in a low voltage activated active matrix liquid crystal display and method
US6650378B2 (en) 1997-05-26 2003-11-18 Mitsubishi Denki Kabushiki Kaisha TFT array substrate and method of manufacturing the same and method of manufacturing liquid crystal display using the same
US6310669B1 (en) 1997-05-26 2001-10-30 Mitsubishi Denki Kabushiki Kaisha TFT substrate having connecting line connect to bus lines through different contact holes
US8576346B2 (en) 2001-05-16 2013-11-05 Samsung Display Co., Ltd. Thin film transistor array substrate for liquid crystal display
US8736780B2 (en) 2001-05-16 2014-05-27 Samsung Display Co., Ltd. Thin film transistor array substrate for liquid crystal display
US7545449B2 (en) 2003-03-07 2009-06-09 Casio Computer Co., Ltd. Liquid crystal display device having auxiliary capacitive electrode
JP2009180981A (en) * 2008-01-31 2009-08-13 Mitsubishi Electric Corp Active matrix substrate, and manufacturing method therefor
JP2011186424A (en) * 2010-03-10 2011-09-22 Samsung Mobile Display Co Ltd Array substrate for liquid crystal display device and method for manufacturing the same
TWI475643B (en) * 2010-03-10 2015-03-01 Samsung Display Co Ltd Array substrate of liquid crystal display and fabrication method thereof

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