JPH0820643B2 - Active matrix display - Google Patents

Description

The present invention relates to a large-sized active matrix display device having a thin film transistor.

(Prior art) A thin film transistor (hereinafter referred to as "TFT") on an insulating substrate.
The active matrix method, in which an array is formed and the pixel electrodes are driven via TFTs, is used in a display device using liquid crystal or the like. The active matrix system is often used especially in a display device which is large and performs high-density display, and has an advantage that it can be used in both a reflection type and a transmission type display device.

FIG. 7 shows an example of a conventional active matrix type liquid crystal display device. The TFT 42 is formed on the glass substrate 41, and the pixel electrode 43 is driven by the TFT 42. Picture element electrode 4
The liquid crystal 4 between the counter electrode 3 and the counter electrode 45 formed on the counter substrate 44.
A voltage is applied to 6 and a display is made.

Amorphous silicon (hereinafter "a-Si") is used for TFT.
), Polycrystalline silicon, Te, CdSe, etc. are used as semiconductor materials. FIG. 4 shows a plan view of a conventional TFT. In FIG. 4, the layers formed by superposition are hatched only on the periphery, and the inside is not hatched. FIG. 5 shows a sectional view taken along the line VV of FIG.

This TFT is manufactured as follows. Glass substrate 2
1 by the spattering method, Ta with a layer thickness of 3000 to 4000Å
Metal is deposited, and the gate bus wiring 23 is patterned by photolithography and etching. The gate electrode 22 is formed as a part of the gate bus line 23 and has a width larger than that of the gate bus line 23. Gate electrode
The surfaces of 22 and the gate bus wiring 23 are anodized to form an anodized film 24 that functions as a gate insulating film.

Layer thickness 2000-400 on the entire surface of substrate 21 by plasma CVD method
A gate insulating film 25 made of 0Å silicon nitride (hereinafter referred to as “SiN _X ”) is formed. Further, on the entire surface of the substrate, an a-Si (i) layer (layer thickness 150 to 1000, which will later become the semiconductor layer 26) is formed.
Å), and later becomes the etching stopper layer and protective film 27
SiN _X layers (layer thickness 100-2000Å) are deposited sequentially. next,
The SiN _X layer is patterned into a predetermined shape, and the protective film 27 is formed leaving only the upper part of the gate electrode 22.

An a-Si (n ⁺ ) layer (layer thickness of 300 to 2000) that covers the protective film 27 and is doped with P (phosphorus) to be a contact layer 28 later is formed.
Å) is deposited by the plasma CVD method. Next, the a-Si (i) layer and the n-type a-Si layer described above are patterned into a predetermined shape to form the semiconductor layer 26 and the contact layer 28. At this point, the contact layer 28 is connected on the protective film 27.

A metal layer of Mo, Ti, Al, etc. is 2000-1000 on the entire surface of this substrate.
The metal layer is deposited to a thickness of 0Å, and this metal layer is patterned by etching to form the source electrode 29 and the drain electrode.
31 is formed. At this time, the contact layer 28 is also simultaneously removed by etching on the protective film 27, and divided into a portion below the source electrode 29 and a portion below the drain electrode 31. The protective film 27 has resistance to this etching and is provided to protect the semiconductor layer 26. Next, an ITO film is deposited on the entire surface of the substrate by sputtering. This ITO film is patterned into a predetermined shape, and the pixel electrode 32
Is formed.

A large number of such TFTs are formed on the gate bus line 23 to form an active matrix substrate. The source bus line 30 is provided orthogonal to the gate bus line 23, and is connected to the source electrodes 29 of the respective TFTs arranged in a direction perpendicular to the direction of the gate bus line 23.

In an active matrix display device using such a TFT, scanning signals are sequentially input to the gate bus wiring 23,
An image signal is input to the corresponding source bus line 30 and the pixel electrode 32 is driven. The intersection of the gate bus wiring 23 and the source bus wiring 30 reaches 307200 in a display device having 480 × 640 picture elements, for example. If a leak occurs between the gate bus wiring 23 and the source bus wiring 30 even at one of the many intersections, a cross-shaped line defect having the leakage location as the intersection occurs. Such line defects significantly deteriorate the image quality and the yield of the display device. In the display device described above, in order to reliably insulate the gate bus wiring 23 and the source bus wiring 30, the anodic oxide film is used.
Ta metal capable of forming 24 is used for the gate bus line 23.

(Problems to be Solved by the Invention) However, since Ta metal has a large specific resistance, a scanning signal is attenuated in a large-sized display device having a long gate bus line 23 for fine display. Therefore, while the picture element located near the input portion of the scanning signal of the gate bus line 23 can obtain sufficient luminance, the picture element located far from the input portion cannot obtain sufficient luminance. Therefore, in the column of picture elements connected to the same gate bus line 23, the luminance gradient of the picture elements is generated from the side closer to the input portion of the scanning signal to the side farther.

In order to eliminate such a defect, it is considered that the gate bus wiring and the gate electrode have a two-layer structure as shown in FIG. The gate bus wiring 23 in FIG. 6 is made of Al, Al
-Si, Al-Si-Cu, Al-Ti, Al-Ti-Si, Al-Mg, Al-Mg-Si, A
Lower gate wiring made of l-Zn, Al-Mn, etc. with low specific resistance 3
3 and an upper gate wiring 34 made of Ta metal. According to such a configuration, the lower gate wiring 33 having a low specific resistance prevents the above-described luminance gradient from occurring.

In the gate bus wiring 23 having such a two-layer structure,
The width of the upper gate wiring 34 is 1 to 5 μm smaller than that of the lower gate wiring 33.
It is necessary that the upper gate wiring 34 completely covers the lower gate wiring 33. This is because the etching rate of Al or the like is much higher than the etching rate of Ta in the step of patterning the upper gate wiring 34 of Ta metal.

However, when the width of the gate bus line 23 is increased in this way, the area of the cross portion with the source bus line 30 is increased and a leak is likely to occur between them. Further, the area occupied by the gate electrode 22 and the gate bus line 23 on the active matrix substrate increases, and the aperture ratio of the display screen decreases. Therefore, the display screen becomes dark and it becomes difficult to display finely.

Further, in the resist stripping process after forming the lower gate wiring 33, hillocks are easily generated in the lower gate wiring 33.
The metal upper gate wiring 34 cannot completely cover the lower gate wiring 33. Therefore, the gate insulating film 25
Even if the intervening line is present, a new problem arises that a leak occurs between the gate bus line 23 and the source bus line 30.

The present invention solves the above-mentioned problems, and an object of the present invention is to provide an active gate gate wiring having a small specific resistance and less leakage between the source bus wiring and a large aperture ratio. A matrix display device is provided.

(Means for Solving the Problems) An active matrix display device according to the present invention has a pair of substrates, at least one of which has a light-transmitting property, and is formed on the inner surface of one of the pair of substrates. An insulating layer, a pixel electrode arranged in a matrix, a thin film transistor connected to the pixel electrode, and a gate bus line connected to the thin film transistor. In this active matrix display device, the gate bus wiring has a lower gate wiring and an upper gate wiring, and the lower gate wiring, the upper gate wiring, and the upper portion are provided in a groove formed in the insulating layer. An insulating film provided on the gate wiring is formed. Further, the insulating layer formed on the inner surface of the substrate and the insulating film provided on the upper gate wiring are made of the same constituent material, and the surface of the insulating layer formed on the inner surface of the substrate and the upper gate wiring The height of the surface of the insulating film provided above is the same as that of the surface of the insulating film. Thereby, the above object is achieved.

(Operation) In the active matrix display device of the present invention, the gate bus wiring is provided inside the groove formed in the insulating layer, and the gate bus wiring has a lower gate wiring and an upper gate wiring. Further, an insulating film is formed on the upper gate wiring in the groove.

By thus forming the gate bus wiring in the two-layer structure, a low resistance metal such as Al can be used for the lower gate wiring, and an anodizable metal such as Ta can be used for the upper gate wiring. .

If a low resistance metal such as Al can be used for the lower gate wiring, the luminance gradient of the picture elements displayed by the picture element electrodes connected to the same gate bus wiring does not occur. In addition, since the gate bus wiring having the above-mentioned two-layer structure is embedded in the insulating layer on the substrate, the lower gate wiring does not need to be wider than the lower gate wiring so that the lower gate wiring and the insulating layer on the substrate are Since it is completely covered with the gate wiring, the width of the entire gate bus wiring can be reduced, and thus the aperture ratio of the display screen can be increased.

When the upper gate wiring is formed of Ta metal, the insulating film formed thereon can be formed by anodizing the upper surface of this Ta metal.

Since the upper gate wiring and the insulating film are provided on the lower gate wiring, the lower gate wiring should be exposed to the etchant in the etching process for forming the pattern of the upper gate wiring and in the subsequent etching process. There is no.
Therefore, a material having low etchant resistance can be used for the lower gate wiring.

Further, since the insulating layer on the substrate and the insulating film on the gate bus wiring have the same constituent material, there are few restrictions when selecting a processing chemical that does not corrode both of them, and the adverse effect of the processing chemical is less likely to occur. The TFT manufacturing process can be easily realized. Further, since the surface of the insulating layer on the substrate and the surface of the insulating film on the gate bus wiring have the same height, the gate bus wiring of the insulating layer on the substrate is buried. The portion that is present is flat, and there is no step due to the gate bus wiring on the surface of the insulating layer. Therefore, disconnection does not occur in the source bus wiring arranged on the gate bus wiring so as to intersect with it.

(Examples) The present invention will be described below with reference to Examples. FIG. 1 shows a plan view of a TFT portion of an embodiment of an active matrix substrate used in the display device of the present invention. It should be noted that in FIG. 1, the layers formed by superposition are hatched only on the periphery, and the inside is not hatched. The gate electrode 2 is formed as a part of the gate bus wiring 3, and TF is formed on the gate electrode 2.
T18 is formed. The source electrode 11 of the TFT 18 is connected to the source bus line 12, and the drain electrode 13 of the TFT 18 is connected to the pixel electrode 14. 2A and 2B are sectional views taken along the lines AA and BB of FIG. 1, respectively.
3A to 3G show the manufacturing process of the active matrix substrate of FIG.

This embodiment will be described according to the manufacturing process. Glass substrate 1
Insulating layer 16 made of Ta ₂ O ₅ (layer thickness 2000 to 10,000
Å) was deposited by the spattering method. A photoresist film 15 was formed on the entire surface of the insulating layer 16, and the photoresist film 15 in the region where the gate bus wiring 3 and the gate electrode 2 were to be formed later was removed. Etching was performed using the photoresist film 15 as a mask to form a groove 17 having a depth of 2000 to 10000Å (FIG. 3A).

Next, the photoresist film 15 is removed and the entire surface of the substrate is
A1 metal layer (layer thickness 1000-9000Å) and Ta metal layer (layer thickness 500)
~ 4500Å) was continuously deposited. A photoresist film was formed on the Ta metal layer in the groove 17, and the A1 metal layer and the Ta metal layer in regions other than the groove 17 were simultaneously removed by etching (FIG. 3B). The A1 metal layer left in the groove 17 becomes the lower gate wiring 19 and the lower gate electrode 4, and the Ta metal layer becomes the upper gate wiring 20 and the upper gate electrode 5.

The upper surfaces of the upper gate wiring 20 and the upper gate electrode 5 are anodized to form an anodized film 6 as an insulating film (
(Figure 3C). Ta ₂ O ₅ obtained by anodizing the upper surface of the Ta metal layer has excellent etching resistance, so it is located under the layer.
The Ta metal layer and the A1 metal layer can be protected from the etchant of the subsequent etching process.

Next, by the plasma CVD method, the gate insulating film 7 made of SiN _X (layer thickness 2000 to 5000Å), and later becomes the semiconductor layer 8.
a-Si (i) layer (layer thickness 200-5000Å) and later protective film 9
SiN _X layer (layer thickness 500-2000 Å) was continuously deposited. The uppermost SiN _X layer was patterned to form a rectangular protective film 9 as shown in FIG. 1 (FIG. 3D).

After forming the protective film 9, an n-type a-Si layer (layer thickness of 500 to 150) that is doped with P (phosphorus) on the entire surface is formed by the plasma CVD method.
0Å) was deposited. This n-type a-Si layer will later become the contact layers 10, 10. The n-type a-Si layer and the a-Si (i) layer described above were simultaneously patterned to form the semiconductor layer 8 and the contact layers 10 and 10 (FIG. 3E). At this stage, the two contact layers 10, 10 are connected on the semiconductor layer 8.

Furthermore, Mo metal layer (layer thickness 2000 ~
3000 Å) is deposited and patterned to form the source electrode 1
1, a drain electrode 13 and a source bus line 12 were formed (Fig. 3F). Simultaneously with patterning of Mo metal layer, protective film 9
The upper n-type a-Si layer is also removed, and the two contact layers 10 and 10 are removed.
Is divided into The two contact layers 10 and 10 are provided to make ohmic contact between the drain electrode 13 and the source electrode 11 and the semiconductor layer 8.

Finally, a pixel electrode 14 made of ITO is formed on the gate insulating film 7.
Was formed. The pixel electrode 14 was formed so as to partially overlap the drain electrode 13.

In this embodiment, the lower gate wiring 19 and the lower gate electrode 4
Is composed of an A1 metal layer, the resistance of the gate bus line 3 and the gate electrode 2 as a whole becomes small, and the same gate bus line 3
The problem of luminance tilt of the picture elements displayed by the picture element electrodes connected above is solved.

The lower gate wiring 19 and the lower gate electrode 4 made of the A1 metal layer are provided in the groove 17, and the upper gate wiring 20 is provided thereon.
And the upper gate electrode 5 and the anodic oxide film 6 are formed. Therefore, the upper gate wiring 20 and the upper gate electrode 5 having the same width as the lower gate wiring 19 and the lower gate electrode 4 are formed.
Can be formed. Therefore, the widths of the gate bus line 3 and the gate electrode 2 can be reduced, and the aperture ratio of the display screen can be increased.

Since Ta is used for the upper gate wiring 20 and the upper gate electrode 5, the anodic oxide film 6 can be formed on the wiring 20 and the electrode 5. When the anodic oxide film 6 is formed, the gate bus line 3 and the gate electrode 2 formed thereunder can be protected from the etchant in the step of forming the TFT 18 later.

Further, in this embodiment, since the A1 metal layer and the Ta metal layer are laminated and then these two metal layers are simultaneously etched, it is possible to prevent the generation of hillocks in the lower A1 metal layer. .

In this embodiment, since the upper surface of the anodic oxide film 6 is formed so as to match the upper surface of the insulating layer 16, the semiconductor layer 8 of the TFT 18 formed on the gate electrode 2 can be formed on a flat surface. . Therefore, the reliability of the TFT 18 is improved. Further, since the source bus line 12 that intersects with the gate bus line 2 can also be formed on a plane, the occurrence of leakage at the intersection between the gate bus line 2 and the source bus line 12 can be reduced.

(Effects of the Invention) The active matrix display device of the present invention has a gate bus line having a small specific resistance and a small width. Therefore, the display device of the present invention has a high aperture ratio. In addition, there is little leakage between the gate bus wiring and the source bus wiring. Further, since there is no step due to the gate bus wiring, it is possible to avoid disconnection in the source bus wiring arranged so as to intersect with the gate bus wiring.

Therefore, according to the present invention, there is an effect that it is possible to cope with the increase in the size and the definition of the display device without deteriorating the image quality of the display device.

Furthermore, according to the present invention, since the insulating layer on the substrate and the insulating film on the gate bus wiring embedded in the insulating layer are made of the same constituent material, the insulating layer and the insulating film after the formation of the insulating film are formed. There are few restrictions when selecting a treatment chemical that does not corrode both of them as a treatment chemical used in the process, and there is also an effect that a TFT manufacturing process in which a harmful effect due to the treatment chemical hardly occurs can be easily realized.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of an active matrix substrate used in the display device of the present invention, and FIGS. 2A and 2B are sectional views taken along the lines AA and BB of FIG. 1, respectively. ,
3A to 3G are views showing the manufacturing process of the active matrix substrate of FIG. 1, FIG. 4 is a plan view of a conventional active matrix substrate, and FIG. 5 is taken along the line VV of FIG. Sectional view, FIG. 6 is a sectional view showing an improved example of the gate bus wiring,
FIG. 7 is a sectional view of a conventional active matrix display device. 1 ... Glass substrate, 2 ... Gate electrode, 3 ... Gate bus wiring, 4 ... Lower gate electrode, 5 ... Upper gate electrode, 6 ... Anodic oxide film, 7 ... Gate insulating film, 8 ... Semiconductor layer, 9 ... Protective film, 10 ... Contact layer, 11 ... Source electrode, 12 ... Source bus wiring, 13 ... Drain electrode, 14 ... Pixel electrode, 16 ... Insulating layer, 17 ... Groove, 18 ……
TFT, 19 ... lower gate wiring, 20 ... upper gate wiring.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-235983 (JP, A) JP-A-62-66665 (JP, A) JP-A-62-193351 (JP, A)

Claims (1)

[Claims] 1. A pair of substrates, at least one of which has a light-transmitting property, and an insulating layer formed on an inner surface of one of the pair of substrates, and pixel electrodes arranged in a matrix. An active matrix display device comprising: a thin film transistor connected to the pixel electrode; and a gate bus line connected to the thin film transistor, wherein the gate bus line has a lower gate line and an upper gate line. The lower gate wiring, the upper gate wiring, and an insulating film provided on the upper gate wiring are formed in the groove formed in the insulating layer, and the lower gate wiring is formed on the inner surface of the substrate. The insulating layer and the insulating film provided on the upper gate wiring are made of the same constituent material, and the surface of the insulating layer formed on the inner surface of the substrate and the surface of the insulating film provided on the upper gate wiring. Is that Active matrix display device height are the same.