JP2002258324A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the coverage of a protective film, etc., covering a thin film transistor. SOLUTION: This liquid crystal display device has a thin film transistor in each pixel area on its substrate, and the thin film transistor has an gate electrode, an insulation layer, an island-shaped semiconductor layer, and a couple of electrode, formed on the top surface of the semiconductor layer, in order from the substrate side and also has a gently-sloping side wall corresponding to the outline of the semiconductor layer and is so constituted that the angle of the side wall to the substrate is smaller than the angle the mutually opposite side walls of a couple of electrodes to the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an improvement of an active matrix type thin film transistor.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device extends in the x direction and is arranged in the y direction on a liquid crystal side surface of one of the transparent substrates opposed to each other via a liquid crystal. A gate signal line to be formed and a drain signal line extending in the y direction and juxtaposed in the x direction are formed, and a region surrounded by each of the signal lines is a pixel region. Each pixel region includes a thin film transistor activated by a scanning signal from one gate signal line, and a pixel electrode to which a video signal from one drain signal line is supplied via the thin film transistor. The pixel electrode generates an electric field between the pixel electrode and a counter electrode formed on one of the transparent substrates, and controls the light transmittance of the liquid crystal by the electric field. Here, in the thin film transistor, a part of a gate signal line is used as a gate electrode, an insulating film and a semiconductor layer are sequentially formed on the gate electrode, and one electrode connected to a drain signal line is formed on an upper surface of the semiconductor layer. (Hereinafter referred to as a drain electrode in this specification) and the other electrode connected to a pixel electrode (hereinafter referred to as a source electrode in this specification) having a so-called inverted staggered structure.
There is known an IS (Metal-Insulator-Semiconductor) type transistor. The thin film transistor thus configured is covered with a protective film made of, for example, SiN, so as to avoid direct contact with the liquid crystal. This is because the characteristics of the thin film transistor are deteriorated when it comes into direct contact with the liquid crystal.

[0003]

However, in the liquid crystal display device configured as described above, the semiconductor layer of the thin film transistor (and each electrode formed on the upper surface thereof) is formed in an island shape, that is, as a closed region. Therefore, the portion is formed as a protruding portion, and a relatively steep step is formed on the side wall. For this reason, when a protective film covering the thin film transistor is formed, it is difficult to sufficiently form the protective film at the step, and the protection film does not sufficiently cover the step, that is, the protection on the step. A portion having poor coverage of the protective film / layer (hereinafter simply referred to as coverage) often appeared on a substrate constituting a liquid crystal display device. As a result, it was pointed out that the pixel electrode formed on the protective film was disconnected on or around a step where the coverage of the protective film was insufficient. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal display device capable of improving coverage of a protective film and the like.

[0004]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present invention, typical ones will be briefly described as follows. A liquid crystal display device according to the present invention is, for example, a liquid crystal display device including a thin film transistor in each pixel region on a substrate, wherein the thin film transistor includes a gate electrode, an insulating film, an island-shaped semiconductor layer, A pair of electrodes formed on the upper surface of the layer are formed, a side wall corresponding to the contour of the semiconductor layer is formed gently, and the angle of the side wall with respect to the substrate is set such that the side walls of the pair of electrodes oppose each other with respect to the substrate. The angle is smaller than the angle. In the liquid crystal display device configured as described above, since the side wall corresponding to the outline of the semiconductor layer of the thin film transistor is formed very smoothly, the coverage of the protection film and the like formed so as to cover the thin film transistor is excellent. Can be.

Another example of the liquid crystal display device according to the present invention is as follows.
A pair of substrates in which a liquid crystal layer is sealed therebetween, a first conductor layer extending in a first direction formed on one main surface (the main surface on the liquid crystal layer side) of the pair of substrates, and A first insulating film formed on one conductor layer, and a semiconductor layer formed on the first insulating film so as to extend in a second direction intersecting the first direction and straddle the first conductor layer And a second conductive layer formed on the semiconductor layer, a second insulating film formed on the second conductive layer, the semiconductor layer, and the first insulating film, and formed on the second conductive layer. A third conductor layer formed in contact with the second conductor layer within the opening of the second insulation film and extending from the opening onto the second insulation film;
On the first conductor layer, the second conductor layer is divided so as to face each other, and the semiconductor layer is thinned in a region where the second conductor layer is divided, and sandwiches the divided region of the second conductor layer. The inclination of the side surface (end surface) of the semiconductor layer and the second conductor layer formed below the third conductor layer is smaller than the inclination of the side surface of the second conductor layer and the semiconductor layer opposed to each other. It has features.

[0006] The first conductor layer is made of, for example, a metal layer or an alloy layer called a gate electrode. The second conductor layer is made of, for example, a metal layer or an alloy layer, and is divided above the first conductor layer to form a field effect transistor together with the semiconductor layer. In this case, the divided second
One of the conductor layers is called a source electrode, and the other is called a drain electrode. The third conductor layer is made of, for example, an oxide conductive material (which may have semiconductor characteristics) made of, for example, indium-tin-oxide or indium-zinc-oxide. The semiconductor layer has, for example, an n-type impurity at a higher concentration than other portions along a junction interface with the second conductive layer. This region is formed, for example, by introducing impurities artificially. In this case, in the divided region of the second conductor layer, the semiconductor layer has a thickness of 90% or less of that in a portion sandwiching the divided region of the second conductor layer so that the impurity introduction region is divided. 80 ~
It has been reduced to either of 40%. The inclination of the side surface (end surface) of the semiconductor layer and the second conductor layer is defined, for example, as the angle of each of the etched surfaces macroscopically with respect to the main surface of the substrate. As long as there is, you can ignore it.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the liquid crystal display device according to the present invention will be described below with reference to the drawings. Embodiment 1 FIG. << Equivalent Circuit >> FIG. 2 is an equivalent circuit diagram showing one embodiment of the liquid crystal display device according to the present invention. The figure is a circuit diagram, but is drawn corresponding to an actual geometric arrangement. In the figure, there is a transparent substrate SUB1, which is arranged to face another transparent substrate SUB2 via a liquid crystal.

[0008] On the liquid crystal side surface of the transparent substrate SUB1,
Gate signal line G extending in the x direction and juxtaposed in the y direction in the figure
L and a drain signal line DL which is insulated from the gate signal line GL, extends in the y direction and is arranged in the x direction, and a rectangular region surrounded by these signal lines is a pixel region (FIG. (Shown by a middle dotted line frame A), and the display unit AR is configured by a set of these pixel regions.

Each pixel region has one gate signal line GL
And a pixel electrode PX to which a video signal (voltage) from one drain signal line DL is supplied via the thin film transistor TFT.

In addition, a capacitor Cadd is formed between the pixel electrode PX and the one gate signal line GL adjacent to the one gate signal line GL, and when the thin film transistor TFT is turned off by the capacitor Cadd. To
The video signal supplied to the pixel electrode PX is accumulated for a long time.

The pixel electrode PX in each pixel region is connected to a counter electrode CT commonly formed in each pixel region on the liquid crystal side surface of the other transparent substrate SUB2 which is disposed to face through the liquid crystal.
(Not shown) to generate an electric field, whereby the light transmittance of the liquid crystal between the electrodes is controlled.

One end of each gate signal line GL extends to one side (left side in the figure) of the transparent substrate, and the extending portion is a bump of a semiconductor integrated circuit GDRC composed of a vertical scanning circuit mounted on the transparent substrate SUB1. And a terminal portion GTM connected to the transparent substrate S is formed at one end of each drain signal line DL.
A terminal portion DTM which extends to one side (upper side in the drawing) of UB1 and which is connected to a bump of a semiconductor integrated circuit DDRC comprising a video signal driving circuit mounted on the transparent substrate SUB1 is formed. I have.

Each of the semiconductor integrated circuits GDRC and DDRC is completely mounted on a transparent substrate SUB1 and is called a so-called COG (chip-on-glass) system.

The bumps on the input side of the semiconductor integrated circuits GDRC and DDRC are also connected to the terminal portions G formed on the transparent substrate SUB1.
The terminal portions GTM2 and DTM2 are respectively connected to TM2 and DTM2, and the terminal portions GTM3 and DTM3 are respectively disposed at portions of the periphery of the transparent substrate SUB1 which are closest to the end face through the respective wiring layers. Is to be connected to.

The transparent substrate SUB2 is formed so as to avoid an area where the semiconductor integrated circuit is mounted.
It is arranged to face UB1 and has an area smaller than that of the transparent substrate SUB1.

The fixing of the transparent substrate SUB2 to the transparent substrate SUB1 is performed by a sealing material SL formed around the transparent substrate SUB2.
Also has a function of sealing the liquid crystal between the transparent substrates SUB1 and SUB2.

In the above description, the liquid crystal display device using the COG system has been described. However, the present invention can be applied to a TCP system. here,
In the TCP system, a semiconductor integrated circuit is formed by a tape carrier system, and its output terminal is a transparent substrate S.
The input terminal is connected to a terminal portion formed on the UB1, and the input terminal is connected to a terminal portion on a printed circuit board arranged close to the transparent substrate SUB1.

<< Pixel Configuration >> FIG. 3 is a plan view showing the configuration of one pixel area of the transparent substrate SUB1.
2 is a drawing corresponding to the portion shown in FIG. FIG. 1 is a sectional view taken along the line II of FIG. 3, and FIG. 4 is a sectional view taken along the line IV-IV of FIG.

In FIG. 3, first, a gate signal line GL extending in the x-direction and juxtaposed in the y-direction is formed on the liquid crystal side surface of the transparent substrate SUB1. This gate signal line G
L has a projecting portion projecting toward the pixel region at a part thereof, and the projecting portion is a thin film transistor TFT described later.
Has a function as the gate electrode GT.

An insulating film GI made of, for example, SiN is formed on the surface of the transparent substrate SUB1 so as to cover the gate signal line GL. The insulating film GI functions as an interlayer insulating film with the gate signal line GL for a drain signal line DL described later, functions as a gate insulating film for a thin film transistor TFT described later, and a capacitive element Cadd described later. Has a function as a dielectric film.

An insulating film GI overlapping the gate electrode GT
I-type (intrinsic: not doped with conductivity type determining impurities) made of, for example, a-Si
0 is formed.

The semiconductor layer AS0 is a semiconductor layer of a so-called inverted staggered MIS transistor by forming a drain electrode SD1 and a source electrode SD2 on the upper surface thereof.

The drain electrode SD1 and the source electrode SD2 of the thin film transistor TFT are formed simultaneously with the drain signal line DL formed on the insulating film GI.

That is, a drain signal line DL is formed extending in the y direction and juxtaposed in the x direction in the figure. A part of the drain signal line DL is formed to extend to the upper surface of the semiconductor layer AS0. By doing so, the extending portion is formed as the drain electrode SD1 of the thin film transistor TFT.

At this time, an electrode formed apart from the drain electrode SD1 (corresponding to the channel width of the thin film transistor TFT) becomes the source electrode SD2.
The source electrode SD2 is connected to a pixel electrode PX, which will be described later, and has a pattern having an extended portion slightly extended toward the center of the pixel region in order to secure the connection.

[0026] In addition, the drain electrode SD1, the source electrode S
A semiconductor layer doped with high-concentration impurities is formed at the interface between D2 and the semiconductor layer AS0, and the semiconductor layer AS1 functions as a contact layer.

After the formation of the semiconductor layer AS0, a thin semiconductor layer AS1 doped with impurities is formed on the surface thereof, a drain electrode SD1 and a source electrode SD2 are formed. Then, by etching the exposed semiconductor layer AS0,
The configuration described above can be adopted.

The drain signal line DL
(The drain electrode SD1 and the source electrode SD2) are formed on the surface of the transparent substrate SUB1 on which the drain signal line DL is formed.
A protective film PSV made of, for example, SiN is formed covering the above.

This protective film PSV is composed of a thin film transistor TF
The source electrode SD of the thin film transistor TFT is provided to avoid direct contact of the T with the liquid crystal.
A contact hole CH for exposing a part of the second extended portion is formed. Further, the upper surface of the protective film PSV covers most of the pixel region, for example, ITO (Indium).
-Tin-Oxide) film, and a transparent pixel electrode PX is formed.

The pixel electrode PX is formed so as to cover the contact hole CH of the protective film PSV, and is thereby connected to the source electrode SD2 of the thin film transistor TFT.

Further, on the surface of the transparent substrate SUB1 on which the pixel electrodes PX are formed, an alignment film (not shown) is formed so as to cover the pixel electrodes PX. This alignment film is made of, for example, a resin, and its surface is rubbed in a certain direction. The alignment film comes into contact with the liquid crystal, and determines the initial alignment direction of the liquid crystal.

<< Thin Film Transistor TFT >> The feature of the structure of the thin film transistor TFT is that, first, as shown in the plan view of FIG. Is to be. By doing so, the effect of reducing the number of manufacturing steps of the thin film transistor TFT, and eventually reducing the number of manufacturing steps of the liquid crystal display device can be obtained.

Since the thin film transistor TFT is formed in this manner, the thin film transistor TFT is formed such that there is no step between the contact layer AS1 with respect to the semiconductor layer AS0 and the drain electrode SD1 and the source electrode SD2 with respect to the contact layer AS1. (Because the drain electrode SD1 and the source electrode SD2 are formed separately from each other, there is a step between this portion and the contact layer.)

FIG. 1 is a cross-sectional view taken along the line II of FIG. 3, showing a cross-sectional view of the thin film transistor TFT.
In this figure, a semiconductor layer AS0, a contact layer AS
1. The side wall corresponding to the contour of the laminated body composed of the sequential lamination of the drain electrode SD1 and the source electrode SD2 is formed gently.

As a result, as shown in FIG. 4, which is a cross-sectional view taken along the line IV-IV in FIG. 3, the protection film PSV formed covering the thin film transistor TFT has an effect of improving the coverage.

FIG. 5 shows a conventional structure corresponding to FIG. 4, in which a side wall corresponding to a contour of a stacked body composed of a sequentially stacked semiconductor layer AS0, contact layer AS1, drain electrode SD1 and source electrode SD2. However, there is a fear that the protective film PSV cannot be sufficiently deposited in this portion and the pixel electrode PX is disconnected.

Then, the semiconductor layer AS0 and the contact layer A
The angle θ with respect to the transparent substrate SUB1 of the side wall corresponding to the contour of the stacked body composed of the S1, the drain electrode SD1, and the source electrode SD2 sequentially stacked is determined by the opposing surfaces of the separated drain electrode SD1 and source electrode SD2 ( That is, the side wall is formed to be sufficiently smaller than the angle に 対 す る with respect to the transparent substrate SUB1.

This means that the angle of the side wall corresponding to the contour of the semiconductor layer AS0 with respect to the transparent substrate SUB1 is smaller than the angle of the side wall of the pair of electrodes facing each other with respect to the transparent substrate SUB1. .

A region (channel region) in each of the opposing portions of the drain electrode SD1 and the source electrode SD2 is
A recess is formed until the contact layer AS1 is removed to reach the semiconductor layer AS0. This is because it is necessary to avoid the occurrence of an electric short circuit between the drain region and the source region of the thin film transistor TFT due to the residue of the material forming the contact layer AS1.

Therefore, the angle of the side wall corresponding to the outline of the semiconductor layer AS0 with respect to the transparent substrate SUB1 is smaller than the angle of the side wall of the recess formed in the semiconductor layer AS0 between the pair of electrodes with respect to the transparent substrate SUB1. Is formed.

<< Manufacturing Method >> One embodiment of a method of manufacturing the above-described thin film transistor TFT will be described below with reference to FIGS. 6 (a) to 6 (e).

Step 1. (FIG. 6A) First, a gate signal line GL is formed on the liquid crystal side surface of the transparent substrate SUB1, and an insulating film GI made of, for example, SiN and a semiconductor made of a-Si cover the gate signal line GL. A layer AS0, a contact layer AS1 doped with a high concentration of n-type impurity on the surface of the semiconductor layer AS0, and a conductive layer SD made of metal are formed.

Here, the conductive layer SD is made of Mo, MoW, W
And so on. Further, Ti / Al / Ti or the like may be used. In order to selectively etch the conductive layers SD and the like by photolithography, a photoresist film PR serving as a material for the mask is formed over the entire area of the transparent substrate SUB1.

Then, a photomask MSUB for selectively exposing the photoresist film PR is disposed above the photoresist film, and exposure is performed through the photomask MSUB. Photomask MSUB in this case
Has a light-shielding film having the pattern shown in FIG. 7 on its surface.

FIG. 7 shows a light shielding film corresponding to the pattern of the drain signal line DL extending in the y direction in the figure, and a drain electrode S extending in the x direction in the figure integrally with the light shielding film.
A light-shielding film corresponding to the pattern of D1, a source electrode SD slightly separated from the light-shielding film and also extending in the x-direction in the figure;
Light-shielding films corresponding to the two patterns are formed (these light-shielding films are denoted by M1 in the figure), and a light-shielding film composed of a plurality of linear patterns is provided around each of the light-shielding films. The light shielding film is formed so as to surround the film in a plurality of layers (this light shielding film is denoted by M3 in the figure). Also, the drain electrode S
Between the pattern of D1 and the pattern of the source electrode SD2, a light-shielding film denoted by M3 is also formed, but another linear light-shielding film is also formed (this light-shielding film is denoted by M2 in the figure). .

That is, such a photomask MSU
By using B, a portion that completely blocks exposure, a portion that sufficiently performs exposure, and a portion that performs approximately intermediate exposure (referred to as half exposure) at a boundary portion between these portions are formed. I have to.

Therefore, it is important to determine the amount of exposure in the half exposure in order to make the effect of the present invention sufficient. In the case of the pattern shown in FIG. Can be controlled by the width of the light-shielding film and the gap between adjacent light-shielding films.

When the photoresist film PR is exposed through such a photomask MSUB, and the photoresist film is developed, as shown in FIG. 6A, a light-shielding film corresponding to the photomask MSUB is formed. Accordingly, the photoresist films PR having different thicknesses from each other remain.

That is, the photoresist film PR on the region where the drain signal line DL, the drain electrode SD1, and the source electrode SD2 are formed remains almost completely (in the original photoresist film thickness) (PR1 in the figure). ), The periphery thereof, that is, the half-exposed portion is formed with a gentle slope (P in the figure).
R3). Here, in the region between the drain electrode SD1 and the source electrode SD2, the photoresist film cannot be completely removed (indicated by PR2 in the figure), and the conductive film SD and the semiconductor layers AS1, AS0 will be described later. It remains with a film thickness that can sufficiently withstand the etching performed.

Step 2. (FIG. 6B) Using the remaining photoresist film PR as a mask, the conductive film SD and the semiconductor layers AS1 and AS0 are selectively etched by, for example, plasma etching.
At this time, the photoresist film PR is also slightly etched from its surface.

Here, the conductive film SD is made of Mo, MoW,
In the case of being formed of W or the like, fluorine (SF ₆ , S
The plasma etching F ₆ / O ₂₎ or chlorine _{(Cl 2, Cl 2 / O} 2), if it is formed by Ti / Al / Ti or the like, a plasma etching chlorine (Cl ₂₎ Is preferred.

This step shows the initial stage of the plasma etching, in which the drain electrode SD1 and the source electrode SD2
The photoresist film still remains on the region between the respective formation regions (indicated by PR2 in the figure).

Then, except for the region, the drain signal line D
L, the conductive film SD and the semiconductor layers AS1 and AS0 other than the regions where the drain electrode SD1 and the source electrode SD2 are formed.
Are sequentially etched.

In this case, the drain signal line D
L, the conductive film SD and the semiconductor layers AS1 and AS0 other than the regions where the drain electrode SD1 and the source electrode SD2 are formed.
An extremely gentle slope is formed in a portion corresponding to the side wall of the first embodiment. Although it has disappeared at present, the photoresist film PR3 in this portion is formed with an extremely gentle slope.

That is, if the photoresist film PR3 is formed with a gentle slope, the side walls of the conductive film SD and the semiconductor layers AS1 and AS0 are formed gently according to the degree.

Step 3. (FIG. 6C) Further, by continuing the etching, the etching of the photoresist film PR2 between the respective formation regions of the drain electrode SD1 and the source electrode SD2 proceeds. As a result, the photoresist film PR2 is completely removed from these formation regions (regions corresponding to a channel portion of a thin film transistor TFT described later), and a conductive layer appears between these formation regions. In this case, the remaining photoresist film PR1 includes the drain signal line DL and the drain electrode SD.
1 and the source electrode SD2.

The region between the formation regions of the drain electrode SD1 and the source electrode SD2 and the drain signal line D
Etching also progresses in a portion corresponding to the side wall of the conductive film, the semiconductor layer, and the insulating film in the region where the L, drain electrode SD1, and source electrode SD2 are formed, and the inclination of the portion gradually increases. This is because the photoresist film (PR3) has already disappeared in this portion, and the etching rate increases from the slope having the smaller layer thickness.

Further, instead of the continuation of the plasma etching using the halogen-based compound gas as described above, for example, oxygen plasma ashing (Ashing) is performed to locate a region corresponding to the channel portion of the thin film transistor TFT (FIG. In other words, the photoresist film PR2 formed on the upper surface of the conductive layer SD (on the channel portion) is completely removed,
This conductive layer SD can be exposed.

Step 4. (FIG. 6D) By continuing the etching, the conductive layer SD in a region between the respective formation regions of the drain electrode SD1 and the source electrode SD2 is etched, and the underlying contact layer AS1 is exposed. Become like At this time, a region between the formation regions of the drain electrode SD1 and the source electrode SD2, the drain signal line DL, and the drain electrode SD
1 and the conductive film S in the formation region of the source electrode SD2.
D, the etching also proceeds on the portions corresponding to the side walls of the semiconductor layers AS1 and AS0, and the increase in the inclination of the portions gradually progresses.

Step 5. (FIG. 6E) By continuing the etching further, the contact layer AS1 in the region between the formation regions of the drain electrode SD1 and the source electrode SD2 is completely etched, and the underlying semiconductor layer AS0 is exposed. However, by continuing the etching, the contact layer AS1 in this portion is completely divided. This is to prevent the remaining contact layer AS1 from making electrical connection between the drain region and the source region of the thin film transistor.

At this time, the region between the formation regions of the drain electrode SD1 and the source electrode SD2 and the drain signal line D
The portions corresponding to the sidewalls of the conductive film SD and the semiconductor layers AS1 and AS0 in the regions where the L, the drain electrode SD1, and the source electrode SD2 are formed are also etched, and the inclination of the portions is gradually increased. Thereafter, by removing the remaining photoresist film PR1, the thin film transistor TFT is completed.

In the thin film transistor TFT formed in this manner, at least the slope of the side wall of the semiconductor layer AS0 (which may include the semiconductor layer AS1) has an extremely large etching time. It is formed more gently than the slope of the side wall of the recess.

This is because the etching in this portion is performed using the photoresist film PR3 having a gentle slope formed by half exposure using the light shielding film M3 of the photomask MSUB as a mask.

Embodiment 2 FIG. FIG. 8A shows another embodiment of the photomask MSUB used in the above-described manufacturing method, and corresponds to FIG. Drain electrode SD1 (drain signal line DL) and source electrode SD2
A plurality of linear patterns are formed so as to surround the patterns corresponding to, and the pattern arranged on the outer periphery thereof is formed as a dotted line (indicated by SLT1 in the figure). ). When the photoresist film is exposed by the photomask MSUB configured as described above, the remaining photoresist film PR1 becomes
As shown in FIG. 8B, the periphery is formed gently, and the end is formed so as to be wavy. When the conductive layer SD, the semiconductor layer AS1, and the semiconductor layer AS0 are collectively etched using the photoresist film PR1 as a mask, the sidewalls of the remaining stacked body have an extremely gentle slope.

Embodiment 3 FIG. FIG. 9 is a view showing another embodiment of the photomask MSUB used in the above-described manufacturing method, and corresponds to FIG. 6A. FIG. 6 (a)
Is different from that of the first embodiment in that a light-shielding film (indicated by M1 in the figure) for completely shielding light and a light-shielding film (indicated by M2 and M3 in the figure) for half-exposure are different layers via a transparent conductive film ML. It was formed in. In this case, when the pattern formed by the light-shielding film of the photomask MSUB is focused on the photoresist film PR when the light-shielding film indicated by M1 in the drawing is focused, the light-shielding films indicated by M2 and M3 in FIG. This has the effect of defocusing and improving the reliability of half exposure.

[0066]

As is apparent from the above description, according to the liquid crystal display device of the present invention, the coverage of the protective film covering the thin film transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a thin film transistor of a liquid crystal display device according to the present invention, and is a cross-sectional view taken along line II of FIG.

FIG. 2 is an equivalent circuit diagram showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 3 is a plan view showing one embodiment of a pixel of the liquid crystal display device according to the present invention.

4 is a cross-sectional view showing an effect of the liquid crystal display device according to the present invention, and is a cross-sectional view taken along line IV-IV in FIG.

FIG. 5 is a cross-sectional view showing an example of a conventional liquid crystal display device, corresponding to FIG.

FIG. 6 is a process chart showing one embodiment of a method of manufacturing a liquid crystal display device according to the present invention.

FIG. 7 is a plan view of an essential part showing one embodiment of a photomask used in the method for manufacturing a liquid crystal display device according to the present invention.

FIG. 8 is a main part plan view showing another embodiment of a photomask used in the method for manufacturing a liquid crystal display device according to the present invention.

FIG. 9 is a main part plan view showing another embodiment of a photomask used in the method for manufacturing a liquid crystal display device according to the present invention.

[Explanation of symbols]

GT: gate electrode, GI: insulating film, AS0: semiconductor layer,
AS1 contact layer, SD conductive layer, SD1 drain layer, SD2 source layer, PSV protective film, CH contact hole, PX pixel electrode.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ryutaro Oke 3300 Hayano Mobara-shi, Chiba F-term in Hitachi Display Group 2H092 JA26 JA29 JA38 JA42 JA46 JA47 JB22 JB31 JB57 KA19 KB14 MA13 MA18 NA15 5C094 AA21 AA31 BA03 BA43 CA19 DA14 DA15 DB04 EA04 EA07 EB02 FB12 FB14 FB15 5F110 AA04 AA26 BB01 CC07 EE23 FF03 GG02 GG15 GG22 GG26 HK03 HK04 HK06 HK09 HK21 HK22 NN02 QQ02 QQ03 QQ04

Claims (8)

[Claims] 1. A liquid crystal display device comprising a thin film transistor in each pixel region on a substrate, wherein the thin film transistor has a gate electrode from the substrate side,
An insulating film, a semiconductor layer having an island shape, a pair of electrodes formed on an upper surface of the semiconductor layer are formed, a side wall corresponding to a contour of the semiconductor layer is formed gently, and the angle of the side wall with respect to the substrate is set to A liquid crystal display device characterized in that the pair of electrodes is configured to have an angle smaller than the angle of the side walls facing each other with respect to the substrate. 2. The liquid crystal display device according to claim 1, wherein the pair of electrodes and the semiconductor layer have a plane pattern formed by batch etching. 3. A semiconductor layer, wherein a layer doped with a high concentration of impurities is formed at an interface with a pair of electrodes, and side walls corresponding to contours of the semiconductor layer face each other of the pair of electrodes. 3. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is formed without a step with respect to other side walls except the side wall corresponding to the contour. 4. The surface of the semiconductor layer between the pair of electrodes has a recessed portion from the layer doped with the high concentration impurity to the semiconductor layer not doped with the high concentration impurity. The liquid crystal display device according to claim 3, wherein the liquid crystal display device is formed. 5. A liquid crystal display device comprising a thin film transistor in each pixel region on a substrate, wherein the thin film transistor has a gate electrode from the substrate side,
An insulating film, a semiconductor layer having an island shape, a pair of electrodes formed on the upper surface of the semiconductor layer are formed, and the semiconductor layer is formed with a layer doped with a high concentration of impurities at an interface with the pair of electrodes. And a recess is formed between the pair of electrodes up to the semiconductor layer not doped with the high-concentration impurity, and an angle of a side wall corresponding to a contour of the semiconductor layer with respect to the substrate is formed. The liquid crystal display device according to claim 1, wherein a side wall of the recess formed in the semiconductor layer between the pair of electrodes is smaller than an angle with respect to the substrate. 6. A liquid crystal display device comprising a thin film transistor in each pixel region on a substrate, wherein the thin film transistor has a gate electrode on the substrate, an insulating film, a semiconductor layer, a conductive layer, Forming a photoresist film; a first portion including a formation region of a drain electrode and a source electrode on the photoresist film surface; a region between the drain electrode and the source electrode; and a drain excluding this region. A second portion including a region around each formation region of the electrode and the source electrode, and a third portion other than the second portion, and the irradiation amount of light that changes stepwise from the first portion to the second portion Selectively exposing the photoresist film by using the photoresist film remaining by development as a mask, and simultaneously etching the conductive layer and the semiconductor layer using the photoresist film as a mask And a method of manufacturing a liquid crystal display device. 7. The method according to claim 6, wherein the first part is shielded from light, the third part is exposed, and the second part is exposed with a smaller exposure than the exposure in the third part. 3. The method for manufacturing a liquid crystal display device according to 1. 8. The method of manufacturing a liquid crystal display device according to claim 6, wherein a semiconductor layer doped with a high concentration of impurity is formed on a surface of the semiconductor layer on which the conductive layer is laminated. Method.