JPH1090702A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the opening ratio of pixel without applying an undesired voltage to a pixel electrode by providing the pixel electrode on the upper player of a gate line and a signal line through an interlayer insulation film and providing a shield electrode below the signal line through an insulation film. SOLUTION: The insulation film and the interlayer insulation film are formed extensively over almost whose surface of an array substrate 20 to cover a gate line 26, the signal line 27 and a CS electrode 32, etc. Then, the pixel electrode 29 is provided on the interlayer insulation film. The shield electrode 31 extended from the precedent gate line 26 corresponding to each pixel electrode is provided on the partial lower part of the signal line 27 through a gate insulation film. By providing the shield electrode 31 on the lower part of the signal line 27, coupling capacity between the signal electrode 27 and the pixel electrode 29 is reduced, and the pixel electrode 29 is formed efficiently in an are surrounded by the gate line 26 and the signal line 27, and the opening ratio of the pixel is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having an improved aperture ratio.

[0002]

2. Description of the Related Art Liquid crystal display devices have features such as low power consumption, thinness, and light weight. By utilizing these features, OA equipment such as word processors and personal computers can be used.
It is widely used as a display unit of a television receiver. In particular, active matrix type liquid crystal display devices are being actively developed because high resolution display is possible. In such an active matrix type liquid crystal display device, one of a pair of substrates opposed to each other with a liquid crystal interposed therebetween is used as an array substrate, and the array substrate is provided with a switching element for each pixel, and in a matrix. A plurality of gate lines and signal lines are provided in a direction crossing each other across the arranged pixel electrodes.

FIG. 10 shows a configuration per pixel on the array substrate, and FIG. 11 shows a configuration of a thin film transistor (TFT) as a switching element. In the array substrate, a plurality of gate lines 2 and a plurality of signal lines 3 are respectively provided in parallel in a direction intersecting with each other on a surface of the glass substrate 1 facing the opposite substrate. Pixel electrodes 4 are provided in a matrix in the partitioned area. Further, a TFT 5 is provided near the intersection of the gate line 2 and the signal line 3. In the TFT 5, a gate electrode 7 connected to the gate line 2 is provided on a glass substrate 1, and a contact layer 9, an etching stopper layer 10, and an etching stopper layer 10 are sequentially formed on the gate electrode 7 via gate insulating films 8a and 8b.
A semiconductor layer 11 is provided. Also, the gate insulating film 8b
The pixel electrode 4 is provided thereon. Further, a source electrode 12 and a drain electrode 13 are provided on the semiconductor layer 11, and the source electrode 12 is connected to the pixel electrode 4. Further, a protective film 14 is provided on the array substrate, and an alignment film (not shown) is provided on the protective film 14.

On the other hand, on a counter substrate facing the array substrate, a light shielding film for blocking incident light to the TFT 5, a counter electrode facing the pixel electrode 4 and these light shielding films are provided on a surface facing the array substrate. An alignment film is provided on the counter electrode.

In the above-mentioned conventional liquid crystal display device, since the gate line and the signal line are provided in a direction intersecting each other with the pixel electrode interposed therebetween, there is a limit in increasing the area of the pixel electrode. There is a problem that it is difficult to improve the rate.

As a structure capable of improving the aperture ratio of the pixel, Japanese Patent Application Laid-Open Nos. Hei 3-288824 and Hei 6-130416 disclose an interlayer insulating film particularly so as to cover a source electrode and a drain electrode of a TFT. A structure in which a pixel electrode is overlapped with a gate line or a signal line by providing a film is shown. With such a configuration, the light-shielding film conventionally provided between the gate line and the pixel electrode and between the signal line and the pixel electrode becomes unnecessary, and the aperture ratio of the pixel can be improved.

[0007]

As described above, an interlayer insulating film is provided so as to cover the source electrode and the drain electrode of the TFT as a structure capable of improving the aperture ratio of the pixel of the active matrix type liquid crystal display device. By employing a structure in which a pixel electrode can be overlaid on a gate line or a signal line, a light-shielding film conventionally provided between a gate line and a pixel electrode and between a signal line and a pixel electrode is unnecessary.
A liquid crystal display device capable of improving the aperture ratio of a pixel has been proposed.

However, in this liquid crystal display device, even if the interlayer insulating film is formed of a film having a high relative dielectric constant, when a voltage is applied to the gate line or the signal line, the voltage is applied between the gate line and the pixel electrode and between the signal line and the pixel. There is a problem that a coupling capacitance (parasitic capacitance) is generated between the electrodes and an undesired voltage is applied to the pixel electrodes.

The present invention has been made in view of the above problems, and has as its object to constitute a liquid crystal display device capable of improving the aperture ratio of a pixel without applying an undesired voltage to a pixel electrode. And

[0010]

A plurality of gate lines, a plurality of signal lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix are formed on an insulating substrate in a direction intersecting the gate lines. In the liquid crystal display device having the array substrate thus formed, the pixel electrode was positioned above the gate line and the signal line via the interlayer insulating film, and the shield electrode was provided below the signal line via the insulating film.

In the above liquid crystal display device, a shield electrode extends from a gate line along a signal line, and a pixel electrode is formed on the shield electrode via an interlayer insulating film.

Further, the peripheral portion of the pixel electrode on the signal line side is provided so as to be located above the shield electrode by self-alignment using the shield electrode as a mask.

Further, the signal line is formed of a transparent conductive film, and the signal line and the pixel electrode can be formed by self-alignment using the shield electrode as a mask.

Further, the shield electrode is formed of a transparent conductive film, and the signal line side of the pixel electrode can be formed by self-alignment using the signal line as a mask.

Further, a black matrix is provided in a region on the array substrate where no shield electrode is formed.

An array substrate having an insulating substrate provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix. A pixel electrode is positioned above a gate line and a signal line via an interlayer insulating film, a shield electrode is provided below the signal line via an insulating film, and the insulating film is provided on the gate line. , An electrode for Cs is formed, and the Cs electrode and the pixel electrode are electrically connected to form a storage capacitor between the gate electrode and the gate electrode.

An array substrate having an insulating substrate provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix. In the liquid crystal display device having the above, the pixel electrode is located above the gate line and the signal line via the interlayer insulating film, and a shield electrode is provided below the signal line via the insulating film. A Cs line independent of the gate line was used.

An array substrate having an insulating substrate provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix. , The thin film transistor is provided on the gate line.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[0020]

Embodiment 1 FIG. 1 shows a configuration per pixel of an active matrix type liquid crystal display device of Embodiment 1, and FIGS. 2, 3 and 4 show cross sections taken along lines II-II, III-III and IV-IV, respectively. Is shown.

This liquid crystal display device has an array substrate 20 and a counter substrate 21 facing each other at a predetermined interval, and is formed in a structure in which a liquid crystal composition 22 is interposed between these substrates 20 and 21.

The array substrate 20 has an insulating film 2 on the surface of the insulating substrate 24 made of transparent glass facing the opposite substrate 21.
5, a plurality of gate lines 26 and a plurality of signal lines 27 are provided in parallel on the insulating film 25 in directions intersecting each other. At the intersections of the gate lines 26 and the signal lines 27, the signal lines 27 are made of silicon oxide (SiO 2).
_x ) is located on the gate line 26 via the gate insulating film 28. A plurality of regions (particularly ITO (indium T
The pixel electrodes 29 made of a transparent conductive film such as in Oxide are provided in a matrix. These pixel electrodes 29
The peripheral portion overlaps with the preceding gate line 26 and the following shield electrodes located on both sides, respectively. Further, a thin film transistor 30 (TFT) described later is provided on the gate line 26 near the intersection of the gate line 26 and the signal line 27. Further, below a part of the signal line 27, a shield electrode 31 extending from the previous gate line 26 is provided via the gate insulating film 28 in correspondence with each pixel electrode 29. In the first embodiment, the width of the shield electrode 31 is formed wider than the width of the signal line 27.
On the gate line 26, corresponding to each pixel electrode 29,
An electrode 32 for Cs described later is provided.

The TFT 30 (see FIG. 2) has a part of the gate line 26 as a gate electrode 34 on an insulating substrate 24 via an insulating film 25 and a gate insulating film 28 on the gate electrode 34. A semiconductor layer 35 made of amorphous silicon (a-Si), an i-stopper layer 36, and an ohmic contact layer 37 are sequentially provided. On the ohmic contact layer 37, a drain electrode 38 and a source electrode 39 connected to the signal line are provided. Is provided. Further thereon, an insulating film 40 and an interlayer insulating film 41 whose surface is flattened are provided. These insulating films 40
The interlayer insulating film 41 extends over substantially the entire surface of the array substrate and covers the gate lines, signal lines, Cs electrodes, and the like. The pixel electrode 29 is provided on the interlayer insulating film 41. The pixel electrode 29 is connected to a source electrode 39 via a contact hole 42 penetrating the insulating film 40 and the interlayer insulating film 41. Further, as shown in FIG. 4, the pixel electrode 29 is connected to the shield electrode 31 via the insulating film 40 and the interlayer insulating film 41.
It extends up.

The Cs electrode 32 (see FIG. 3) is provided via a gate insulating film 28 on a gate line 34 provided on the substrate 24 via an insulating film 25. This C
The s electrode 32 is connected to the pixel electrode 29 via a contact hole 44 penetrating the insulating film 40 and the interlayer insulating film 41 covering the s electrode 32.

The array substrate 20 provided with the above members is provided with an alignment film 45a made of a polyimide resin so as to cover the respective members.

On the other hand, the opposing substrate 21 is
A common electrode 47 made of a transparent conductive film such as ITO is provided on a facing surface of the other substrate 46 facing 0, and a black matrix layer 48 for shielding a TFT forming portion of the array substrate from light is provided on the common electrode 47. I have. Further, an alignment film 45b made of a polyimide resin is provided on the common electrode 47 and the black matrix layer 48.

This liquid crystal display device is manufactured as follows.

As for the array substrate 20, the insulating substrate 24
In order to prevent contamination from the substrate 24 and protect the substrate 24 on the surface facing the opposite substrate 21, the insulating film 25 is formed to a thickness of about 300 nm by a sputtering method or a plasma chemical vapor deposition (CVD) method. Formed.

Next, molybdenum-tungsten (MoW) or molybdenum-tantalum (MoTa) is deposited on the insulating film 21 to a thickness of about 200 nm by sputtering, and carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) are deposited. ₂ )
Is etched by a plasma chemical dry etching (CDE) method using a mixed gas of
The gate line 26 and the shield electrode 31 having a tapered side surface of 30 ° or less with respect to the plate surface of No. 4 are formed. Such a gate line 26 and the shield electrode 31 are obtained by etching at a flow rate of carbon tetrafluoride of 160 sccm and a flow rate of oxygen of 320 sccm at an etching pressure of 30 Pa.

Next, silicon oxide (SiO _x ) is deposited on the insulating substrate 24 on which the gate lines 26 and the shield electrodes 31 are formed by plasma CVD using, for example, tetraethyloxysilane (TEOS) gas. Forms a flat gate insulating film 28.

Next, amorphous silicon (a-Si) is deposited to a thickness of 500 nm by a plasma CVD method.
The semiconductor layer 35 is formed by etching.

Next, silicon nitride (SiN _x ) is deposited by plasma CVD and etched to form an i-stopper layer 36. Thereafter, n ⁺ a-Si is deposited to a thickness of 50 nm by a plasma CVD method, unnecessary portions are removed by a CDE method, and the drain electrode 3 on the semiconductor layer 35 is removed.
An ohmic contact layer 37 is formed at the portion where the source electrode 39 is formed.

Next, a metal layer composed of three layers of molybdenum Mo / aluminum Al / molybdenum Mo is deposited to a thickness of 30 nm / 350 nm / 70 nm by a sputtering method and etched to form the ohmic contact layer 3.
The signal line 27 is formed on the drain electrode 38 and the source electrode 39, the shield line 31 via the gate insulation 28, and the Cs electrode 32 on the gate line 26 via the gate insulation 28.

Next, the plasma CV is applied to the insulating substrate 24 on which the drain electrode 38 and the source electrode 39 are formed.
The insulating film 40 is formed by depositing SiN _x by the method D.
Furthermore, after applying a photosensitive agent containing an acrylic resin as a main component by a spin coating method and heating it at 90 ° for 1 minute,
The interlayer insulating film 41 is formed by exposing and developing by photolithography.

Then, the insulating film 40 is etched by using the interlayer insulating film 41 as a resist to form contact holes 42 and 44 reaching the source electrode 39 and the Cs electrode 32.

Next, ITO is deposited on the interlayer insulating film 41 by a sputtering method, and the pad portions on the pixel electrodes 29 and the gate lines 26 are formed using reactive ion etching (RIE) and an HF-based etchant. Form an opening.

Thereafter, a polyimide resin is applied on the surface on which the pixel electrodes 29, the TFTs 30 and the like are formed, and rubbing is performed to form an alignment film 45a.

On the other hand, with respect to the opposing substrate 21, ITO is deposited on the surface of the insulating substrate 46 facing the array substrate 20 by sputtering to form a common electrode 47, and then the common electrode 47 is formed on the common electrode 47 by sputtering. A metal film such as Cr is formed and etched by a photolithography method to form a black matrix layer 48 that shields a portion of the array substrate 20 where a TFT is to be formed. Further, a polyimide resin is applied on the common electrode 47 and the black matrix layer 48 and rubbed to form an alignment film 45b.

Next, the array substrate 20 and the opposing substrate 2
After sealing the peripheral portions of the substrates 20 and 21 with an adhesive, the substrates 20 and 21 are separated from each other.
The liquid crystal composition 22 is sealed therebetween.

By the way, when the liquid crystal display device is configured as described above, the pixel electrode 29 of the array substrate 20 has the interlayer insulating film 4 provided above the gate line 26 and the signal line 27.
1, the signal line 27 serves as a black matrix of pixels. Therefore, the aperture ratio of the pixel can be determined by the signal line 27 and the black matrix layer 48 of the counter substrate 21. In the above embodiment, the aperture ratio of the pixel is 82%. Rate can be improved. Moreover, by planarizing the surface of the interlayer insulating film 41, the pixel electrode 29 formed on the interlayer insulating film 41 is formed.
Can be prevented from being cut off and the coverage can be reduced.

The shield electrode 3 is provided below the signal line 27.
By providing 1, the coupling between the signal line 27 and the pixel electrode 29 can be significantly reduced. That is, with the distance x between the signal line 27 and the pixel electrode 29 shown in FIG. 4 (cross section taken along line IV-IV in FIG.
When the coupling capacitance (parasitic capacitance) between the pixel electrode 7 and the pixel electrode 29 was examined, the relationship shown by the curve 50 in FIG. . The coupling capacitance shown by the curve 50 is the same as the curve 5 shown for the case of the conventional structure without the shield electrode.
When x = 2 μm, the value is much smaller than 2.1, that is, about 2.1 × 10 ⁻³ pF.

A part of the gate line 26 is connected to the gate electrode 3.
4, since the TFT 30 is formed near the intersection of the gate line 26 and the signal line 27 so that the main part overlaps the gate line 26, the distance between the gate line 26 and the shield electrode 31 is very small, 10 μm. Can be made small and the counter substrate 2
One black matrix layer 48 can be made smaller. As a result, the aperture ratio of the pixel can be improved, and at the same time, a short circuit between the gate electrode 30 and the shield electrode 27 can be avoided.

Further, since the Cs electrode 32 is formed of the same metal as the signal line 27 on the gate line 26 via the gate insulating film 28, and the Cs portion is located in a region shielded by the gate line 26, the Cs electrode 32 is formed. No light is further blocked by the part. Therefore, also from this point, the aperture ratio of the pixel can be improved. In particular, the width of the Cs electrode 32 is
By making the width smaller than 6, the C due to misalignment is reduced.
The aperture ratio can be improved while preventing a change in the s value. In addition, the width of the Cs electrode 32 is
, The width of the gate line 26 is set to 1
Cs without providing an undesired light shielding part
A part can be formed.

In the first embodiment, the pixel electrode is provided apart from the gate line for supplying the gate voltage to the pixel electrode. However, the pixel electrode is provided so as to overlap the gate line for supplying the gate voltage to the pixel electrode. Is also good. By thus overlapping, a liquid crystal display device can be configured without a black matrix.

Further, an organic solvent comprising a fluorine-containing polymer having a repeating unit derived from a material having a large interlayer insulating film or a small dielectric constant, for example, perfluoroanyl vinyl ether or perfluorobutenyl vinyl ether; The coupling capacitance between the signal line and the pixel electrode can be further reduced by forming it with a top (a relative dielectric constant of about 2.1, manufactured by Asahi Glass Co., Ltd.) or the like.

[0046]

Embodiment 2 FIG. 6 shows a configuration per pixel of an active matrix type liquid crystal display device of Embodiment 2. In this liquid crystal display device, the shield electrode 31 is provided independently of the gate line 26. The shield electrode 31 also serves as a Cs line, and includes a portion located on both sides of the pixel electrode 29 along the signal line 27, and a portion connecting the portions located on both sides across the pixel electrode 29. ing. A Cs electrode 32 is provided on a portion connecting the portions located on both sides across the pixel electrode 29.

The other parts are described in the first embodiment.
Therefore, the same reference numerals are given to the same parts, and the description thereof will be omitted.

When the liquid crystal display device is configured in this manner, the load on the gate line 26 is reduced. Therefore, it is preferable that the gate line time constant be lower, such as a high-definition liquid crystal display device, or Cs such as H common inversion drive. A liquid crystal display device suitable for a device having a smaller time constant is preferable.

[0049]

Third Embodiment FIG. 7 shows the structure of an active matrix type liquid crystal display device according to a third embodiment. In this liquid crystal display device, the signal line 27 is made of a transparent conductive film such as ITO, and the width of the signal line 27 is equal to the width of the shield electrode 31 at the bottom.

The other parts are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals and description thereof will be omitted.

When the signal line 27 is made of a transparent conductive film as described above, the pixel electrode 29 is formed by self-alignment using the shield electrode 31 as a mask.
The aperture ratio of the pixel can be further improved. Further, the coupling capacitance between the signal line 27 and the pixel electrode 29 can be reduced.

[0052]

Fourth Embodiment FIG. 8 shows the configuration of an active matrix type liquid crystal display device of a fourth embodiment. In this liquid crystal display device, the width of the signal line 27 is smaller than the width of the shield electrode 31 at the lower portion, and the pixel electrode 29 can be formed by self-alignment using the shield electrode 31 as a mask.

The other parts are the same as those in the first embodiment, and therefore, the same parts are denoted by the same reference numerals and description thereof will be omitted.

In this way, the aperture ratio of the pixel can be increased, and the coupling capacitance between the signal line 26 and the pixel electrode 29 can be reduced.

[0055]

Fifth Embodiment FIG. 9 shows the structure of an active matrix type liquid crystal display device of a fifth embodiment. In this liquid crystal display device, the shield electrode 31 is made of a transparent conductive film such as ITO, and the width of the shield electrode 31 is larger than the width of the signal line 27.

The other parts are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals and description thereof will be omitted.

When the shield electrode 31 is made of a transparent conductive film in this manner, the pixel electrode 29 can be formed by self-alignment using the signal line 27 as a mask, and the shield electrode 27 can be formed without affecting the aperture ratio of the pixel. Can be increased in width.

[0058]

As described above, according to the present invention, by providing the shield electrode below the signal line, the coupling capacitance between the signal line and the pixel electrode is reduced, and the pixel electrode is connected to the gate line. Can be formed without waste in a region surrounded by the signal lines and the aperture ratio of the pixel can be improved.

In addition, by providing a main part of the TFT on the gate line with a part of the gate line as a gate electrode,
From this point as well, the aperture ratio of the pixel could be improved.

Further, by forming the signal line or the shield electrode under the signal line with a transparent conductive film, the pixel electrode can be formed by self-alignment using the shield electrode or the signal line as a mask. Can be further improved, and the coupling capacitance between the signal line and the pixel electrode can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration per pixel of an active matrix liquid crystal display device of Example 1 in an embodiment of the present invention.

FIG. 2 is a sectional view of the active matrix type liquid crystal display device shown in FIG. 1, taken along the line II-II.

3 is a sectional view of the active matrix type liquid crystal display device shown in FIG. 1, taken along the line III-III.

FIG. 4 is a sectional view of the active matrix type liquid crystal display device shown in FIG. 1, taken along the line IV-IV.

FIG. 5 is a diagram for explaining a coupling capacitance between a signal line and a pixel electrode of the active matrix liquid crystal display device according to the first embodiment.

FIG. 6 is a diagram showing a configuration per pixel of an active matrix liquid crystal display device of Example 2 in an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a configuration of an active matrix liquid crystal display device of Example 3 in an embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a configuration of an active matrix liquid crystal display device of Example 4 in an embodiment of the present invention.

FIG. 9 is a sectional view showing a configuration of an active matrix liquid crystal display device of Example 5 in an embodiment of the present invention.

FIG. 10 is a diagram showing a configuration per pixel of a conventional active matrix liquid crystal display device.

FIG. 11 is a diagram showing a configuration of a TFT in a conventional active matrix liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 20 array substrate 21 counter substrate 26 gate line 27 signal line 28 gate insulating film 29 pixel electrode 30 thin film transistor 31 shield electrode 32 Cs electrode 40 insulating film 41 interlayer insulating film 47 common electrode 48 ... Black matrix layer

Claims (9)

[Claims] An array substrate provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting with the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix on an insulating substrate. Wherein the pixel electrode is located above the gate line and the signal line via an interlayer insulating film, and a shield electrode is provided below the signal line via an insulating film. Characteristic liquid crystal display device. 2. The liquid crystal display according to claim 1, wherein the shield electrode extends from the gate line along the signal line, and a pixel electrode is provided on the shield electrode via an interlayer insulating film. apparatus. 3. The liquid crystal display according to claim 1, wherein the pixel electrode is formed so that a peripheral portion on the signal line side is located above the shield electrode by self-alignment using the shield electrode as a mask. apparatus. 4. The liquid crystal display according to claim 1, wherein the signal line is formed of a transparent conductive film, and the signal line and the pixel electrode can be formed by self-alignment using the shield electrode as a mask. apparatus. 5. The shield electrode is formed of a transparent conductive film,
2. The liquid crystal display device according to claim 1, wherein the signal line side of the pixel electrode can be formed by self-alignment using the signal line as a mask. 6. The liquid crystal display device according to claim 1, wherein a black matrix is formed in a region on the array substrate where no shield electrode is formed. 7. An array substrate having an insulating substrate provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix. Wherein the pixel electrode is located above the gate line and the signal line via an interlayer insulating film, a shield electrode is provided below the signal line via an insulating film, and the gate electrode An electrode for Cs is formed on the wire via the insulating film, and the Cs
A liquid crystal display device, wherein an auxiliary electrode is electrically connected to the pixel electrode to form an auxiliary capacitor between the gate electrode and the pixel electrode. 8. An array substrate provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix on an insulating substrate. Wherein the pixel electrode is located above the gate line and the signal line via an interlayer insulating film, and a shield electrode is provided below the signal line via an insulating film. Extending from a Cs line independent of the gate line. 9. An array substrate in which an insulating substrate is provided with a plurality of gate lines, a plurality of signal lines in a direction intersecting the gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes arranged in a matrix. 2. The liquid crystal display device according to claim 1, wherein the thin film transistor is provided on the gate line.