KR20010050708A - Thin film transistor for liquid crystal display - Google Patents

Abstract

PURPOSE: A thin film transistor substrate for a liquid crystal display device is to reduce a distortion according to a voltage of a storage capacitance electrode, thereby minimizing a failure such as a flicker and a crosstalk. CONSTITUTION: A gate interconnection includes gate lines(22) which are formed in a row direction. A data interconnection insulated with the gate interconnection includes data lines(62) which are formed in a column direction. The gate lines are intersected with the data lines to thereby form pixels in a matrix form. A pixel electrode(82) receives a video signal from the data lines. A storage capacitance interconnection is overlapped with the pixel electrode to form a charge capacitance. The storage capacitance interconnection includes storage capacitance electrode lines(26,28) and a storage capacitance electrode. A storage capacitance interconnection connecting unit(84) electrically connects the storage capacitance interconnection of adjacent pixels.

Description

Thin film transistor substrate for liquid crystal display device {THIN FILM TRANSISTOR FOR LIQUID CRYSTAL DISPLAY}

The present invention relates to a thin film transistor substrate for a liquid crystal display device, and more particularly, to a thin film transistor substrate for a liquid crystal display device having separate independent wirings for forming a storage capacitor.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a pixel electrode and a common electrode formed on each of two substrates and a thin film transistor for switching a voltage applied to the pixel electrode are used. It is common to form one together, and the board | substrate with which the thin film transistor was formed is called the thin film transistor substrate for liquid crystal display devices.

A gate line and a data line are formed on the thin film transistor substrate for a liquid crystal display device to cross each other, and a thin film transistor is formed at an intersection portion of the gate line and the data line. According to the switching operation of the thin film transistor, a pixel electrode to which an image signal is transmitted through a data line is formed.

On the other hand, a sustain electrode line is formed on the thin film transistor substrate for a liquid crystal display device to assist and maintain the charge holding ability of the liquid crystal capacitor, and the sustain electrode line overlaps the pixel electrode and the insulating film to form a storage capacitor. On the other hand, the common electrode applied to the common electrode formed on the other substrate forming the liquid crystal capacitor facing the pixel electrode to form the liquid crystal capacitor is transferred to the sustain electrode line or the gate voltage transferred to the gate line.

However, the voltage transmitted to the storage electrode line is affected by the change of the image signal transmitted to the data line, so that the voltage of the storage electrode line changes depending on the position, and the voltage of the common electrode line causes signal distortion due to resistance according to the storage capacitance. As a result, the liquid crystal capacitance of the pixel is changed, which causes problems such as flickering or crosstalk.

An object of the present invention is to minimize the flicker or crosstalk failure by reducing the distortion to the voltage of the sustain electrode line.

In addition, another object of the present invention is to provide a thin film transistor substrate for a liquid crystal display device having a wiring structure capable of repairing defects in gate lines and data lines.

1 is a schematic diagram illustrating a structure of a thin film transistor for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view illustrating in detail a structure of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

3 is a cross-sectional view taken along the line III-III 'of FIG. 2,

4A to 4D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention, in the order of their processes;

5A to 5G are cross-sectional views illustrating another method for manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, in the order of their processes;

6 is a circuit diagram showing the structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention;

FIG. 7 is a layout view specifically illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line VIII-VIII 'of FIG. 7;

9 is a circuit diagram illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

In order to solve such a problem, an auxiliary line connecting at least the storage electrode lines of pixels adjacent to each other is formed on the thin film transistor substrate for a liquid crystal display according to the present invention, and a repair beam in which both ends of the storage electrode lines of the pixels adjacent to each other overlap each other. Joseon is formed.

In the thin film transistor substrate for a liquid crystal display device according to the present invention, a gate wiring including a gate line is formed in a horizontal direction and a data wiring including a data line is formed in a vertical direction. A pixel electrode, which receives an image signal through a data line, is formed in a pixel defined by the intersection of the gate line and the data line, and a storage electrode overlaps with the pixel electrode to form a storage capacitor, and includes a storage electrode line and a storage electrode connected to the storage electrode line. Wiring is formed. In addition, a storage wiring connection portion for electrically connecting the storage wirings of neighboring pixels to each other is formed.

At this time, both ends may further include a repair auxiliary line overlapping with the storage wiring of the pixels adjacent to each other.

Here, it is preferable that the sustain wiring connection portion is formed of the same layer as the pixel electrode, the repair auxiliary line is formed of the same layer as the data line, and the sustain wiring is formed of the same layer as the gate wiring.

In addition, the edge of the pixel electrode preferably overlaps with the sustain wiring, and the pixel electrode is formed by connecting a plurality of squares having curved edges or a square, jagged or It may have a cross shape.

More specifically, in the thin film transistor substrate for a liquid crystal display device according to the present invention, a gate wiring including a gate line formed in the row direction and a gate electrode connected to the gate line is formed on the insulating substrate, and in the row direction. A sustain wiring including a sustain electrode line and a sustain electrode connected to the sustain electrode line is formed. In addition, a gate insulating film is formed over the substrate, and a semiconductor layer is formed over the gate insulating film. The gate insulating film is formed over the gate insulating film. A data line is formed that includes an extended source electrode and a drain electrode separated from the source electrode and extending to an upper portion of the semiconductor layer. Each pixel is formed with a pixel electrode electrically connected to the drain electrode and overlapping the storage wiring to form a storage capacitor, and at least a storage wiring connection portion for connecting pixel wirings of neighboring pixels to each other.

In this case, the repair auxiliary line may be formed on the passivation layer in the same layer as the pixel electrode, and the repair auxiliary line may further include a repair auxiliary line in which both ends overlap the sustain wiring of the pixels adjacent to each other. have.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

1 is a schematic diagram illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

As shown in FIG. 1, a plurality of gate lines 22 are formed in a horizontal direction in the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention, and cross the gate lines 22 to form a matrix. The data line 62 defining the pixel region is formed. In each pixel area, a pixel electrode 82 through which an image signal is transmitted is formed through the data line 62, and is connected to the gate line 22 at a portion where the gate line 22 and the data line 62 cross each other. A thin film transistor including a gate electrode 24, a source electrode 65 connected to the data line 62, and a drain electrode 66 connected to the pixel electrode 82 is formed. In the horizontal direction, double storage electrode lines 26 and 28 are formed parallel to each other, and the storage electrode lines 26 and 28 parallel to each other are formed in the vertical direction in each pixel area. Connected via Here, the storage wirings 26, 27, and 28 overlap with the pixel electrode 82 to form a storage capacitor. Further, in the vertical direction, the repair auxiliary line 68 having both ends overlapped with the storage wirings 26, 27, 28 of the pixel rows adjacent to each other and the storage wirings 26, 27, 28 of the pixel rows adjacent to each other at least. The maintenance wiring connection part 84 which electrically connects is formed.

In the structure of the thin film transistor substrate for a liquid crystal display according to the exemplary embodiment of the present invention, the sustain wirings 26, 27, and 28 adjacent to each other are connected to each other through the sustain wiring connecting portion 84, and thus the sustain wirings 26, 27, It is possible to minimize the signal distortion of the voltage for the storage capacitance transmitted through 28). Therefore, crosstalk or flicker defects can be minimized.

Further, in the structure according to the embodiment of the present invention, when the gate line 22 or the data line 62 is disconnected, the maintenance wirings 26, 27, 28, repair auxiliary line 68 and the maintenance wiring connection portion 84 ), The disconnection of the wiring can be repaired.

For example, if the data line 62 is disconnected at the A (Δ) portion, the laser is irradiated to the C portion to short the data lines 62 and the sustain electrode lines 26 and 28, and the laser is irradiated to the B portion. Short-circuit the repair auxiliary line 68 and the sustain electrode lines 26 and 28, and disconnect the sustain electrode lines 26 and 28 of both outer D portions between the B portion and the C portion and transfer them to the data line 62. The image signal to be used is made to bypass the storage electrode lines 26 and 28 and the repair auxiliary line 68.

For example, if the gate line 22 is disconnected at the E (Δ) portion, the laser is irradiated to the F portion to short the gate line 22, the storage electrode lines 26 and 28, and the storage wiring connection portion 84. The sustain electrode lines 26 and 28 and the sustain wiring connecting portion 84 of the G portion are disconnected so that the gate signal is bypassed through the sustain electrode lines 26 and 28 and the repair auxiliary line 68. In this case, only the repair auxiliary line 68 may be used instead of the maintenance wiring connection part 84.

In this case, the repair auxiliary line 68 and the storage wiring connecting unit 84 may be formed of the same layer as the pixel electrode 82 or the data line 62, and may be formed of different layers. In the embodiment of the present invention, the sustain wirings 26, 27, and 28 are formed of the same layer as the gate line 22, and the repair auxiliary line 68 is formed of the same layer as the data line 62. The sustain wiring connection portion 84 is formed of the same layer as the pixel electrode 82. This will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention in detail. FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

First, a gate made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) or the like on the insulating substrate 10. Wiring and sustain wiring are formed. The gate wiring includes a scan signal line or a gate line 22 extending in the horizontal direction and a gate electrode 24 of a thin film transistor that is part of the gate line 22. The gate wiring is connected to the end of the gate line 22 to be external. The gate pad may further include a gate pad receiving the scan signal from the gate line 22. The sustain wiring is formed in parallel to the gate line 22 and is formed in the vertical direction and the sustain electrode lines 26 and 28 that receive a voltage such as the common electrode voltage input to the common electrode of the upper plate from the outside. A storage electrode 27 for connecting the storage electrode lines 26 and 28 to each other. The sustain wirings 26, 27, and 28 are intended to make a storage capacitor overlapping with the pixel electrode 82, which will be described later, to form a storage capacitor for improving the charge storage capability of the pixel.

Here, the gate wirings 22, 24 and the sustain wirings 26, 27, 28 may be formed in a single layer, but may also be formed in a double layer or a triple layer. In the case where more than two layers are formed, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials, especially indium zinc oxide (ITO) used as a pixel electrode. This is because the pad part is formed together with the wiring material and the ITO material for the pixel electrode in order to reinforce the pad part electrically connected to the outside.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22 and 24 and the storage wirings 26, 27, and 28 to form the gate wirings 22 and 24 and the storage wirings 26 and 27. 28).

A semiconductor pattern 40 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 30, and is heavily doped with n-type impurities such as phosphorus (P) on the semiconductor pattern 40. An ohmic contact layer pattern or intermediate layer patterns 55 and 56 made of amorphous silicon are formed.

On the contact layer patterns 55 and 56, source and drain electrodes 65 and 66 of a thin film transistor made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, and Ta are formed, respectively. The data line 62 which is connected to the source electrode 65 and crosses the gate line 22 and defines the pixel is formed in the vertical direction. The data lines 62, 65, and 66 may further include a data pad connected to one end of the data line 62 to receive an image signal from the outside. On the gate insulating layer 30, a repair auxiliary line 68 overlapping the adjacent storage electrode lines 26 and 28 of the pixel row adjacent to each other in the same layer as the data lines 62, 65, and 66, are arranged in the vertical direction. Formed. As mentioned above, the maintenance wiring connection part 84 (see FIG. 1) together with the repair auxiliary line 68 may also be formed on the gate insulating layer 30 in the same layer as the data lines 62, 65, and 66.

The data wirings 62, 65, 66 and the repair auxiliary line 68 may also be formed in a single layer like the gate wirings 22, 24 and the sustain wirings 26, 27, 28, but may be formed in a double layer or a triple layer. It may be formed. Of course, when forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials.

A passivation layer 72 is formed on the data wires 62, 65, and 66, the repair auxiliary line 68, and the semiconductor pattern 40 not covered by the passivation layer, and the passivation layer 72 forms the drain electrode 66. It has a contact hole 71 which exposes, and also has the contact hole 74 which exposes the storage electrode lines 26 and 28 with the gate insulating film 30, respectively. The passivation layer 72 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 72, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the common electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is physically and electrically connected to the drain electrode 66 through a contact hole 71 to receive an image signal. I receive it. In addition, the upper portion of the passivation layer 72 may have the same layer as that of the pixel electrode 82, and the storage line connecting portion 84 may electrically and physically connect the adjacent storage lines 26, 27, and 28 adjacent to each other through the contact hole 74. ) Is formed. As mentioned above, the repair auxiliary line 68 may be formed on the passivation layer 72 in the same layer as the sustain wiring connection 84. The passivation layer 72 may have a contact hole that exposes the gate pad and the data pad, and an auxiliary gate pad and an auxiliary data pad may be formed on the same layer as the pixel electrode to cover the gate pad and the data pad through the contact hole. .

In this case, as shown in FIG. 2, the sustain wirings 26, 27, and 28 may be used as a light blocking film that blocks light leaking from the edge portion of the pixel electrode 82. It is preferable to overlap with the sustain wirings 26, 27, 28. In addition, in order to improve the viewing angle of the liquid crystal display, it is preferable to divide and align the liquid crystal molecules. For this purpose, the pixel electrode 82 may have a shape in which several corners having curved edges are connected. It may have an opening pattern of various shapes of square or serrated shape. In this way, a fringe field may be formed to align the liquid crystal molecules in a divisional manner, and in order to obtain the best viewing angle, it is preferable that the quadrant oriented microregions are contained within one pixel region, thereby obtaining a stable division orientation. In order to prevent the occurrence of disclination or irregular textures outside the boundaries of the divided micro-areas, it is desirable that the angle formed by the liquid crystal director of the adjacent micro-areas be 90 degrees. desirable. In this case, when light leaks due to the foreground or an arrangement of irregular liquid crystal molecules, the structures of the storage wirings 26, 27, and 28 may be variously changed to block the leaked light. Of course, according to the shape of the pixel electrode 82, various opening patterns may be formed on a common electrode (not shown) facing the pixel electrode 82.

In the exemplary embodiment of the present invention, the repair auxiliary line 68 or the storage wiring connecting portion 84 is formed for each pixel, but a plurality of pixels may be formed as a unit.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

A method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, in the order of their processes.

First, as shown in FIG. 4A, a low-resistance conductive material is stacked on the substrate 10 and patterned by a photolithography process using a mask to form the gate wirings 22 and 24 and the storage wirings 26, 27, 28, 2).

Subsequently, as shown in FIG. 4B, the gate insulating layer 30 made of an insulating material such as silicon nitride, the semiconductor layer 40 made of a semiconductor material such as amorphous silicon, and the ohmic contact layer made of a conductive material such as doped amorphous silicon The semiconductor layers 40 are sequentially stacked by chemical vapor deposition, and the resistive contact layer 50 is patterned on the semiconductor layer 40 and the upper portion thereof by a photolithography process using a mask.

Subsequently, as shown in FIG. 4C, the conductive material having a low resistance is stacked and patterned by a photolithography process using a mask to form the data lines 62, 65, 66, and FIG. 2, and the repair auxiliary line 68. do.

Subsequently, the intermediate layer not covered by the data lines 62, 65, and 66 is etched to etch the ohmic contact layer 50, thereby separating the ohmic contact layer into two parts 55 and 56, and the source and drain electrodes 65 and 66. The semiconductor layer 40 between the layers is exposed.

Subsequently, as shown in FIG. 4D, a protective film 72 is formed by stacking silicon nitride, silicon oxide, or an organic insulating film, and the protective film 72 is patterned together with the gate insulating film 30 by a photolithography process using a mask to drain. Contact holes 71 and 74 are formed to expose the electrode 66 and the sustain wirings 26, 27, 28 (see FIG. 2).

2 and 3, a transparent conductive material such as IZO or ITO is stacked on the passivation layer 72 and patterned by a photolithography process using a mask to form the pixel electrode 82 and the storage wiring connection 84. To form.

On the other hand, there are various manufacturing methods for completing a thin film transistor substrate using four masks, but one embodiment will be described below.

5A to 5G are cross-sectional views illustrating another method for manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention, in the order of their processes.

First, as shown in FIG. 5A, the gate wirings 22 and 24 and the storage wirings 26, 27, and 28 are stacked and patterned by stacking and patterning a conductive material having a low resistance on the substrate 10 as in the previous embodiment. , See FIG. 2).

Next, as shown in FIG. 5B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are successively deposited by using a chemical vapor deposition method, and then a low resistance conductive material is included. The conductor layer 60 is deposited by a method such as sputtering, and then a photosensitive film is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIG. 5B. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 disposed between the source electrode 65 and the drain electrode 66, may be disposed in the data wiring portion and the repair auxiliary line portion. The thickness of the photoresist film of the other portion (B) is smaller than that of the second portion (112) positioned at the corresponding portion A, that is, the portion where the data lines 62, 65, 66 and the repair auxiliary line 68 are to be formed. Remove everything. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C and the thickness of the photoresist film 112 remaining in the A portion should be different depending on the process conditions in the etching process, which will be described later. It is preferable to make the thickness of 114 into 1/2 or less of the thickness of the second part 112.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data wiring, the repair auxiliary line, and the film under the film remain in the portion A, and only the semiconductor layer remains in the channel portion C, and the upper three layers 60 and 50 in the remaining portion B. , 40 must be removed to expose the gate insulating film 30.

First, as shown in FIG. 5C, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than in the case of wet etching so that the first portion 114 is removed in this process so that the conductor layer 60 is not exposed in the channel portion C.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIG. 5C, only the conductor layers of the channel portion C and the A portion, that is, the conductor pattern 67 for the source / drain and the conductor pattern 68 for the repair auxiliary line remain, and the other portion B All of the conductor layer 60 is removed to reveal the underlying intermediate layer 50. In this case, the remaining conductor patterns 67 and 68 are in the form of the data wires 62, 65 and 66 and the repair auxiliary line 68 except that the source and drain electrodes 65 and 66 are connected without being separated. Is the same as In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIG. 5D, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this way, as shown in FIG. 5D, the first portion 114 of the channel portion C is removed to reveal the source / drain conductor pattern 67, and the intermediate layer 50 and the semiconductor portion of the other portion B are exposed. The layer 40 is removed to reveal the gate insulating film 30 thereunder. On the other hand, since the second portion 112 of the A portion is also etched, the thickness becomes thin. In this step, the semiconductor pattern 40 is completed.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIG. 5E, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 50 under the etching are removed by etching. In this case, the etching may be performed only by dry etching for both the source / drain conductor pattern 67 and the intermediate layer pattern 50, and the source / drain conductor pattern 67 may be wet-etched, and the intermediate layer pattern ( 50) may be performed by dry etching. In the former case, it is preferable to perform etching under a condition where the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 50 is large. This is difficult to find an etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 40 remaining in the. For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the dry intermediate layer pattern 50 is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 50 and the semiconductor pattern 40 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} may leave the semiconductor pattern 40 in a uniform thickness. In this case, as shown in FIG. 15B, a portion of the semiconductor pattern 40 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched, and the second portion 112 is etched to expose the lower data lines 62, 65, 66, and the repair auxiliary line 68. It is a matter of course that the photosensitive film pattern is preferably thick so that there is no work.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 65, 66, the repair auxiliary line 68, and the contact layer patterns 55, 56, 58 thereunder. do.

Finally, the photosensitive film second portion 112 remaining in the portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 50 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 65, 66 and the repair auxiliary line 68 are formed in this manner, as shown in FIG. 5F, silicon nitride is deposited by the CVD method to form the protective film 70. Subsequently, patterning is performed with the gate insulating film 30 to form contact holes 71 and 74 exposing the drain electrode 66 and the storage wirings 26, 27, and 28.

Finally, as shown in FIG. 5G, as described above, ITO or IZO is deposited and etched using a mask to form the pixel electrode 82 connected to the drain electrode 66. At this time, the storage wiring connecting portion 84 for electrically connecting the storage wirings of the pixels adjacent to each other through the contact hole 74 is formed.

In this case, the data lines 62, 65, and 66, the intermediate layer patterns 55 and 56, and the semiconductor pattern 40 may be formed together in a photolithography process using a single mask, thereby reducing manufacturing costs.

In this case, unlike the structures of FIGS. 2 and 3, the semiconductor layer 40 and the ohmic contact layers 55 and 56 are formed along the shapes of the data lines 62, 65, and 66. In this case, the data lines 62, 65, 66 and the intermediate layer patterns 55 and 56 are formed in the same pattern, and the semiconductor pattern 40 except for the channel portion between the source electrode 65 and the drain electrode 66 may have the data line. It is formed in the same pattern as the (62, 65, 66) and the intermediate layer patterns (55, 56). Of course, the semiconductor layer and the intermediate layer remain below the repair auxiliary line 68.

A thin film transistor substrate for a liquid crystal display device having a sustain wiring connection according to an exemplary embodiment of the present invention is used in a twisted nematic mode or a vertical alignment mode. This will be described.

6 is a circuit diagram illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 6, a plurality of gate lines 22 are formed in the horizontal direction, and data lines 62 are formed to cross the gate lines 22 and define a pixel area in a matrix form. Each pixel region includes a gate electrode 24 connected to the gate line 22, a source electrode 65 connected to the data line 62, and a drain electrode 66 connected to the pixel electrode 82. A thin film transistor TFT is formed. In each pixel area, the pixel electrode 82 and the storage electrode lines 26 and 28 are both terminals, and the storage capacitor C _st having the storage capacitance, and the pixel electrode 82 and the common electrode (not shown) are both ends. A liquid crystal capacitor C _LC having a liquid crystal capacity is formed. Further, in the vertical direction, a sustain wiring connection portion 84 for electrically connecting the sustain wirings 26, 27, 28 of the pixel rows adjacent to each other is formed. Here, the sustain wiring connection portion 84 is formed in each pixel.

On the other hand, a thin film transistor substrate for a planar drive type liquid crystal display device which is formed on the same substrate and formed in substantially parallel to each other to drive liquid crystal molecules has a structure of electrically connecting at least one terminal of the storage capacitors of pixels adjacent to each other. The maintenance wiring connection part may be formed, which will be described in detail with reference to FIGS. 7 and 8.

FIG. 7 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment. FIG. 8 is a cross-sectional view taken along the line VIII-VIII ′ of FIG. 7.

As shown in FIG. 7 and FIG. 8, the gate wiring and the common wiring are formed on the insulating substrate 10. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction, the ends of the gate electrode 24 and the gate line 22 of the thin film transistor that is part of the gate line 22 to apply a scan signal from the outside. It includes a gate pad 25 to receive and transfer to the gate line (22). The common wiring further includes common electrode lines 23 and 29 formed in parallel to the gate line 22 and a common electrode 21 formed in the longitudinal direction and connected to the common electrode electrode lines 23 and 29. . The common electrode lines 23 and 29 overlap the pixel electrode lines 63 and 69 which will be described later to form a storage capacitor that forms a storage capacitor for improving the charge storage capability of the pixel.

On the gate wirings 22, 24, 25 and the common wirings 23, 21, 29, a gate insulating film 30 made of silicon nitride (SiN _x ) is formed to form the gate wirings 22, 24, 25, and the sustain wiring ( 21, 23, 29).

A semiconductor pattern 40 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 30, and is heavily doped with n-type impurities such as phosphorus (P) on the semiconductor pattern 40. An ohmic contact layer pattern or intermediate layer patterns 55 and 56 made of amorphous silicon are formed. Here, the semiconductor layer 40 is formed in the vertical direction along the data line 62 which will be described later. The semiconductor layer 40 is formed to be wider than other portions at the portion where the data line 62 and the gate line 22 cross each other, thereby forming the data line 62. Minimize disconnection.

Source and drain electrodes 65 and 66 of the thin film transistor are formed on the contact layer patterns 55 and 56, respectively, and are connected to the source electrode 65 on the gate insulating layer 30. Data lines 62 that cross and define pixels are formed in the vertical direction. The data lines 62, 65, and 66 include a data pad 64 connected to one end of the data line 62 to receive an image signal from the outside. In addition, the gate electrode 30 is connected to the pixel electrode lines 63 and 69 and the pixel electrode lines 63 and 69 which extend in the horizontal direction and overlap the common electrode lines 23 and 29 to form a storage capacitor. 21 and a pixel wiring including a pixel electrode 61 forming an electric field almost parallel to the substrate 10 for driving the liquid crystal molecules, and the pixel wirings 61, 63, and 69 are drain electrodes 66. ) Is electrically connected. In addition, a repair auxiliary line 68 overlapping the adjacent common electrode lines 23 and 29 of pixel rows adjacent to each other in the same layer as the data lines 62, 64, 65, and 66 on the gate insulating layer 30. It is formed in the vertical direction. As mentioned above, the storage wiring connection 84 (see FIG. 1) may also be formed on the gate insulating layer 30 in the same layer as the data wirings 62, 64, 65, and 66.

The passivation layer 72 is formed on the data wires 62, 64, 65, 66, the repair auxiliary line 68, and the semiconductor pattern 40 not covered by the passivation layer. ) Contact holes 74 exposing the common electrode lines 23 and 29, contact holes 75 and 78 exposing the gate pad 25 and the data pad 64, and contact holes exposing the data line 62, respectively. 76).

On the passivation layer 72, an auxiliary data pad 80 connected to and overlapped with the data line 62 through a contact hole 76 and an auxiliary data pad connected to the data pad 64 through a contact hole 78 ( An auxiliary data line including 88) is formed of a conductive material such as metal. In addition, an auxiliary gate electrode 85 connected to the gate pad 25 is formed on the passivation layer 72 through the contact hole 75, and the storage wirings of pixels adjacent to each other through the contact hole 74 are adjacent to each other. A common wiring connection 84 for electrically and physically connecting the 21, 23, and 29 is formed. Here, the auxiliary data lines 80 and 88 and the auxiliary gate pad 85 may be formed of a conductive material such as ITO or IZO to improve the reliability of the pad portion.

Most of the manufacturing method of the thin film transistor substrate for a liquid crystal display according to the second embodiment of the present invention is the same as the manufacturing method according to the first embodiment.

However, the common wirings 21, 23, and 29 are formed together with the gate wirings 22, 24, and 25, and the pixel wirings 61, 63, and 69 are formed together with the data wirings 62, 64, 65, and 66. The auxiliary data lines 80, 85, and 88 are formed on the passivation layer 72.

9 is a circuit diagram illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

As shown in FIG. 9, most of the structures are the same as in FIG.

However, both terminals of the storage capacitor C _st and the liquid crystal capacitor C _{LC are} connected to the pixel wirings 63 and 69 and the common wirings 23 and 29.

As in the exemplary embodiment of the present invention, the signal distortion of the sustain voltage can be minimized by connecting the sustain lines of pixels adjacent to each other through the sustain line connection part, thereby minimizing crosstalk and flicker defects. In addition, a failure in disconnection of the gate line or the data line can be repaired by providing a maintenance wiring connection portion or a repair auxiliary line.

Claims (11)

A gate wiring including a gate line formed in a row direction, A data line comprising a data line insulated from and intersecting the gate line and formed in a column direction; A pixel electrode formed in a pixel of a matrix defined by the intersection of the gate line and the data line, and receiving an image signal from the data line; A storage wiring overlapping the pixel electrode to form a storage capacitor, the storage wiring including a storage electrode line and a storage electrode connected to the storage electrode line; And a storage wiring connection portion for electrically connecting the storage wirings of the pixels adjacent to each other. In claim 1, A thin film transistor substrate for liquid crystal display devices, further comprising a repair auxiliary line whose both ends overlap with the sustain wiring of pixels adjacent to each other. In claim 2, And the sustain wiring connection portion is formed of the same layer as the pixel electrode. In claim 2, And the repair auxiliary line is formed of the same layer as the data line. In claim 1, The thin film transistor substrate for liquid crystal display device, wherein the sustain wiring and the gate wiring are formed of the same layer. In claim 1, The sustain wiring overlaps an edge portion of the pixel electrode. In claim 1, The pixel electrode has a shape in which a plurality of squares are connected to each other in a corner to divide and align the liquid crystal molecules, or a plurality of opening patterns having a rectangular or serrated shape. Board, A gate line formed on the substrate and including a gate line extending in a horizontal direction and transmitting a scan signal and a gate electrode connected to the gate line; A sustain wiring formed on the substrate and including a sustain electrode line extending in a horizontal direction and connected to the sustain electrode line; A gate insulating film covering the gate wiring and the sustain wiring; A semiconductor layer formed on the gate insulating film and formed of a semiconductor; A data line formed on the gate insulating layer and extending in a vertical direction to define the gate line and a pixel in a matrix form; a source electrode connected to the data line and formed on the semiconductor layer; A data line formed on the semiconductor layer and including a drain electrode facing the source electrode with respect to the gate electrode; A protective film covering the semiconductor layer, A pixel electrode formed in the pixel in connection with the drain electrode and overlapping the sustain wiring to form a storage capacitor; and And at least one of the storage wirings of the adjacent pixels includes a storage wiring connection portion electrically connected to each other. In claim 8, The thin film transistor substrate for a liquid crystal display device of which the sustain wiring connection portion and the pixel electrode are formed on the same layer. In claim 9, And the sustain wiring connection part and the pixel electrode are formed on the passivation layer. In claim 8, And a repair auxiliary line formed on the same layer as the data line and overlapping the storage line of the pixel row adjacent to each other.