TWI229215B - Thin film transistor array panel for liquid crystal display - Google Patents

Abstract

A plurality of gate lines extending in a horizontal direction are formed on an insulating substrate, and a data line is formed perpendicular to the gate line thereby defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line is formed in the horizontal direction, and a storage electrode connected to the storage electrode line and forming a storage capacitance by overlapping the pixel electrode is formed in the pixel. A redundant repair line both ends of which overlap the storage wire of the neighboring pixel, and a storage wire connection line connecting the storage wires of a neighboring pixel are formed. In this structure, because the storage wires of a neighboring pixel are connected to each other through the storage wire connection line, the variation of the voltage for the storage capacitance may be minimized, and this results in a reduction of its distortion, such that crosstalk and flicker problems are minimized.

Description

1229215 A7 B7 V. Description of the Invention (i Invention Back t U) Scope of the Invention The present invention relates to a thin film transistor array panel for a liquid crystal display. More particularly, the present invention relates to a thin film transistor array panel for a liquid crystal display, which has an independent storage circuit to form a storage capacitor. (b) Relevant technical description / Night crystal displays (LCDs) are one of the most widely used flat panel display (FpD) structures. The liquid crystal display has two panels-which have electrodes for an electric field-and a liquid crystal layer disposed between the two panels. The transmittance of incident light is controlled by the strength of the electric field applied to the liquid crystal layer. In the most widely used liquid crystal display, field generating electrodes (common and pixel electrodes) are individually formed on two panels, and one of the panels has a switching element such as a thin film transistor to control a voltage applied to the pixel electrode. Video signal. μ ° Typical liquid crystal displays use thin-film transistors, such as switching elements. The data lines and open lines intersect and define each other—the pixels in the matrix array are formed on a panel with a thin-film transistor arranged above. In addition, a pixel electrode receives an image signal from a data line via a thin film transistor and generates an electric field with a common electrode, which is formed in each pixel. On a thin film transistor array surface for a liquid crystal display — τ a " 'electrode lines are formed to cover the pixel electrodes via an insulating layer, and the electrodes together provide storage capacitance to improve the capacitance of the liquid crystal capacitor. 、 Common signal usually applied to the common electrode formed on the other panel = Shi O: \ 66 \ 66315-930206.DOC 4 This paper size applies the Chinese National Standard (CNS) Α4 specification (21〇χ 297 mm ) -4 1229215 A7 B7 V. Description of the invention The gate signal applied to the gate line is applied to the storage electrode line. However, during the operation of the liquid crystal display, the voltage applied to the storage electrode changes due to the continuous change of the image signal transmitted to the data line, and the resistance caused by the storage capacitor distort the potential of the storage electrode line. Due to crosstalk and wobble problems, this causes the liquid crystal capacitance to change and the overall image quality of the liquid crystal display to be reduced. SUMMARY OF THE INVENTION It is an object of the present invention to provide a thin-film electrical crystal panel for a liquid crystal display, which reduces distortion of a voltage applied to a storage electrode line, and minimizes crosstalk and wobble problems. Another object of the present invention is to provide a thin-film electrical panel for a liquid crystal display, which has a circuit structure to make it easy to repair open / short circuit defects of the circuit. These and other purposes are provided by forming more than one line according to the present invention, which connects at least the storage lines of adjacent pixels to each other, and forms a redundant repair line, which Each end covers a storage line of an adjacent pixel. In a thin film transistor array panel for a liquid crystal display according to the present invention, a gate line including a gate line is formed in a horizontal direction, and a gate line including a data line is connected to a tritium line. The intersecting wire edge _ material line is formed in the vertical direction, and the pixel electrode that receives the image signal through the data line is formed in a pixel. The pixel is formed by the intersection of the gate line and the data line: the line and the line connected to the storage electrode line. Storage power: The storage capacitor is formed by overlaying the pixel electrode, and the connection line connects at least the storage line of the adjacent pixel. Storage line O: \ 66 \ 66315-930206.DOC 4 -5-

V. Description of the invention

_ M lines can be formed. A Yu repair line 'whose end is covered by a storage layer of an adjacent pixel repair == The line is formed on the same line as the pixel electrode is formed on the same line as the _ line; the material is on the same layer, and it is staggered and looks like + In order to cover the edge portion of the pixel electrode with a material line, a plurality of square two liquid crystal molecules with rounded corners are connected. 4 or cross-shaped in order to align with a multi-domain structure. More specifically, in the horizontal direction, the inter-line formation of the line between _, check = scanning signal-including the library electrode formed on the insulating substrate, to the storage The storage of the electrode line is in the horizontal direction, and a semi-conductor θ made by connecting and closing the closed line with the library line m, and a semiconductor material, =: layer. The formation-data line includes a -data line, a conductive layer, and the poles extend to two =: connected to the data line and extend to the half-pole and -storage two-layer: Π :: purification layer. After forming-the pixel is connected to = to form a storage capacitor, and the storage line connection line is connected to the storage line connected to the adjacent pixel. :: is a pixel electrode storage line connection line 'and is formed on the purification layer. Moreover, a redundant repair line can be added, O: \ 66 \ 66315-930206.DOC 4 1229215 A7

It is formed on a layer opposite to the data line, and the two ends are covered with a storage line of an adjacent pixel. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this invention, illustrate one embodiment of the invention and, together with the description, serve to explain the principles of the invention. FIG. 1 is a circuit diagram of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention. Fig. 2 is a wiring diagram of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line of FIG. 2. 4A to 4D are sectional views of a thin film transistor array panel for a liquid crystal display according to a manufacturing method of a first embodiment of the present invention. 5A to 5G are cross-sectional views of a thin film transistor array panel for a liquid crystal display according to another manufacturing method of the first embodiment of the present invention. / FIG. 6 is a circuit diagram of a transistor array panel for a liquid crystal display according to a first embodiment of the present invention. Fig. 7 is a wiring diagram for a liquid crystal array panel according to a second embodiment of the present invention. Thin-film display of a display FIG. 8 is a cross-sectional view taken along line Vm-VIII of FIG. 7 and FIG. 9 is a circuit diagram for a liquid crystal array panel according to a second embodiment of the present invention. The details of the preferred embodiment & The figure shows the implementation of the present invention in different forms. The present invention will be described more fully below with reference to the accompanying drawings, a preferred embodiment of the invention. However, the present invention can be many O: \ 66 \ 66315-930206.DOC 4 1229215 V. Description of the invention (5 and should not be construed as limited to the embodiment presented here. In the figure, for clarity, the layer and The thickness of the region is exaggerated. The same number describes the same element. It can be understood that when an element such as a layer, region, or substrate is described as "on" another element, it can be directly on another element, or it can have Inserted components. For comparison, when an component is described as "directly on" another component, there are no inserted components.

FIG. 1 is a circuit diagram of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention. As shown in FIG. 1, in a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention, a plurality of gate lines 22 that transmit scanning signals and a plurality of data lines 62 that transmit display signals or image signals cross each other. . The gate line 22 and the data line 62 define a plurality of pixels in a matrix array. Each pixel includes a pixel electrode 82. An image signal is applied to a thin film transistor TFT through a data line. The gate, source, and drain of the thin-film transistor tft are individually connected to the gate line 22, the data line 62, and the pixel electrode U. Also, a plurality of storage electrode lines 26 and 28 are formed, which are parallel to the gate line 22 and receive a voltage, such as applying Common voltage to panel on one of the LCD displays (not shown). The storage electrode lines 26 and 28 have a two-wire structure and are connected to each other via a storage electrode 27, and they are parallel to the data line 62. The material lines 26, 27, and 28 provide a storage capacitor by covering the pixel electrode 82. A storage line connecting line 84 forms a straight direction, which at least electrically connects the adjacent pixel storage lines 26, 27, and 28, and forms a redundant repair. Its two ends are more abundant than the storage lines 26, 27, and 28 and the phase. Adjacent pixels. In the thin film transistor panel for liquid crystal display according to the present invention, because the storage lines 26, 27, and 28 of adjacent pixels are connected via the storage line connection line O: \ 66 \ 66315-930206.DOC 4 Mound standard _) A4 specification (2iqx297 male -8-1229215 A7! ~; _____ 5! __ 5. Description of the invention (6 "-84 and at least connected to each other, so it is used for storage capacitors-it is applied to the storage lines 26, 27 The voltage variation with 28 ° can be minimized, which results in reducing its distortion, thereby minimizing crosstalk and sloshing problems. In addition, in the thin film transistor panel for liquid crystal displays according to the present invention, the 'if gate The line 22 or the data line 62 is disconnected individually, and the disconnection of the line can be repaired using the redundant repair line 68, the storage lines 26, 27, and 28, and the storage line connection line 84. This will be described below with reference to FIG.

For example, if the data line 62 is broken at part A, the laser will overlap at the two ends of part A and overlap the data line 62 with the storage electrode lines 26 and 28, and the laser will overlap at the left side of part A. The storage electrode wires 26 and 28 and | part B of the remaining repair wires 68 are short-circuited. Therefore, the image signal transmitted to the broken data line 62 is connected again via the redundant repair line 68 and the storage electrode lines 26 and 28. At this time, the D part of the storage electrode wires 26 and 28 (X represents its external part on both sides of the part between B and C-to prevent the image signal from being transmitted to all the storage lines 26, 27, and 28. As another example, If the gate line 22 is broken at the part E, a laser is used to overlap the part 1 of the gate line 22 and the storage line connection line 84 to the right of the part E, and to overlap the redundant repair line 68 and storage at the left side of the part E. The 1? Part of the electrode wire 26 is individually short-circuited. Therefore, the scanning signal transmitted to the broken gate wire 22 is rewired via the redundant repair line 68, the storage electrode wire 26 and the storage line connection line 84. At this time, the The G portion (represented by X) of the external storage electrode line 26 on both sides of the portion between the F portions, the storage electrode 27 connected to the storage electrode line 26 between the F portion and the Η portion, and the F and storage electrode lines The storage line connecting line 84 between 28 is broken to prevent the scanning signal from being transmitted to all O: \ 66 \ 66315-930206.DOC 4 _ This paper is a national standard (CNS) Α4 specification (2ι () χ297 public love ) 1229215

The storage lines 26, 27 are ^ ^ ^ ^. A few repair lines 68 can only be used to repair the gate line 68 fish pins without using the storage line connection line 84. Here, redundant repair storage line connections ㈣ can be formed or ㈣ It is formed on the same layer of the two pixel electrodes 82 or the data lines 62 that are the same as each other. In accordance with the present invention, the 'storage lines 26, 27, and 28 are formed on the same line as the interval line M: a few repair lines 68 are formed On the same layer as the data line 62, the storage sub-channel connection line 84 is formed on the same layer as the pixel electrode 82. This will be described in detail with reference to Figs. 2 and 3. The diagram is according to the first embodiment of the present invention. Thin film electric LCD panel used for liquid crystal display] panel wiring diagram, and Figure 3 is a cross-sectional view taken along the line of Figure 2. As shown in Figures 2 and 3, such as Ming) or aluminum alloy, or Molybdenum-tungsten (MoW) gate (Cr), metal or conductive material and conductive circuit of ta (Ta) are formed on -edge base material 1G. _Gate line includes _Gate, line (or scanning signal line) ) 22 and-the gate electrode 24, ㈣22 extends in the horizontal direction and transmits a scanning signal, the gate electrode 24 is the gate line One part and one terminal of the thin film transistor. The gate line may include a gate pad connected to one end of the gate line 22 and transmitting a scanning signal from an external circuit to the gate line ^. A storage line includes a storage electrode line 26 and 28 and a storage electrode 27. The storage electrode lines 26 and 28 are parallel to the gate line 22 and have a double structure. The storage electrode 27 connects the storage electrode lines 26 and 28 to each other. There is an electrical waste such as a common voltage, which is applied To a common electrode (not shown) on the upper panel of the liquid crystal display. The storage circuits 26, 27 and 28 and a pixel electrode 82 provide storage capacitance together, which will be described later to improve the capacitance of the liquid crystal capacitor. -10 O: \ 66 \ 66315-930206.DOC 4 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 1229215 A7 B7 V. Description of the invention (8 Gate line areas 22 and 24 and storage line area 26, "and It may have a multi-layer structure and a single-layer structure. When the gate line areas 22 and 24 and the storage line areas 26, 27, and 28 are formed of a plurality of layers, it is preferable that one layer is made of a material having low electric conductivity. And other materials-special Is ιτ〇 (marine tin oxide)-made of a material with good contact for pixel electrodes. This is because the wiring for the pixel electrode is used with indium tin oxide to strengthen the electrical connection to the external pad The gate insulating layer 30 of silicon nitride (SiNx) is formed on and covers the gate line portions 22 and 24 and the storage circuit regions 26, 27, and 28. A semiconductor pattern 40 (conducted by a semiconductor such as hydrogenated amorphous silicon) (Made of) is formed on the gate insulating layer 30. Resistive contact layer patterns 55 and 56 (made of a material such as amorphous silicon, which is heavily doped with impurities such as filling) are formed on the semiconductor pattern 40. Sources and drains 65 and 66 made of conductive materials such as molybdenum or molybdenum tungsten, aluminum or aluminum alloys, and buttons are formed on the resistive contact layer pattern "and brother. A data line 62 is formed on the gate insulating layer 3. 2 and extending in the vertical direction of FIG. 2, it is connected to the source 65 and defines a pixel with the gate line 22. The data line areas 62, 65 and 66 may include a data pad, which is connected to the data line 62. One end. The data pad transmits the image signal from an external circuit to the data line 62. Moreover, a redundant repair line 68, each end of which covers the storage electrode lines 26 and 28 of adjacent pixel rows, is in the vertical direction of FIG. It is formed on the gate insulation layer 30 and on the same layer as the data line areas 62, 65, and 66. As described above, the storage line connection line 84 (refer to FIG. 1) may also be formed on the gate together with the redundant repair line 68. ,,, and the marginal layer 30, and in the same layer as the data line areas 62, 65, and 68 O: \ 66 \ 66315-930206.DOC 4 11 Scale suitable financial _ _ 准 (⑽) A4 size (2i (J_ X 297 mm) 1229215

1229215 A7 ~~ ________ B7 V. Description of the Invention (10 ~ " " --------- In order to increase the wide viewing angle of the LCD, the desire is that the LCD molecules are aligned in multiple fields. In order to obtain With this configuration, the pixel electrode 20 may have various pixel force-cut patterns. Here, the pixel electrode M may have a square with a plurality of = rounded corners, a square open pattern, a zigzag shape, or | Structure, by providing a fringe field, aligning the liquid crystal molecules. In order to achieve the best viewing angle, one unit of pixels is divided into four domains. In order to achieve stable segmentation alignment, the desires are, except in multiple fields Outside the boundary of the area, no undesired or uneven texture is produced, and preferably, the leader of the liquid crystal molecules in the adjacent area defined by the shape is not placed at 90 °. At this time, the leak The light is generated by undesired or uneven, literary and artistic, and the storage lines 26, 27, and 28 may have various patterns. Of course, the common electrode (not shown) opposite to the pixel electrode 82 may have various open patterns, It depends on the pattern of the pixel electrode 82. In the structure according to the present invention, the redundant repair line 68 or the storage line connecting line 84 is located in each pixel area, and may be located in each of the plurality of pixel areas. In these embodiments, A transparent indium tin oxide is used as an example of the material of the pixel electrode 82. However, the opaque conductive material IT0 can also be used in a reflective liquid crystal display. Next, the liquid crystal display according to the first embodiment of the present invention will be described with reference to the drawings. 4A to 4D are cross-sectional views of a thin-film transistor array panel for a liquid crystal display according to a manufacturing method of a first embodiment of the present invention. First, as shown in FIG. , Using a mask on an insulating substrate 10, depositing and patterning a conductive layer with low resistance O: \ 66 \ 66315-930206.DOC4 _ 13 _ This paper standard applies to Chinese national standards (CNS ) A4 specification (210X297 mm) 1229215 A7 I ------------ B7 V. Description of the invention ...-------- I 、 / Cheng 3 gate wire 22 and inter electrode 24 Area of the gate circuit, and contains = 28 and storage electrode area 27 (refer to FIG. H ′ as shown in FIG. 4B, a thin layer 1, made of an insulating material such as nitrided stone, 30, a marginal layer 30, a semiconductor made of such as amorphous stone, The semiconductor layer 40 made of materials and a resistive contact layer 50 made of a conductive material such as doped amorphous silicon are sequentially layered by a chemical vapor deposition method, and the semiconductor layer 40 and the resistive contact layer 50- Both are island-shaped—formed on the top of the gate electrode 24 and the opposite gate insulation layer 30 using a mask patterning process. Secondly, as shown in FIG. 4C, a conductor layer having a low resistance is deposited by a method such as sputtering, and is converted into a pattern through a photolithography process to form data lines 62, 65, and 66 (reference Figure 2) and redundant repair line 68. Then, the resistive contact layer 50 is etched using the data lines 62, 65, and 66 as a mask to divide the resistive contact layer patterns 55 and 56, and expose the semiconductor layer 40 between the source 65 and the drain 66. Secondly, as shown in FIG. 4D, a passivation layer 72 is formed by depositing an inorganic insulator or an organic insulator such as silicon nitride (SiNx) or silicon oxide, and is patterned with the gate insulating layer 30 to form individual exposure drains. The contact holes 71 and 74 of the pole 66 and the storage circuit%, 27 and 28 (refer to FIG. 2). Secondly, as shown in FIGS. 2 and 3, a transparent conductive layer of IZO or ITO is deposited and etched by photo-etching using a mask to form the pixel electrode 82 and the storage line connection line 84. On the other hand, referring to the figure, A method for manufacturing a thin film transistor array panel for a liquid crystal display using a four-screen method according to an embodiment of the present invention will be described. I O: \ 66 \ 66315-930206.DOC 4 -14_ This paper size applies to Chinese national standards ((:;) ^ 3) A4 size (210X 297 mm) 1229215

FIG. 1 is a sectional view of a thin film transistor array panel for a liquid crystal display according to another manufacturing method of the first embodiment of the present invention. Baixian ', as shown in FIG. 5A, a conductive layer with low resistance is deposited and patterned by etching the conductive layer with a dry or wet name through a photo-etching process to form open circuit areas 22 and 24, and a storage circuit area 26, 27 and 28. Next, as shown in FIG. 5A, a gate insulating layer 30, a semiconductor layer 40, and a resistive contact layer 50 are individually sequentially deposited by a method such as chemical vapor deposition (CVd). Then, a conductor layer 60 is deposited by a method such as sputtering, and a photoresist layer having a thickness of 1 to 2 micrometers is coated on the conductor layer 60. Thereafter, the photoresist layer is exposed and developed through a second mask to form photoresist patterns 112 and 114 'as shown in FIG. 5B. At this time, the first portion 114 of the photoresist pattern located between the source 65 and the drain 66, that is, a thin film transistor channel region C, as shown in FIG. 5B, is positioned above the portion A—where it will be The second portion U2 of the photoresist pattern forming a data line area 62, 65, 66 and a redundant repair line 68- is thinner. In addition, the third portion, or the remaining portion of the photoresist pattern located at the eighth portion, is thinner than the first portion. The thickness of the third part can be changed depending on the etching method. For example, when wet etching is used, the third portion may have a thickness of substantially zero, but when dry etching is used, the third portion may have a non-zero thickness. At this time, the thickness ratio between the first portion 114 and the second portion 112 depends on the etching conditions described later. However, it is preferable that the thickness of the first portion 114 is equal to or less than half of that of the second portion 112. There are many ways to change the thickness of the photoresist layer depending on the position, and the shape is O: \ 66 \ 66315-930206.DOC 4 This paper size is suitable for wealth ® ® Household Fresh (CNS) M size (21GX tear public director) -15 -1229215 V. Description of the invention (13 into a pattern such as a slit or a rafter, or by providing a bright layer on the curtain, you can control the amount of incident light. The size of the gap and the opaque part between the gaps is smaller than the resolution of the exposure device. When using a partially transparent layer, in order to reduce the amount of exposure, a mask containing a film can be used. The film has different light transmission properties, or has Variable thickness. When the photoresist layer is exposed to light passing through this mask, the polymer of the photoresist layer is decomposed by light. The exposure step is completed when the polymer of the directly exposed portion is completely decomposed. However, The polymer of the photoresist layer portion exposed through the slit pattern is not completely decomposed, because the amount of light emitted by a person is less than the number of directly exposed portions. The polymer of the photoresist layer portion is hardly exposed by the barrier layer Minute After the photoresist layer is developed, the portion of the photoresist layer that hardly decomposes remains, and a thinner portion remains below the portion where the exposure is less than the portion that receives the full exposure. However, if the exposure time is too long, the photoresist layer The entire polymer is decomposed. Therefore, this overexposure must be avoided. The formation of the thin portion 114 can be achieved by forming a photoresist layer made of a light-sensitive and reflowable material, so that the photoresist layer is exposed through a mask. The mask has individual substantially transparent portions and substantially opaque portions to form a photoresist pattern having a portion of zero and non-zero thickness, and a photoresist to flow back into the zero-exhaust portion to form a new photoresist pattern .

Referring back to FIG. 5B, the photoresist pattern 114 and the layer including the conductive layer 60, the resistive contact layer 50, and the semiconductor layer 40 underneath it are subjected to an etching process. When this process is completed, a data line and a redundant repair line, and below it are at A -16- O: \ 66 \ 66315-930206.DOC 4 This paper size itffi China National Solution (CNS) X 297 En) 5. The layer of the invention description (M) part can be left, and only the semiconductor layer is on the channel region C. In addition, the three layers 60, 50 and 40 in the remaining area B are removed from the gate insulating layer 30. As shown in FIG. 5C, the resistive contact layer 50 of the region B is exposed by removing the conductor layer 60 thereon. At this time, both wet and dry etching can be used, and it is preferable that the etching is performed under the condition that the conductor layer 60 is etched but the photoresist layers 112 and 114 are not etched. However, since it is difficult to achieve this in the case of the dry etching, the etching can be performed while the photoresist layers 112 and 114 are also etched. In this case, the first portion 114 may be made thinner than that of the wet etching case, so that the conductive layer 60 is not exposed. If the conductor layer 60 is made of molybdenum or molybdenum-tungsten alloy, aluminum or aluminum alloy, or button, then both dry and wet etching methods can be used. However, if the conductor layer 60 is made of chromium, wet etching is preferable because chromium is not easily removed by dry etching. CeNH03 can be used as a wet etchant for etching the chromium conductor layer 60. A mixed gas system of CF4 and HC1 or CF4 and O2 can be used to dry molybdenum or molybdenum tungsten conductor layer 60. In this case, the etching rate of the photoresist layer on the latter system is similar to that of conductor layer 60. Referring to FIG. 5C 'result', only the portions of the conductors 67 and 68 under the photoresist layers 112 and H4 in the channel area c and the portion a for the source / inverter and a redundant repair line are left, and in the area B The remaining portion of the conductive layer 60 is completely removed to break the resistive contact layer 50 below it. At this time, the conductor pattern 68 has the same wiring pattern as the data line regions 62, 65, 66 and the redundant repair region 68 ', but the source 65 and the non-electrode 66 are connected to each other. When the dry etching is used, the photoresist layers 112 and 114 are also etched to a certain thickness. Secondly, the exposed part of the resistive conductor layer 50 in the area B and O: \ 66 \ 66315-930206.DOC 4-17 _ under the figure 5D _ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Ϊ229215 V. Description of the invention (15) The semiconductor layer 40 is removed from the first part of the photoresist layer by dry etching. The etching condition can be: the photoresist pattern 1212 and 丨 14, the resistive connection layer 50 and the semiconductor layer 40 are all Etching (the semiconductor layer and the resistive contact layer have almost the same etch rate), but the gate insulating layer 30 cannot be etched. Preferably, the etch rates of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. This occurs For example, a mixed gas system of SF6 and HC1 or SF0 and 〇2. At this time, if the photoresist patterns U2 and 114 and the etching rate of the semiconductor layer 40 are almost the same, the thickness of the first portion H4 is equal to or smaller than the 帛 conductor layer 40 and the resistance contact layer 50. Then, as shown in FIG. 5D, the conductor pattern 67 is exposed by removing the first portion 114 of the channel region c, and the gate insulating layer 30 is removed by removing the resistance of the region 3. The contact layer 50 and the semiconductor layer 40 are exposed. At the same time, the thickness of the second portion 112 above the portion A is reduced due to etching. In addition, the complete semiconductor pattern is obtained as in this step. Then, the remaining photoresist layer on the conductor pattern 67 is subjected to ashes or electricity. The slurry is removed by etching. As shown in FIG. 5E, the conductor pattern 67 for the source / drain in the channel region and the resistive contact layer pattern 50 for the source / drain in FIG. 5E It is removed by etching. At this time, both the conductive pattern 67 and the resistive contact layer pattern 50 may be etched by a dry etching method, or the conductive pattern 67 may be etched by a wet etching method and the resistive contact layer pattern may be etched by a dry etching method. In the former case, it is preferable to use an etching condition having a large selectivity between the conductor pattern 67 and the resistive contact layer pattern 50. This is because it is difficult to detect the etching if the etching selectivity is not sufficiently large. End point, and control channel area c O: \ 66 \ 66315-930206.DOC 4 Vegetable paper size collapse specifications (21 × 7i ¥ r -18 1229215 A7 ._____ B7 V. Description of the invention (16) Thickness of the semiconductor pattern 40 around .This can be used, for example Sf6 and 〇2 mixed gas system was achieved. In the case of sequential wet and dry money engraving, the side of the conductor pattern 67 that received wet # engraving was also left, but the dry contact engraved resistance contact layer pattern 50 The sides are hardly engraved. Therefore, the outlines of these two patterns 67 and 50 are stepped. The mixed gas system of eh and 〇2 or (: 174 and 11 (:: 1) is an example of an etching gas system. The resistive contact layer pattern 50 and the semiconductor pattern 40 are etched. The semiconductor pattern 40 can also be formed to a uniform thickness by etching with a mixed gas system of%. At this time, as shown by the spell, the thickness of the semiconductor pattern 40 can be reduced, and the second portion 112 of the photoresist pattern is also etched to a certain thickness. The etching condition may also be set such that the gate insulating layer 30 is not etched, and it is preferable that the photoresist pattern is sufficiently thick without exposing the data lines 62, 65, 66 and the redundant repair line 68. As a result, the source 65 and the drain 66 are divided, and a complete data line region 62 65, 66 and several repair lines 68 and the complete contact layer patterns 55 and 56 below it are obtained. It-person, remove the remaining second part of the photoresist layer on the negative line. However, this removal of the second part 112 may be performed after the step of removing the conductor pattern 67 for the source / drain on the channel region c, and after removing the resistive contact layer pattern 5 under the conductor pattern 67. Before the steps. … This process can be performed using both wet etching and dry etching in sequence, or only dry etching. In the former case, the conductor layer of the region B is first removed by wet etching, and then the 'resistive contact layer and the semiconductor layer below it are removed by wet etching. At this time, the photoresist layer in the region C is consumed to a certain thickness, and the region. May leave O: \ 66 \ 66315-930206.DOC 4 1229215 V. Description of the invention (17 or no residual photoresist is left, which is roughly determined by the initial thickness of the photoresist layer in area c. When area C is left When the residual photoresist is lowered, the residual photoresist is removed by dust removal. Finally, the conductor layer in the area c is wet-etched to separate the source and the drain, and the resistive contact layer in the area C is removed by dry etching. In the latter For example, the conductive layer, the resistive contact layer, and the semiconductor layer of the region B are removed by dry etching. As in the former case, the region c may or may not leave a residual photoresist, and when the region C does have any residual photoresist At this time, the residual photoresist is removed by dust removal. Finally, the conductor layer in area c is dry-etched to separate the source and the drain, and the resistive contact layer in area C is removed by dry etching. Moreover, if the data line is etched , The semiconductor pattern, the contact layer pattern, and the data line can be completed in the same steps at once. That is, during the dry etching of the conductor layer, the resistive contact layer, and the semiconductor layer in the region B, the photoresist pattern 114 in the region c and its Underlying contact layer 50 dry etching And part of the photoresist pattern 112 in area a is engraved. Since the latter process uses only one etching method, although it is more difficult to achieve the correct etching condition, it is relatively simple. On the other hand, the former process is more complicated, but The advantage is that it is easy to achieve the correct money engraving condition. After forming the data line areas 62, 65, 66 and the redundant repair line 68 through the above steps, a passivation layer 70 is formed by a method such as chemical vapor deposition (cvd). As shown in FIG. 5F. Second, through a photo-etching process, a mask is used, and the passivation layer 70 is drawn along the gate insulation layer 30 to form individual contact holes 71 and 74 that expose the drain 66 and the storage line. As shown in Figure 5G. Secondly, as described above, a layer of IZ0 or a layer of IT0 is deposited with a curtain and O: \ 66 \ 66315-930206.DOC 4 As soon as the paper is closed, the money is closed. • 20 · 1229215 A7 B7

It is etched to form a pixel electrode 82 connected to the drain 66. At this time, a storage line connecting line 84 electrically connects the storage lines 26, 27, and 28 of the adjacent pixel through the contact hole 74. In this embodiment with the same effect, the thin film transistor can also be simplified by forming the data line regions 62, 65, 66 and redundant repair lines 68, the resistive contact layer patterns 55, 56 and the semiconductor pattern 40 through the photo-etching process. Manufacturing method of array panel. In this case, the semiconductor layer 40 and the resistive contact layer patterns 55 and 56 are formed based on the data lines 62, 65, and 66, and are different from the structures shown in Figs. The resistive contact layer patterns 55 and 56 have the same wiring patterns as the data line regions 62, 65 and 66. The semiconductor layer 40 has the same wiring pattern as the data line regions 62, 65, 66 and the resistive contact layer patterns 55, 56 except for the channel portion between the source 65 and the drain 66. Of course, a semiconductor layer and a resistive contact layer may remain under the redundant repair line 68. The thin film transistor array panel having storage line connecting lines according to the first embodiment can serve as one of the liquid crystal displays of a twisted nematic (TN) mode or a vertical alignment (VA) mode. Fig. 6 is a circuit diagram of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention. As shown in FIG. 6, the gate line 22 of the plural transmission scanning signal and the data line 62 of the plural transmission display No. or image # cross each other. The gate lines 22 and the data lines 62 define a plurality of pixels in a matrix array. Each pixel includes a thin film transistor TFT, a source 65 connected to the data line 62, and a drain 65 connected to the pixel 82. The thin film transistor TFT has a gate 24 connected to a gate line 22. O: \ 66 \ 66315-930206.DOC 4 This paper size is applicable to China National Standard (CNS) A4 specification (21〇χ 邠 7 mm) 1229215 A7 " -------------- B7 V. Description of the invention (19)-~ ---- Moreover, each pixel contains a storage capacitor Cu which generates a storage capacitor, and has two terminals of the pixel electrode 82 and the storage electrode lines 26 and 28, and a liquid production day. The NEC Valley liquid crystal capacitor Clc has two terminals of the pixel electrode 82 and a common electrode (not shown). The common electrode is formed on one of the upper panels of the liquid crystal display. At least the storage lines 26, which electrically connect adjacent pixels, and a plurality of storage line connection lines 84 are formed in a vertical direction. Here, the storage line connection lines 84 are formed in each pixel. On the other hand, referring to FIG. 7 and FIG. 8 illustrates that a thin-film transistor array surface used for a planar IPS liquid crystal display is inverted, and the surface has a pixel electrode and a common electrode, which are formed on the same panel to form an electrode field and then arrange liquid molecules. It may have a storage line connecting line which at least electrically connects the storage lines of adjacent pixels. FIG. 7 is a wiring diagram of a thin film transistor array panel for a liquid crystal display according to a second embodiment of the present invention, and FIG. A cross-sectional view taken along line VIII-VIII 'of Fig. 7. As shown in Figs. 7 and 8, a gate line and a common line of a metal or conductive material are formed on an insulating substrate 10. A gate line includes a gate line (or scan (Signal line) 22, a gate electrode 24 and a gate gasket, the gate line 22 extends in the horizontal direction of FIG. 7 and transmits a scanning signal, the gate electrode 24 is a part of the gate line 22 and a terminal of a thin film transistor, The gasket is connected to one end of the gate line 22 and transmits the scanning signal from an external circuit to the intermediate line 22. The common line includes common electrode lines 23 and 29 and-the common electrode 21, and the common line is parallel to the open line 22 and has a double Structure, the common electrode 21 is connected to the second electrode storage electrode lines 23 and 29. The storage electrode lines 29 and 29 and the pixel electrode lines 63 and 69 provide storage capacitance, which will be described later to improve the capacitance of the liquid crystal capacitor. O: \ 66 \ 66315-930206.DOC 4 1229215 A7 B7 Invention description (20) A gate insulating layer 30 of silicon nitride (SiNx) is formed in the gate circuit areas 22, 24, and 25 and the storage circuit areas 21, 23, and 29, and covers them. A semiconductor pattern 40 (made of a semiconductor such as argonized amorphous stone) is formed on the gate insulating layer 30. The resistive contact layer patterns 55 and 56 (made of such as amorphous stone-which is heavily doped with impurities such as phosphorus)- Made of a material) is formed on the semiconductor pattern 40. Here, the semiconductor pattern 40 extends in a vertical direction along a data line 62, which will be described later, and a portion of the semiconductor pattern 40-the gate line 22 and the data line 62 Overlapping on each other The different parts of the case 40 are wider to minimize the detachment of the data line 62. Sources and drain electrodes 65 and 66 made of a conductive material are formed on the resistive contact layer patterns 55 and 56. They are formed on the gate insulating layer 30 The data line 62 extending vertically in FIG. 7 is connected to the source 65 and defines a pixel from the gate line 22. The data line areas 62, 65, and 66 include a data pad 64 connected to the data line One end of 62. The data pad transmits the image signal from the external circuit to the data line 62. Moreover, a pixel circuit area is formed on the gate insulating layer 30, and the pixel circuit area includes the pixel electrode lines 63 and 69 and the pixel electrode 61, and the pixel The electrode lines 63 and 69 extend in the horizontal direction and provide a storage capacitor by overlapping the common electrode lines ^ and ". The pixel electrode 61 is connected to the pixel electrode lines 63 and 69 and is almost parallel to the base electrode together with the common electrode 21. The electric field of the material 10 controls the molecules of the liquid crystal display. The pixel line regions 61, 63, and 69 are connected to the drain M. A redundant repair line 68 whose two ends overlap the common electrode lines 22 and 29 of adjacent pixel rows can be formed on the gate insulating layer 在 in the vertical direction of FIG. 7 and in the areas 62, 65, and 66 with the data line On the same layer. As mentioned above, storage O: \ 66 \ 66315-930206.DOC -23- 1229215 A7 plant · 'B7 V. Description of the invention (21)'-Line connection line 84 (refer to figure 丨) can also be formed on the interlayer insulation layer , And on the same layer as I and the routing area 62, 64, 65 and 66. I. The purification layer M is formed on the data line areas 62, 64, 65, and 66 and the semiconductor pattern 40, and is not covered by the data line areas 62, material, "and". The passivation layer 72 has a contact hole 74, a contact hole 75 and 78, a contact hole 76 and a gate I, and a rim layer M. The contact hole 74 exposes the common electrode lines 23 and 29, and the contact holes 75 and 78 expose the gate pad 25 and Information pad 64. A redundant data line region, which is fabricated on a conductive material such as a metal, is formed on the passivation layer 72. The redundant data line includes a redundant data line 80 connected to the data line 62 via the contact hole 76, and a redundant data pad 88 connected to the data pad 64 via the contact hole. Further, the redundant gate pads | sheet 85, the common line connection line and the gate insulation layer 30 are formed on the passivation layer 72, the redundant gate pads 85 are connected to the gate pads 25 through the contact holes 75, and the common line connection lines 84 Adjacent common lines 21, 23 and 29 are connected via the contact hole 74 of the passivation layer 72. The redundant data lines 80 and 88 and the redundant gate pad 85 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZ0) to improve the reliability of the pad portion. Next, a method for manufacturing a thin film transistor array panel for a liquid crystal display device according to a second embodiment of the present invention will be described with reference to the drawings. The manufacturing method according to the second embodiment of the present invention is mostly the same as that of the first embodiment. However, the common lines 21, 23, and 29 are formed when the gate lines 22, 24, and 25 are formed, and the pixel lines 61, 63, and 69 are formed when the data lines 62, 64, 65, and 66 are formed. Then, redundant data lines 80, 85, and 88 are formed on the passivation layer 72. O: \ 66 \ 66315-930206.DOC 4 _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Ϊ229215 Ϊ229215 A7 B7 V. Description of the invention (22) ^-Figure 9 is based on this paper Circuit diagram of a thin film transistor array panel for a liquid crystal display according to a second embodiment of the invention. The structure according to the first embodiment is mostly the same as that according to the first embodiment of FIG. However, two terminals of the 'storage capacitor Cst and the liquid crystal capacitor Clc are individually connected to the pixel lines 63 and 69, and the common lines 23 and 29. In the present invention, 'by forming a storage line connecting line that at least interconnects the storage lines of adjacent pixels, the voltage variation of the storage capacitor can be minimized, which results in reduced distortion and minimizes crosstalk and sloshing problems. . Moreover, by using the 7L excess repair line and the storage line connection line, it is easy to repair the open circuit defect of the brake line and the data line. Typical preferred embodiments of the present invention have been disclosed in the drawings and the description, and although specific terminology is used, they are used for generality and illustration only, not for limitation. The materials of the present invention are disclosed in the scope of the following patent applications. O: \ 66 \ 66315-930206.DOC 4 -25-

Claims (1)

1229215 Su 089118479 Patent Acoustic Reading Chinese Application Patent Scope of Application Fan Gu j 2. 3. 4. 5. 6. 7.】 · A thin film transistor array panel for liquid crystal displays, including ... The road of the line is formed in the horizontal direction. The data line containing the data line, the shape line intersects with the line and is insulated; in the straight direction, the bei receives the material electrode through the data line. In the figure, the pixel is defined by the intersection of the data line and the data line; a storage line, a storage electrode with a material f pole line, the storage line is connected to the field storage electrode line capacitance; and the inner side is covered by the pixel electrode A storage element ": storage circuit connection line is formed, which connects at least the storage circuit to -adjacent image =: Fan and also includes-a storage circuit that covers the pixels. Line °: 1: Thin film transistor array panel of the second item in the range, in which the connection line is formed on the same layer as the pixel f⑽. The thin film transistor array panel of the second item: L item: = 1, wherein the redundant c-line is formed on a layer that is in phase with the data line. ::: The thin film transistor array panel of item i of the patent scope, the storage lines are formed on the same layer as the gate line. μStorage ^ No. of patent applications! In the thin film transistor array panel, the memory lines cover the edge portions of the pixel electrodes. Μ 啫 If the shape of the thin film transistor array panel electrode of item 1 of the scope of patent application is a plurality of square figure tombs with rounded corners, slaves W 丄,. 丄. Order f where the pixel squares are 0 and 8 ^, 丨Using the square, square pattern, zigzag, or cross of the dipper cone, ^ ^ ^ will be aligned with the multi-field structure 66315-931102.doc This paper is a national standard suitable for financial purposes (⑶ Ii) M specification (2ιχ; mm) 1229215 6. Apply for patent Fan Yuanjing molecule. 8. A thin-film transistor array panel for a liquid crystal display, comprising: an insulating substrate; and a green gate circuit formed on the insulating substrate, the gate circuit comprising a gate electrode connected to an open wire Thousands of directions and transmission of the scanning signal 'Idle, insulated storage line on the substrate, the storage line includes a storage electrode, a capacitor, a line and a gate insulation layer connected to the storage electrode line, which covers the gate line and The storage line · A semiconductor layer formed on a gate insulating layer and made of a semiconductor material; a data line including a data line, a deep source, and a drain; the data line is formed in a vertical direction, and the source is connected to The material is connected to the Beco line and extends on the semiconductor layer, and the drain electrode extends on the semiconductor layer. Eight touches u μ — and Xing and the gate-related source knife away from the material line and the gate line. The image of a matrix array is a passivation layer covering the semiconductor layer;-image: an electrode is formed in a pixel and is electrically connected to a drain electrode; the pixel electrode forms a storage by covering a storage line 9. The two storage capacitor lines and the connection lines connected to at least adjacent to the image of the storage line. For example, in the thin-film transistor array panel of the eighth patent application, the electrodes and the storage line connection lines are formed on the same layer. ^ ”, Claws such as the thin film transistor array panel under the scope of patent application No. 8 and redundant repair lines, each end of which covers the storage line of adjacent pixels, and is formed on the same layer as the data line. • 2- 66315-931102.doc This paper size applies Chinese National Standard (CNS) A4 specification (210X297 Gongcheng) 8 8 8 8 A BCD 1229215, patent application scope 11. Such as the thin film transistor array of the patent application scope item 9 A panel, in which a pixel electrode and a storage line connection line are formed on the passivation layer. 66315-931102.doc This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 1229215 Amendment Supplement No. 89118479 Patent Application Chinese Schematic Correction Page (January, 1989) ro Ln CD 1229215 Patent Application No. 089118479 Chinese Schematic f Page Change Year n 9_ssl 涵 oo ·· 1229215 No. 089118479 Zhuan Xin Chinese Schema # 赖 《页 mineral