KR20130067827A - Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for FFS(Fringe-Field Switching) liquid crystal display devices and a manufacturing method thereof are provided to form a gate line and a pixel electrode with a single mask, form an active layer, a source electrode, and a drain electrode with a single mask, and omit a process of forming a gate insulating layer, thereby manufacturing an FFS liquid crystal display device with four mask processes. CONSTITUTION: A gate line, a gate electrode(106b), and a pixel electrode(103a) are formed by etching the side parts of a first and a second transparent conductive material layer pattern part by using a photosensitive insulating layer pattern(107a) as an etching mask. An active layer(113a) and an ohmic contact layer(115a) are formed by successively etching a second conductive metal layer, an amorphous silicon layer containing impurities, and an amorphous silicon layer by using a first and a second pattern part of a second photoresist as an etching mask. A source electrode(117b) and a drain electrode(117c) are formed by etching the exposed part of the second conductive metal layer by using the first pattern part as an etching mask.

Description

AR-SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate and a manufacturing method for a FFS (Fringe Field Switching) type liquid crystal display device.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

Although not shown in the drawings, such a transverse electric field type liquid crystal display device has a color filter substrate and a thin film transistor substrate facing each other, and a liquid crystal layer interposed between the color filter substrate and the thin film transistor substrate.

A thin film transistor, a common electrode, and a pixel electrode are formed for each of a plurality of pixels defined in the thin film transistor substrate. At this time, the common electrode and the pixel electrode are formed on the same substrate in parallel to each other.

In the color filter substrate, a black matrix is formed at a portion corresponding to a gate wiring formed on the thin film transistor substrate, a data wiring and a thin film transistor formed at a crossing point of the wiring, and a color filter is provided corresponding to the pixel .

Therefore, the liquid crystal layer is driven by the horizontal electric field between the common electrode and the pixel electrode.

In the transverse electric field liquid crystal display device having the above configuration, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure luminance, but by design, the common electrode and the pixel are separated by a distance between the common electrode and the pixel electrode. Only a part of both ends of the electrode contribute to the improvement of brightness, and most areas result in light blocking.

Therefore, the proposed technique for maximizing such brightness improvement effect is FFS (Fringe Field Switching) technology. The FFS technique is characterized in that there is no color shift and a high contrast ratio can be obtained by precisely controlling the liquid crystal, so that it is possible to realize a high screen quality compared with a general transverse electric field technique.

The FFS liquid crystal display according to the related art having the advantage of realizing such high screen quality will be described with reference to FIGS. 1 to 2 as follows.

1 is a plan view of a thin film transistor substrate for a conventional FPS type liquid crystal display device.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a schematic cross-sectional view of a thin film transistor substrate for a FPS type liquid crystal display device according to the prior art.

In the conventional FFF type liquid crystal display, as shown in FIGS. 1 and 2, a plurality of gate wirings 15 extending in one direction and spaced in parallel to each other are disposed on the transparent insulating substrate 11. A gate electrode 15a extending from the gate wiring 15; A gate insulating film 17 formed on an entire surface of the substrate including the gate electrode 13a; A plurality of data lines 23 formed on the gate insulating layer 17 and defining pixel regions in an area intersecting the gate lines 13; It is provided at the intersection of the gate wiring 15 and the data wiring 23, and is spaced apart from the active layer 19 and the ohmic contact layer 21 on the gate electrode 15a and the gate insulating layer 17. And a thin film transistor T composed of a source electrode 23a and a drain electrode 23b.

Here, a large area pixel electrode 13 is disposed on the substrate 11 of the pixel region where the gate wiring 15 and the data wiring 23 intersect, and a gate insulating film (above the pixel electrode 23). 17 and a plurality of rod-shaped transparent common electrodes 29a and 29b spaced apart from each other with the passivation film 25 interposed therebetween.

In addition, the pixel electrode 13 overlaps the plurality of common electrodes 29a and passes through the pixel electrode contact hole 27 formed in the gate insulating layer 17 and the passivation layer 25. Is electrically connected to 23b).

In addition, the common electrode 29b is disposed to overlap the data line 23.

According to the above configuration, when a data signal is supplied to the pixel electrode 13 via the thin film transistor T, the common electrodes 29a supplied with the common voltage form a fringe field to form the fringe field. ) And the liquid crystal molecules arranged in the horizontal direction between the color filter substrate (not shown) are rotated by the dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

A method of manufacturing a fringe field (FFS) type liquid crystal display device according to the related art having the above configuration will be described in detail with reference to FIGS. 3A to 3F.

3A to 3F are cross-sectional views illustrating a manufacturing process of a conventional FPS type liquid crystal display device.

First, a transparent insulating substrate 11 defining a plurality of pixel regions including a switching region is prepared.

3A, an ITO layer (Indium Tin Oxide) (not shown), which is a first transparent conductive material, is deposited on the entire surface of the insulating substrate 11, and then the ITO layer is formed through a first mask process. By selectively patterning, a pixel electrode 13 having a large area is formed in the pixel region of the insulating substrate 11.

Subsequently, as illustrated in FIG. 3B, a first conductive metal layer (not shown) is deposited on the entire surface of the insulating substrate 11 including the pixel electrode 13 by a sputtering method, and then a photolithography technique is used. The first conductive metal layer (not shown) is selectively patterned through a two-mask process to form a gate wiring 15, a gate electrode 15a protruding from the gate wiring 15, and a gate pad electrically connected to an external driving circuit. (Not shown) is formed.

Next, as shown in FIG. 3C, a gate insulating film 17 is deposited on the entire surface of the substrate including the gate wiring 15. Then, an amorphous silicon layer (a-Si: H) (not shown) and impurities are deposited thereon. The amorphous silicon layer (n + or p +) (not shown) is sequentially deposited, and then the amorphous silicon layer (n + or p +) (not shown) containing the impurities is subjected to a third mask process using photolithography technology. And the amorphous silicon layer (a-Si: H) (not shown) are selectively etched to form an active layer 19 and an ohmic contact layer 21 on the gate insulating layer 17 on the gate electrode 15a. ).

Subsequently, as illustrated in FIG. 3D, a second conductive metal layer (not shown) is deposited on the gate insulating layer 17 including the ohmic contact layer 21 and the active layer 19.

Next, the second conductive metal layer (not shown), the ohmic contact layer 21, and the active layer 19 are selectively removed through a fourth mask process using a photolithography technique. The data wirings 23 perpendicularly intersecting, the source electrodes 23a and the drain electrodes 23b extending from the data wirings 23 are formed. At this time, when the data line 23 is formed, a data pad (not shown) extending from the data line 23 and electrically connected to the external driving circuit part is also formed.

Subsequently, as illustrated in FIG. 3E, a passivation film 25 is deposited on the entire substrate including the pixel electrode 23.

Next, the passivation layer 25 and the gate insulating layer 17 are selectively etched through a fifth mask process using a photolithography technique to expose the drain electrode 23b and the pixel electrode 13. A contact hole 27a is formed.

Subsequently, as illustrated in FIG. 3F, a second transparent conductive material layer (not shown) is deposited on the passivation layer 25 including the pixel electrode contact hole 27a and then the photolithography technique is used. The second transparent conductive material layer (not shown) may be selectively etched through a six mask process, and the drain electrode may be formed through the pixel electrode contact hole 27a together with the plurality of common electrodes 29a and 29b spaced apart from each other. A pixel electrode connection pattern 29c which electrically connects 23b with the pixel electrode 13 is formed.

In this manner, the thin film transistor array substrate manufacturing process for the F-type liquid crystal display device according to the prior art is completed.

Subsequently, although not shown in the drawing, a FPS type liquid crystal display device is manufactured by performing a process of filling a liquid crystal layer between the array substrate and the color filter substrate together with a color filter substrate manufacturing process.

As described above, according to the method for manufacturing an array substrate of a FPS type liquid crystal display device according to the prior art, the manufacturing process is performed because six times the mask process is performed during the manufacture of the array substrate for a FPS type liquid crystal display device. The time is increased and the cost of the mask process is increased. In particular, in the conventional FFS (French Field Switching) type liquid crystal display, the number of mask processes is increased by using a separate mask to form the active layer and the pixel electrode.

In addition, according to the method of manufacturing an array substrate of the FSF type liquid crystal display device according to the related art, a gate insulating film and a passivation film are formed between a large area pixel electrode and a plurality of common electrodes. This decreases.

In addition, according to the method of manufacturing an array substrate of the FSF type liquid crystal display device according to the related art, there is a fear that the ITO layer constituting the pixel electrode may be damaged when the gate insulating film is deposited on the entire surface of the substrate including the pixel electrode.

Accordingly, the present invention is to solve the problems of the prior art, it is possible to reduce the number of manufacturing processes, low power consumption by eliminating the process of forming a gate insulating film when manufacturing an array substrate for FPS (FFS) type liquid crystal display device An array substrate for a FPS type liquid crystal display device capable of increasing transmittance and a method of manufacturing the same are provided.

According to an aspect of the present invention, there is provided an FSF type liquid crystal display array substrate comprising: a gate wiring formed in one direction on one surface of a transparent insulating substrate and a gate electrode extending from the gate wiring; A photosensitive insulating film formed on the surface of the gate electrode to surround the gate electrode; An active layer formed on the insulating substrate including the photosensitive insulating layer, and a source electrode and a drain electrode formed on the active layer and spaced apart from each other; A data line perpendicular to the gate line; A pixel electrode formed in the pixel region of the insulating substrate formed by crossing the gate wiring and the data wiring; A passivation film formed on an entire surface of the insulating substrate including the pixel electrode and the data wiring and exposing the pixel electrode and the drain electrode; And a pixel electrode connection pattern formed on the passivation layer and electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display (FFS) type liquid crystal display device, comprising: a gate line and a gate extending from the gate line in one direction on one surface of a transparent insulating substrate having a pixel area defined therein; Forming an electrode and forming the pixel electrode in the pixel region; Forming a photosensitive insulating film surrounding the gate electrode on a surface of the gate electrode; Forming a data interconnection perpendicular to the gate interconnection with an active layer and a source electrode and a drain electrode spaced apart from each other on the insulation substrate including the photosensitive insulating layer; Forming a passivation film exposing the pixel electrode and the drain electrode on an entire surface of the insulating substrate including the pixel electrode and the data wiring; And forming a pixel electrode connection pattern on the passivation layer to electrically connect the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode.

In fabricating an array substrate for a fs type liquid crystal display device according to the present invention, a gate wiring and a pixel electrode, an active layer, a source electrode and a drain electrode can be formed using one mask, respectively, to form a gate insulating film. By omitting the process, the FPS type liquid crystal display device can be manufactured by using a four-time mask process instead of the conventional six-time mask process, thereby reducing the mask cost, thereby reducing the manufacturing process cost, and thus shortening the manufacturing process time. In particular, a process of stripping the photo SGI by using a photosensitive insulating film, for example, photo SGI (photo SGI) instead of a photoresist during the patterning process for forming the gate wiring, and a process of forming the gate insulating film are omitted. Therefore, the process time and the number of manufacturing processes are thereby shortened.

In addition, in the fabrication of the FPS type liquid crystal display array substrate according to the present invention, since the gate insulating film formed on the large area of the pixel electrode is omitted, the total thickness of the insulating film between the pixel electrode and the common electrode becomes thinner. Low power consumption is realized and transmittance is improved.

In the manufacturing of the FPS type liquid crystal display array substrate according to the present invention, since the gate insulating film deposition process is omitted, the ITO damage of the pixel electrode portion is eliminated.

1 is a plan view of a thin film transistor substrate for a conventional FPS type liquid crystal display device.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a schematic cross-sectional view of a thin film transistor substrate for a FPS type liquid crystal display device according to the prior art.
3A to 3F are cross-sectional views illustrating a manufacturing process of a conventional FPS type liquid crystal display device.
4 is a plan view of a thin film transistor substrate for a FPS type liquid crystal display device according to the present invention.
FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4 and is a schematic cross-sectional view of a TFT substrate for a liquid crystal display device according to the present invention.
6A to 6R are cross-sectional views illustrating a manufacturing process of a FPS type liquid crystal display device according to the present invention.

Hereinafter, an array substrate for a FPS type liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a thin film transistor substrate for a FPS type liquid crystal display device according to the present invention.

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4 and is a schematic cross-sectional view of a TFT substrate for a liquid crystal display device according to the present invention.

As shown in FIGS. 4 to 5, an array substrate for a FPS type liquid crystal display device according to the present invention includes a gate wiring 106a formed on one surface of the transparent insulating substrate 101 in one direction and the gate wiring. A gate electrode 106b extending from 106a; A photosensitive insulating film 107a formed on the surface of the gate electrode 106b so as to surround the gate electrode 106b; An active layer 113a formed on the insulating substrate 101 including the photosensitive insulating layer 107a and a source electrode 117b and a drain electrode 117c formed on the active layer 113a and spaced apart from each other; A data line 117a perpendicularly intersecting with the gate line 106a; A pixel electrode 103 formed in the pixel region of the insulating substrate 101 where the gate wiring 106a and the data wiring 117a cross each other; A passivation film 123 formed on the entire surface of the insulating substrate 101 including the pixel electrode 103a and the data wiring 117a and exposing the pixel electrode 103a and the drain electrode 117c; A pixel electrode formed on the passivation layer 123 and electrically connecting the pixel electrode 103a and the drain electrode 117c with a plurality of common electrodes 129a and 129b overlapping the pixel electrode 103a. It is configured to include a connection pattern (129c).

Here, the gate electrode 106b including the gate wiring 106a has a stacked structure of a transparent conductive material layer pattern 103b and a conductive metal layer pattern 105b. In this case, the transparent conductive material layer pattern 103b is formed of any one selected from a group of transparent materials including indium tin oxide (ITO) and indium zinc oxide (IZO). In the present invention, a case where ITO (Indium Tin Oxide) is used as the transparent conductive material layer pattern 103b will be described.

In addition, the conductive metal layer pattern 105b may be formed of aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), and molybdenum (MoTi). ), And at least one selected from the group of conductive metals including copper / mortitanium (Cu / MoTi). In the present invention, a case where copper (Cu) is used as the conductive metal layer pattern 105b will be described as an example.

The pixel electrode 103a is formed on the entire pixel region of the insulating substrate 101 corresponding to a space spaced apart from the gate wiring 106a and the data wiring 117a. In this case, the pixel electrode 110 is formed of any one selected from a group of transparent materials including indium tin oxide (ITO) and indium zinc oxide (IZO). In the present invention, a case where ITO (Indium Tin Oxide) is used as the transparent conductive material layer pattern 103b will be described.

In addition, the common electrodes 129a and 129b overlap the pixel electrode 103a with the passivation layer 123 interposed therebetween. In this case, the common electrode 129a overlaps the pixel electrode 103a of the large area disposed in the pixel region, and the common electrode 129b overlaps the data wiring 117a. The common electrode 129a may be formed of any one selected from a group of transparent materials including indium tin oxide (ITO) and indium zinc oxide (IZO). In the present invention, a case where ITO (Indium Tin Oxide) is used as the material of the common electrodes 129a and 129b will be described.

The pixel electrode connection pattern 129c electrically connects the pixel electrode 110 and the drain electrode 117d through the pixel electrode contact hole 127.

Accordingly, the common electrodes 129a and 129b are supplied with reference voltages for driving the liquid crystals, that is, common voltages, to each pixel. The common electrodes 129a and 129b overlap a large area of the pixel electrode 103a with the passivation layer 123 interposed therebetween to form a fringe field in each pixel area.

In addition, as shown in FIG. 5, the thin film transistor T surrounds the gate electrode 106b extending in the vertical direction from the gate wiring 106a formed on the insulating substrate 101 and the gate electrode 106b. The photosensitive insulating layer 107a, the active layer 113a, and the ohmic contact layer 115a are formed of a source electrode 117b and a drain electrode 117c spaced apart from each other by the channel region of the active layer 113a. In this case, the photosensitive insulating layer 107a may be selected from any one of photosensitive organic insulating materials including a photo solgi gate insulator (SGI), photo-acryl (PAC), and PSG. In addition, the photosensitive insulating layer 107a is used as a gate insulating layer of the thin film transistor.

A gate pad (not shown) is formed at one end of the gate wiring 106a to extend from the gate wiring 106a to be connected to an external driving circuit unit.

Further, at one end of the data line 117a, a data pad (not shown) extending from the data line 117a and connected to the external driving circuit unit is formed.

Although not shown in the drawing, a lower alignment layer (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 129a and 129b.

A black matrix (BM) 143 for blocking light from being transmitted to an area excluding a pixel area on the color filter substrate 141 spaced apart from and bonded to the thin film transistor substrate, that is, the insulating substrate 101. Is formed.

In addition, color filter layers 145 of red, green, and blue colors are formed in the pixel region of the color filter substrate 141. In this case, the black matrix 143 is formed on the color filter substrate 141 between the color filter layers 145 of red, green, and blue colors.

Here, when the color filter substrate 141 and the insulating substrate 101 which is the thin film transistor substrate are bonded together, the black matrix 143 is an area excluding a pixel region of the insulating substrate 101, for example, a thin film transistor ( T), the gate wiring 106a and the data wiring 117a are disposed to overlap with each other.

Although not shown in the drawings, an upper alignment layer (not shown) is formed on the color filter layer 145 to arrange the liquid crystals in a predetermined direction.

In this way, when a data signal is supplied to the pixel electrode 110 through the thin film transistor T, a fringe field is formed between the common electrodes 129a and 129b and the pixel electrode 103a supplied with the common voltage. The liquid crystal molecules arranged in the horizontal direction between the insulating substrate 101 and the color filter substrate 141 are rotated by dielectric anisotropy, so that the light transmittance of the liquid crystal molecules passing through the pixel region varies depending on the degree of rotation. As a result, gray scales are realized.

Therefore, according to the present invention, since the photosensitive insulating film used as the gate insulating film is formed only on the surface of the gate electrode and not on the large area of the pixel electrode, the total thickness of the insulating film between the pixel electrode and the common electrode becomes thinner. Low power consumption is realized and transmittance is improved.

Meanwhile, a method of manufacturing an array substrate for a FPS type liquid crystal display device according to the present invention having the above configuration will be described with reference to FIGS. 6A to 6R.

6A to 6R are cross-sectional views illustrating a manufacturing process of an array substrate for a FPS type liquid crystal display device according to the present invention.

As shown in FIG. 6A, a plurality of pixel areas including a switching area are defined on the transparent insulating substrate 101, and the first transparent conductive material layer 103 and the first conductive layer are formed on the insulating substrate 101. The metal layer 105 is sequentially deposited by the sputtering method. Here, the first transparent conductive material layer 103 may be formed of any one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Here, the case where ITO (Indium Tin Oxide) is used as the first transparent conductive material layer 103 will be described as an example.

In addition, the first conductive metal layer 205 may include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), or molybdenum. At least one selected from the group of conductive metals, including titanium (MoTi), copper / mortitanium (Cu / MoTi), is used. Here, the case where copper (Cu) is used as the first conductive metal layer 205 will be described as an example.

Next, a photosensitive insulating layer 107 is formed on the first conductive metal layer 105. At this time, the photosensitive insulating layer 107 is selected from any one of the photosensitive organic insulating material including a photo SGI (photo Soluble Gate Insulator), PAC (photo-acryl), PSG. In addition, the photosensitive insulating layer 107a is used as a gate insulating layer of the thin film transistor.

Subsequently, an exposure process is performed on the photosensitive insulating layer 107 through a first mask process using a first diffraction mask 109 including the light blocking part 109a, the transflective part 109b, and the transmission part 109c. In this case, the first diffraction mask 109 is a mask that can control the transmittance using a diffraction phenomenon of light, and includes a slit mask and a half-ton mask. Here, the case where the slit mask is used as the diffraction mask will be described as an example.

The light blocking portion 109a of the first diffraction mask 109 is positioned above the photosensitive insulating layer 107 corresponding to the gate wiring, the gate electrode and the gate pad forming region, and is half of the first diffraction mask 109. The transmissive part 109b is positioned above the photosensitive insulating layer 107 corresponding to the pixel electrode formation region.

Next, as shown in FIG. 6B, the photosensitive insulating layer 107 may be selectively removed through the developing process, and then the photosensitive insulating layer pattern corresponding to the gate wiring, the gate electrode, and the gate pad forming region may be formed. 107a and a dummy photosensitive insulating film pattern 107b corresponding to the pixel electrode formation region are formed.

At this time, since the photosensitive insulating layer pattern 107a is in a state where light is not transmitted, the photosensitive insulating layer 107 is kept intact, but the dummy photosensitive insulating layer pattern 107b is partially removed by transmitting a portion of light. That is, the dummy photosensitive insulating layer pattern 107b has a thickness thinner than that of the photosensitive insulating layer pattern 107a.

Subsequently, as shown in FIG. 6C, the first transparent conductive material layer 103 and the first conductive metal layer 105 are selectively formed using the photosensitive insulating layer pattern 107a and the dummy photosensitive insulating layer pattern 107b as an etching mask. First wet etching to form a first metal layer pattern portion (not shown) and a first transparent conductive layer pattern portion (not shown) in the gate wiring forming region, and a second metal layer pattern portion 105b and in the gate electrode forming region; A second transparent conductive layer pattern portion 103b is formed, and a third metal layer pattern portion 105a and a third transparent conductive layer pattern portion 103a are simultaneously formed in the pixel electrode formation region. In this case, the third transparent conductive layer pattern part 103a is used as a pixel electrode.

At this time, the first transparent conductive material layer 103 and the first conductive metal layer 105 during the first wet etching, the copper layer (Cu) and the first conductive used as the first transparent conductive material layer 103 An etching solution capable of simultaneously etching the ITO layer used as the metal layer 105 is used.

Therefore, during the first wet etching of the first transparent conductive material layer 103 and the first conductive metal layer 105 using the etching solution, the first transparent conductive material layer 103 and the first conductive metal layer ( Since the etching degree of 105 is different, the side portion of the first transparent conductive material layer 103 is formed to protrude from the side portion of the first conductive metal layer 105.

6C and 6D, an ashing process is performed to cover the first metal layer pattern portion (not shown) and the first transparent conductive layer pattern portion (not shown) in the gate wiring forming region. A portion of the photosensitive insulating layer pattern 107a formed on the second metal layer pattern portion 105b and the second transparent conductive layer pattern portion 103b in the gate electrode formation region is etched, and the first portion in the pixel electrode formation region is etched. The transparent conductive layer pattern portion, that is, the dummy photosensitive insulating layer pattern 107b formed on the pixel electrode 103a and the third metal layer pattern portion 105a is completely etched to form the third conductive metal layer pattern in the pixel electrode formation region. 105a) Expose the top surface.

At this time, through the ashing process, the photosensitive insulating layer pattern 107a is etched by a predetermined thickness so as to overlap the upper surface of the first metal layer pattern portion (not shown) and the second metal layer pattern portion 105b, but the first transparent conductive layer Since the side portions of the pattern portion (not shown) and the second transparent conductive layer pattern portion 103b do not overlap, the side portions of the first transparent conductive layer pattern portion (not shown) and the second transparent conductive layer pattern portion 103b are external. Will be exposed.

Subsequently, as shown in FIG. 6E, the exposed third conductive metal layer pattern 105a and the pixel electrode (below) are used as an etch mask using the photosensitive insulating layer pattern 107a etched a part of the thickness by the ashing process. The sidewalls of the exposed first transparent conductive material layer pattern portion (not shown) and the second transparent conductive material layer pattern portion 103b together with 103a are etched by a second wet etching process, thereby forming the gate wiring forming region and Gate wirings (not shown, see 106a in FIG. 4) and gate electrodes 106b are formed in the gate electrode formation region, respectively, and pixel electrodes 103a are formed in the pixel electrode formation region. In this case, the second wet etching process is performed until the exposed dummy conductive metal layer pattern 105a is completely etched.

In addition, the gate wiring (not shown) (see 106a of FIG. 4) has a stacked structure of the first wet-etched first transparent conductive material layer pattern portion (not shown) and the first conductive metal layer pattern portion (not shown). The gate electrode 106b has a stacked structure of a second transparent conductive material layer pattern portion 103b and a second conductive metal layer pattern portion 105b. The pixel electrode 103a is formed of a second wet conductive etched third transparent conductive material layer pattern portion.

6E and 6F, a reflow process is performed, and the side surface portion of the remaining photosensitive insulating layer pattern 107a flows down to the side surface of the gate electrode 106b to be cured. The entire surface of the electrode 106b is covered. In this case, the reflow process is performed by heat treatment at a temperature of 100 to 300 ℃. In addition, the photosensitive insulating layer pattern 107a covering the entire surface of the gate electrode 106b is used as the gate insulating layer of the thin film transistor.

Subsequently, as shown in FIG. 6G, an amorphous silicon layer (a-Si: H) 113 and an amorphous silicon layer including impurities are formed on the entire surface of the substrate including the photosensitive insulating layer pattern 107a and the pixel electrode 103a. n + or p +) 115 and the second conductive metal layer 117 are sequentially stacked.

At this time, the amorphous silicon layer (n + or p +) 115 containing the amorphous silicon layer (a-Si: H) 113 and the impurities is deposited by a chemical vapor deposition (CVD) method, 2 conductive metal layer 117 is deposited by a sputtering method.

Although only the chemical vapor deposition method and the sputtering method are described above as the deposition method, other deposition methods may be used if necessary. The second conductive metal layer 117 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten At least one selected from the group of conductive metals including titanium (MoTi), copper / moly titanium (Cu / MoTi) is used.

Subsequently, as illustrated in FIG. 6H, a photoresist having high transmittance is coated on the second conductive metal layer 117 to form a first photoresist layer 119.

Next, an exposure process is performed on the first photoresist layer 119 through a second mask process using a second diffraction mask 121 including the light blocking part 121a, the transflective part 121b, and the transmitting part 121c. . In this case, the second diffraction mask 121 is a mask that can control the transmittance using a diffraction phenomenon of light, and includes a slit mask and a half-ton mask. Here, the case where the slit mask is used as the diffraction mask will be described as an example.

In this case, the light blocking portion 121a of the second diffraction mask 121 is located above the second photoresist layer 119 corresponding to the data pad formation region together with the data wiring, source electrode and drain electrode formation regions. The transflective portion 121b of the second diffraction mask 121 is positioned above the second photosensitive layer 119 corresponding to the channel formation region of the thin film transistor.

Subsequently, as illustrated in FIG. 6I, the second photoresist layer 119 is etched through the exposure process, and then the first pattern portion 119a corresponding to the data wiring, source electrode, and drain electrode formation regions is formed. ) And a second pattern portion 119b corresponding to the channel formation region.

At this time, since the first pattern portion 119a does not transmit light, the thickness of the second photoresist layer 119 is maintained. However, since the second pattern portion 119b transmits a part of the light, do. That is, the second pattern portion 119b is thinner than the first pattern portion 119a.

Next, the second conductive metal layer 117, the amorphous silicon layer 115 including impurities, and the amorphous silicon layer using the first pattern portion 119a and the second pattern portion 119b of the second photoresist layer as an etch mask. The 113 is sequentially etched together with the data line 106a and the data pad (not shown) perpendicularly intersecting with the gate line 106a and on the gate insulating layer 111 corresponding to the gate electrode 105c. The active layer 113a and the ohmic contact layer 115a are formed.

Subsequently, as illustrated in 6j, an ashing process may be performed to form a second pattern portion corresponding to the channel formation region along with a portion of the first pattern portion 119a corresponding to the source electrode and drain electrode formation region. Completely remove 119b). In this case, an upper surface of the second conductive metal layer 117 overlapping the channel region is exposed to the outside.

Next, the exposed portions of the second conductive metal layer 117 are etched using the first pattern portion 119a from which the portions are removed, and the source electrode 117b and the drain electrode 117c are separated from each other. Form. At this time, a portion of the ohmic contact layer 115a on the channel region is exposed to the outside.

Subsequently, as shown in FIG. 6K, the ohmic contact layer 115a exposed between the source electrode 117b and the drain electrode 117c is also etched and spaced apart from each other. At this time, a channel region is formed in the active layer 113a under the etched ohmic contact layer 115a.

Next, as shown in FIG. 6L, the first pattern portion 119a of the second photoresist film is removed, and then an inorganic insulating material or organic insulating material made of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate. A material is deposited to form a passivation film 123, and then a photoresist having high transmittance is applied on the passivation film 123 to form a second photoresist film 125. Here, the second photoresist film 125 is formed. For example, an inorganic insulating material made of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is used as the passivation film 123. Before forming the passivation film 123, the substrate is formed. A passivation film may be thinly deposited on the entire surface.

Subsequently, as illustrated in FIG. 6M, the second photoresist layer 125 is patterned to form a second photoresist layer pattern 125a by performing exposure and development processes by a third mask process using an exposure mask (not shown). do.

Next, as shown in FIG. 6N, the passivation layer 123 and the gate insulating layer 111 below are selectively etched using the second photoresist layer pattern 125a as a mask to form the drain electrode 117c and the pixel. The pixel electrode contact hole 127 exposing the electrode 103a is formed. Although not shown in the drawing, the gate pad contact hole (not shown) exposing the gate pad (not shown) and the data pad contact exposing the data pad (not shown) are formed when the pixel electrode contact hole 127 is formed. Holes (not shown) are also formed.

Subsequently, as shown in FIG. 6O, the third photoresist layer pattern 125a is removed, and the second transparent conductive material layer 129 is disposed on the passivation layer 123 including the pixel electrode contact hole 127. It deposits by magnetron sputtering. At this time, as the second transparent conductive material layer 129, any one selected from a transparent material group including indium tin oxide (ITO) and indium zinc oxide (IZO) is used.

Next, a photoresist having high transmittance is coated on the second transparent conductive material layer 129 to form a third photoresist layer 131.

Subsequently, as illustrated in FIG. 6P, the fourth photoresist layer pattern 131a is selectively patterned by performing an exposure and development process through a fourth mask process using an exposure mask (not shown) to selectively pattern the fourth photoresist layer 131. To form.

Next, as shown in FIG. 6Q, the second transparent conductive material layer 129 is selectively etched using the third photoresist pattern 131a as an etch mask, and thus the plurality of common electrodes 129a and 129b are spaced apart from each other. And a pixel electrode connection pattern 129c for electrically connecting the pixel electrode 103a and the drain electrode 117c through the pixel electrode contact hole 127 at the same time. In this case, when the plurality of common electrodes 129a and 129b and the pixel electrode connection pattern 129c are formed, although not shown in the drawing, the gate pad contact hole (not shown) and the data pad contact hole (not shown) are provided. A gate pad connection pattern (not shown) and a data pad connection pattern (not shown) respectively connected to the gate pad (not shown) and the data pad (not shown) are also formed.

Subsequently, although not shown in the drawing, the third photoresist layer pattern 131a is removed, and a lower alignment layer (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 129a and 129b, thereby f. The manufacturing process of the array substrate for the FPS type liquid crystal display device is completed.

Next, as shown in FIG. 6R, light is blocked from being transmitted to an area excluding the pixel area on the thin film transistor substrate, that is, the color filter substrate 141 spaced apart from each other and bonded to the insulating substrate 101. To form a black matrix (BM) 143.

Next, a color filter layer 145 of red, green, and blue colors is formed in the pixel region of the color filter substrate 141. At this time, the black matrix 143 is located on the color filter substrate 141 between the red, green, and blue color filter layers 145.

At this time, the black matrix 143 is an area except for the pixel region of the insulating substrate 101 when the color filter substrate 141 and the insulating substrate 101 that is the thin film transistor substrate are bonded together, for example, a thin film transistor. (T), the gate wiring 106a and the data wiring 117a are disposed so as to overlap.

Next, although not shown in the drawing, a process of manufacturing a color filter array substrate is completed by forming an upper alignment layer (not shown) on the color filter layer 145 to arrange liquid crystals in a predetermined direction.

Subsequently, although not shown in the drawing, the liquid crystal layer 151 is formed between the insulating substrate 101 and the color filter substrate 141 to manufacture a FPS type liquid crystal display device according to the present invention.

As described above, in fabricating an array substrate for a FPS type liquid crystal display device according to the present invention, a gate wiring and a pixel electrode, an active layer, a source electrode and a drain electrode can be formed using one mask, respectively. By omitting the process of forming the gate insulating film, it is possible to manufacture the FPS type liquid crystal display device by using the four mask process instead of the conventional six mask process, thereby reducing the mask cost and reducing the manufacturing process cost, and thus the manufacturing process time. This is shortened. In particular, a process of stripping the photo SGI by using a photosensitive insulating film, for example, photo SGI (photo SGI) instead of a photoresist during the patterning process for forming the gate wiring, and a process of forming the gate insulating film are omitted. Therefore, the process time and the number of manufacturing processes are thereby shortened.

In addition, in the fabrication of the FPS type liquid crystal display array substrate according to the present invention, since the gate insulating film formed on the large area of the pixel electrode is omitted, the total thickness of the insulating film between the pixel electrode and the common electrode becomes thinner. Low power consumption is realized and transmittance is improved.

In the manufacturing of the FPS type liquid crystal display array substrate according to the present invention, since the gate insulating film deposition process is omitted, the ITO damage of the pixel electrode portion is eliminated.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

101: insulating substrate 103a: pixel electrode
106a: gate wiring 106b: gate electrode
107a: photosensitive insulating film 113a: active layer
115a: Ohmic contact layer 117a: Data wire
117b: source electrode 117c: drain electrode
123: passivation film 127: pixel electrode contact hole
129a and 129b common electrode 129c pixel electrode connection pattern
141: color filter substrate 143: black matrix
145: color filter layer 151: liquid crystal layer

Claims (11)

A gate wiring formed on one surface of the transparent insulating substrate in one direction and a gate electrode extending from the gate wiring;
A photosensitive insulating film formed on the surface of the gate electrode to surround the gate electrode; An active layer formed on the insulating substrate including the photosensitive insulating layer, and a source electrode and a drain electrode formed on the active layer and spaced apart from each other;
A data line perpendicular to the gate line;
A pixel electrode formed in the pixel region of the insulating substrate formed by crossing the gate wiring and the data wiring;
A passivation film formed on an entire surface of the insulating substrate including the pixel electrode and the data wiring and exposing the pixel electrode and the drain electrode;
And a pixel electrode connection pattern formed on the passivation layer and electrically connecting the pixel electrode and the drain electrode with a plurality of common electrodes overlapping the pixel electrode. The array substrate of claim 1, wherein the photosensitive insulating layer is used as a gate insulating layer. The liquid crystal display device as claimed in claim 1, wherein the photosensitive insulating layer is selected from photosensitive organic insulating materials including photo soluble gate insulator (SGI), photo-acryl (PAC), and PSG. Array substrate. The array substrate of claim 1, wherein the gate electrode has a stacked structure of a transparent conductive material layer pattern and a conductive metal layer pattern. The array substrate of claim 4, wherein the photosensitive insulating layer is formed on the entire surface of the gate electrode and the transparent conductive material layer pattern. Forming a gate wiring and a gate electrode extending from the gate wiring in one direction on one surface of a transparent insulating substrate having a pixel region defined therein, and forming the pixel electrode in the pixel region;
Forming a photosensitive insulating film surrounding the gate electrode on a surface of the gate electrode;
Forming a data interconnection perpendicular to the gate interconnection with an active layer and a source electrode and a drain electrode spaced apart from each other on the insulation substrate including the photosensitive insulating layer;
Forming a passivation film exposing the pixel electrode and the drain electrode on an entire surface of the insulating substrate including the pixel electrode and the data wiring;
And forming a pixel electrode connection pattern electrically connecting the pixel electrode and the drain electrode together with a plurality of common electrodes overlapping the pixel electrode on the passivation layer. 7. The method of claim 6, wherein the photosensitive insulating film is used as a gate insulating film. The liquid crystal display device as claimed in claim 6, wherein any one of photosensitive organic insulating materials including photo soluble gate insulator (SGI), photo-acryl (PAC), and PSG is selected and used as the photosensitive insulating layer. Array substrate manufacturing method. The method of claim 6, wherein the forming of the gate electrode, the pixel electrode, and the photosensitive insulating layer is performed by:
Sequentially depositing a transparent conductive material layer, a metal conductive layer, and a photosensitive insulating layer on the insulating substrate;
By selectively patterning the photosensitive insulating layer through a mask process using a diffraction mask, a photosensitive insulating layer pattern having a first thickness and a dummy photosensitive insulating layer having a second thickness thinner than the first thickness are formed on the gate electrode forming region and the pixel electrode forming region. Forming a pattern, respectively;
Etching the metal conductive layer and the transparent conductive material layer using the photosensitive insulating layer pattern and the dummy photosensitive insulating layer pattern as an etching mask;
Removing the dummy photosensitive insulating layer pattern through an ashing process to expose a metal conductive layer portion located above the pixel electrode formation region;
Etching the exposed portion of the metal conductive layer using the photosensitive insulating layer pattern as an etching mask to expose the lower pixel electrode;
And performing a reflow process so that the sidewall portion of the photosensitive insulating layer pattern located above the gate electrode formation region flows down and hardens, thereby covering the gate electrode surface. Manufacturing method. 10. The method of claim 9, wherein the gate electrode has a stacked structure of a transparent conductive material layer pattern and a conductive metal layer pattern. The method of claim 10, wherein the photosensitive insulating layer is formed on the entire surface of the gate electrode and the transparent conductive material layer pattern.

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