JP3987889B2 - Electrode substrate and flat display device - Google Patents

Description

  The present invention relates to an electrode substrate including fine electrode wirings, and more particularly to an electrode substrate and a flat display device which are divided into a plurality of regions and exposed.

  In recent years, flat display devices typified by liquid crystal display devices have various characteristics such as television display devices, computer display devices, car navigation display devices, etc., taking advantage of features such as light weight, thinness, and low power consumption compared to CRTs and the like. It is used in.

  In particular, an active matrix display device in which a switching element such as a thin film transistor (hereinafter abbreviated as TFT) or an MIM (Metal Insulator Metal) element is used for each display pixel has no crosstalk between adjacent pixels. Research and development has been actively conducted since a good display image can be realized.

  The prior art will be briefly described by taking as an example an active matrix liquid crystal display device in which a TFT is used as a switching element for each display pixel. An active matrix liquid crystal display device is formed by sealing a liquid crystal composition as a light modulation layer in a gap between an array substrate on which a plurality of pixel electrodes are arranged and a counter substrate on which a counter electrode is formed. In this array substrate, TFTs and pixel electrodes connected to the TFTs are arranged in a matrix on a transparent insulating substrate such as a glass substrate, and are further connected in common to the gate electrodes of the TFTs arranged in the row direction. A signal line commonly connected to the drain electrodes of the TFTs arranged in the line and column directions, and an auxiliary capacitance line that constitutes an auxiliary capacitance (Cs), which is disposed opposite to the pixel electrode via an insulating layer, are arranged. ing.

  An array substrate of such an active matrix liquid crystal display device is manufactured by forming an insulating film, a conductive film, a dielectric film, or the like, and repeating resist coating, exposure, development, and patterning.

  By the way, in recent years, a flat display device represented by a liquid crystal display device is required to realize a large and high-definition display image, and a high-precision exposure technique is required to realize this.

  Therefore, instead of exposing the resist on the substrate all at once, for example, as shown in FIG. 13, division exposure is known in which a plurality of regions are divided and each region is exposed.

  In FIG. 13, (A1) is an area exposed by the first exposure, (A2) is an area exposed by the second exposure, (A3) is an area exposed by the third exposure, and (A4) is an area exposed by the fourth exposure. Each area to be exposed is shown. In addition, the region (A1) exposed by the first exposure and the region (A2) exposed by the second exposure overlap with each other so that there is no exposure leak between the regions (A1) and (A2). Double exposure areas (A1, A2). Similarly, the double exposure areas (A1, A3) where the area (A1) and the area (A3), the area (A3) and the area (A4), and the area (A2) and the area (A4) are also exposed overlapping each other. , (A3, A4), (A2, A4).

  According to such an exposure technique, one exposure area can be made smaller with respect to the substrate area depending on the number of sections, so that each area can be exposed with high accuracy, thereby realizing a large and high-definition display image. Therefore, it is possible to provide a flat display device capable of the above.

  By the way, the double exposure areas (A1, A2), (A1, A3), (A3, A4), (A2, A4) in the above-described divided exposure method cause wiring defects such as disconnection compared to other areas. The rate of doing becomes extremely high.

  FIG. 14A shows a first exposure image (RP1) of the resist exposed by the first exposure for forming one electrode wiring, and a second exposure image (RP2) of the resist exposed by the second exposure. Respectively. As shown in FIG. 14A, the first exposure image (RP1) and the second exposure image (RP2) are different from each other in that the alignment accuracy between the masks, the distortion of the substrate, or the accuracy of the mask itself are different from each other. The wiring width (W1) of the first exposure image (RP1) and the wiring width (W2) of the second exposure image (RP29) are different from each other, and the exposure images may be shifted from each other. For this reason, as shown in FIG. 5B, based on the wiring width (W1 ′) of the electrode wiring patterned based on the first exposure image (RP1) and the second exposure image (RP2). The wiring width (W2 ′) of the patterned electrode wiring is different based on each deviation.

  Further, the double exposure regions (A1, A2) exposed in the first exposure and the second exposure are patterned based on the first exposure image (RP1) and the second exposure image (RP2), respectively. Therefore, the wiring width (W3) of the electrode wiring becomes very narrow or causes a defect such as disconnection in accordance with the alignment accuracy between the masks, the distortion of the substrate or the accuracy of the mask itself.

  The present invention has been made in response to the above-described technical problems, and an object thereof is to provide an electrode substrate and a flat display device in which defects such as disconnection are extremely reduced.

  According to a first aspect of the present invention, there is provided a first exposure region in which an electrode wiring disposed on a substrate is exposed by at least a first exposure, a second exposure region in which exposure is performed by a second exposure, and the first exposure. And a third exposure area exposed by the second exposure, a fourth exposure area exposed by at least the fourth exposure, and a fifth exposure area exposed by the fifth exposure. And a second conductor disposed in a stacked manner on the first conductor layer and electrically connected to the first conductor layer, and a sixth exposure region exposed by the fourth exposure and the fifth exposure. An electrode substrate comprising: an electrode wiring having a layer, wherein the third exposure region of the first conductor layer and the sixth exposure region of the second conductor layer are in regions different from each other in a plane. It is in.

  According to a fourteenth aspect of the present invention, a first conductive film is deposited on a substrate, divided into at least a first region and a second region, respectively exposed, patterned to form a first conductor layer, and the first conductive layer is formed. Depositing a second conductive film on one conductor layer, dividing it into at least a third region and a fourth region, exposing each of them, and patterning to form a second conductor layer laminated on the first conductor layer; An electrode substrate comprising: a first double exposure region exposed by both exposure of the first region and exposure of the second region; and exposure by both exposure of the third region and exposure of the fourth region. The electrode substrate is characterized in that the second double-exposure region to be formed is at a different position in a plane.

  According to a sixteenth aspect of the present invention, there are provided a plurality of pixel electrodes disposed on a substrate, a first exposure region exposed by at least a first exposure, a second exposure region exposed by a second exposure, and the first A first conductor layer including a first exposure and a third exposure region exposed by the second exposure; a fourth exposure region exposed by at least a fourth exposure; and a fifth exposure exposed by a fifth exposure. An exposure region and a sixth exposure region exposed by the fourth exposure and the fifth exposure, and are laminated on the first conductor layer and electrically connected to the first conductor layer. A first electrode substrate comprising electrode conductors including two conductor layers, wherein the third exposure region of the first conductor layer and the sixth exposure region of the second conductor layer are in regions different from each other in plan view; , Disposed opposite to the pixel electrode A counter substrate having an electrode, in flat panel display characterized by including a light modulation layer held between the counter substrate and the electrode substrate.

  The electrode wiring of this invention is comprised including the 1st conductor layer and the 2nd conductor layer arrange | positioned electrically connected on the 1st conductor layer. In addition, a third exposure region that is doubly exposed by both the first exposure of the first conductor layer and the second exposure mainly including an exposure region different from the first exposure, and the fourth exposure of the second conductor layer. In addition, the fourth exposure and the sixth exposure area which is double-exposed by the fifth exposure including mainly different exposure areas are in areas different from each other in a plane.

  Therefore, even if a wiring failure such as disconnection occurs in either the third exposure region of the first conductor layer or the sixth exposure region of the second conductor layer, each conductor layer functions redundantly. The electrode wiring itself does not break.

  Further, even if disconnection occurs at the same time in the third exposure region of the first conductor layer and the sixth exposure region of the second conductor layer, the third exposure region of the first conductor layer and the sixth exposure region of the second conductor layer. Are different from each other in plan view, and the electrode wiring itself is not disconnected. By the way, if any one of the first conductor layer and the second conductor layer is formed at the same time as the pixel electrode, the manufacturing process is not increased.

  According to the present invention, it is possible to obtain an electrode substrate and a flat display device in which defects such as disconnection of electrode wiring are extremely reduced.

  Hereinafter, an active matrix liquid crystal display device according to the present invention will be described with reference to the drawings. 1 is a partial schematic plan view of an array substrate for a display device according to the active matrix type liquid crystal display device of this embodiment, and FIG. 2A is an active matrix cut along the line AA ′ in FIG. FIG. 4B is a schematic cross-sectional view of the active matrix liquid crystal display device cut along the line BB ′ of FIG.

  The array substrate (100) for the display device of this embodiment has 640 × 3 signal lines Xi (i = 1, 2,..., 1920) and 480 scanning lines on a transparent insulating substrate (101) made of glass. Yj (j = 1, 2,..., 480) are arranged substantially orthogonal to each other, and the source electrode (141) is made of ITO (Indium Tin Oxide) at the intersection of each signal line Xi and the scanning line Yj. A TFT (131) electrically connected to the electrode (151) is disposed.

The TFT 131 is formed on the scanning line Yj so that the scanning line Yj itself serves as a gate electrode. That is, the scanning line Yj is used as a gate electrode, and a semiconductor film (123) made of an amorphous silicon (a-Si: H) thin film is disposed thereon via an insulating film (121) made of silicon oxide (SiO ₂ ). Then, a channel protective film (125) self-aligned with the scanning line Yj on the semiconductor film (123), and the semiconductor film (123) and the signal line Xi are connected to an ohmic contact film (n ⁺ type amorphous silicon thin film). 127) is provided with a drain electrode (143) extending from the signal line Xi which is electrically connected via the terminal 127). The source electrode (141) described above electrically connects the semiconductor film (123) to the pixel electrode (151) through an ohmic contact film (129) made of an n ⁺ type amorphous silicon thin film.

Further, the storage capacitor line Cj (j = 1, 2,..., 480) overlaps the pixel electrode 151 via an insulating film 121 made of silicon oxide (SiO ₂ ) and substantially parallel to the scanning line Yj. As a result, an auxiliary capacitance (Cs) is formed between the pixel electrode (151) and the auxiliary capacitance line Cj.

  The scanning line Yj and the auxiliary capacitance line Cj are respectively composed of a first scanning line conductor layer (103) and a first auxiliary capacitance line conductor layer (105) made of aluminum (Al) having a wiring width of 5 microns and a wiring width of 10 microns, The first scanning line conductor layer (103) is coated so as to prevent hillocks and round swelling generated in the one scanning line conductor layer (103) and the first auxiliary capacitance line conductor layer (105) and to further improve chemical resistance and the like. The laminated layers are arranged so as to cover the second scanning line conductor layer (107) and the first auxiliary capacitance line conductor layer (105) having a wiring width of 9 microns made of molybdenum (Mo) -tantalum (Ta) alloy. And a second auxiliary capacitance line conductor layer (109) made of molybdenum (Mo) -tantalum (Ta) alloy and having a wiring width of 14 microns. The reason why aluminum (Al) is used for the first scanning line conductor layer (103) and the first auxiliary capacitance line conductor layer (105) is to achieve a sufficiently low resistance even when the device is enlarged. As the second scanning line conductor layer (107) and the second auxiliary capacitance line conductor layer (109), an alloy of molybdenum (Mo) and a refractory metal can be used, and other than molybdenum (Mo) -tantalum (Ta) alloy. Also, a molybdenum (Mo) -tungsten (W) alloy is preferably used.

The signal line Xi comprises a first signal line conductor layer (111) having a wiring width of 5 microns made of an amorphous silicon (a-Si: H) thin film constituting the semiconductor film (123), and an ohmic contact film (127). A second signal line conductor layer (113) made of an n ⁺ type amorphous silicon thin film and arranged on the first signal line conductor layer (111) with the same wiring width, and the ITO formed simultaneously with the pixel electrode (151) A third signal line conductor layer (115) made of a film and disposed on the second signal line conductor layer (113) with the same wiring width; a first signal line conductor layer (111); and a second signal line conductor layer ( 113) and a fourth signal line conductor layer (117) having a wiring width of 5 microns comprising a laminate of molybdenum (Mo) and aluminum (Al) laminated so as to cover the third signal line conductor layer (115). including.

  The counter substrate (300) is formed on the transparent insulating substrate (301) made of glass, the gap between the signal line Xi and the pixel electrode (151), the gap between the scanning line Yj and the pixel electrode (151), and the TFT (131). A matrix-shaped light shielding film (311) made of chrome (Cr) so as to shield the light, and red (R), green (G), and blue (B) color filters disposed in the openings of the light shielding film (311) ( 321), a light shielding film (311), a protective film (331) disposed on the color filter (321), and a counter electrode (341) made of an ITO film disposed on the protective film (331) .

  Between the display device array substrate (100) and the counter substrate (300), a twisted nematic liquid crystal composition (400) is held via alignment films (401) and (403), respectively. Yes. Further, polarizing plates (411) and (413) are arranged on the outer surfaces of the substrates (100) and (300), respectively, so that the polarization axes are orthogonal to each other. 1) is structured.

  By the way, in the array substrate for display device (100) of this embodiment, during the exposure, as shown in FIG. 3, the transparent insulating substrate (101) is composed of the first exposure area (A1), the second exposure area (A2), Four areas of a third exposure area (A3) and a fourth exposure area (A4), and although not shown, a first exposure area (A1 ′), a second exposure area (A2 ′), a third exposure area (A3 ′), and A fourth exposure area (A4 ′) is divided into four areas, and each area is sequentially exposed. More specifically, since a circular lens is used for exposure, the circular area as shown in FIG. 3 becomes the exposure possible areas (S1), (S2), (S3), (S4). Light-shielded area (A1) exposed by rectangular first exposure, area (A2) exposed by second exposure, area (A3) exposed by third exposure, exposed by fourth exposure Area (A4), an area (A1 ') exposed by another rectangular first exposure (not shown), an area (A2') exposed by the second exposure, an area (A3) exposed by the third exposure '), The exposure is sequentially performed by the area (A4') exposed by the fourth exposure.

  Then, the double exposure region (A1) exposed by the first exposure and the region (A2) exposed by the second exposure are exposed to overlap each other so that there is no exposure leakage due to each exposure. A1 and A2), and areas (A1) and area (A3), areas (A3) and area (A4), and areas (A2) and area (A4) are also exposed to each other. (A1, A3), (A3, A4), (A2, A4). Although not shown, similarly, the double exposure region (A1 ′) in which the region (A1 ′) exposed by the other first exposure and the region (A2 ′) exposed by the second exposure are exposed to overlap each other. , A2 ′), the region (A1 ′) and the region (A3 ′), the region (A3 ′) and the region (A4 ′), the region (A2 ′) and the region (A4 ′) are also overlapped with each other and exposed. Double exposure areas (A1 ', A3'), (A3 ', A4'), (A2 ', A4').

  The double exposure areas (A1, A2), (A1, A3), (A3, A4), (A2, A4) and (A1 ', A2'), (A1 ', A3'), (A3 ' , A4 ′), (A2 ′, A4 ′), the wiring width is narrower than the others, or there is a high possibility that disconnection or the like will occur. Therefore, in this embodiment, the overlap length (OLL) is 6 in both cases. Set to micron. The overlap length (OLL) is preferably made small so as not to cause exposure omission, and is preferably made shorter than one side length of adjacent pixel electrodes. Further, the double exposure areas (A1, A2), (A1, A3), (A3, A4), (A2, A4) and (A1 ', A2'), (A1 ', A3'), (A3 ' , A4 ′) and (A2 ′, A4 ′) are desirably set avoiding the TFT (131) formation region.

  Hereinafter, a detailed description will be given with reference to FIG. 4 and FIGS. First, an aluminum (Al) film is deposited on a transparent insulating substrate (101) made of glass by sputtering and patterned to obtain 480 first scanning line conductor layers (103) as shown in FIG. 4 (a). 480 first auxiliary capacitance line conductor layers (105) substantially parallel to the first scanning line conductor layer (103) are formed simultaneously. The aluminum (Al) film is patterned by depositing an aluminum (Al) film, applying a photoresist on the aluminum (Al) film and drying, and then, as shown in FIG. 5, four regions (A1) and (A2) , (A3), (A4) and sequentially exposing, developing and etching, then removing the photoresist to remove the first scanning line conductor layer (103) having a wiring width of 5 microns and the first having a wiring width of 10 microns. An auxiliary capacitance line conductor layer (105) was obtained.

  The region (A1) and the region (A2) have double exposure regions (A1, A2) that are exposed to overlap each other so that no exposure is lost in the first to fourth exposures, and the region (A1) And the region (A3), the region (A3) and the region (A4), the region (A2) and the region (A4) are also exposed to overlap each other, the double exposure regions (A1, A3), (A3, A4), (A2, A4). The overlap length (OLL) of each double exposure area (A1, A2), (A1, A3), (A3, A4), (A2, A4) is set to 6 microns, and the first scanning line conductor The double exposure regions (A1, A3), (A2, A4) substantially parallel to the layer (103) and the first auxiliary capacitance line conductor layer (105) are arranged between the adjacent first scan line conductor layers (103), Specifically, it is set so as to be between the adjacent first scanning line conductor layer (103) and the first auxiliary capacitance line conductor layer (105). The overlap length (OLL) of each double exposure area (A1, A2), (A1, A3), (A3, A4), (A2, A4) can be determined according to the alignment accuracy between masks. It is desirable that it is 10 microns or less.

  The region Y (A1) corresponding to the double exposure regions (A1, A2), (A3, A4) of the first scanning line conductor layer (103) and the first auxiliary capacitance line conductor layer (105) thus formed. , A2), Y (A3, A4), C (A1, A2), C (A3, A4), the wiring width becomes narrow due to mask accuracy, mask misalignment, or distortion of the substrate (101). Depending on the case, disconnection may occur. Therefore, in this embodiment, a region Y (A1) corresponding to the double exposure regions (A1, A2), (A3, A4) of the first scanning line conductor layer (103) and the first auxiliary capacitance line conductor layer (105). , A2), Y (A3, A4), C (A1, A2), C (A3, A4), double exposure areas (A1, A2), ( The wiring width of the mask corresponding to A3, A4) was previously set to be about 1 micron thicker than other regions.

  However, it is assumed that, for example, disconnection occurs in Yj (A1, A2) due to the influence of mask accuracy, mask misalignment, or distortion of the substrate (101). Next, a molybdenum (Mo) -tantalum (Ta) alloy film is deposited thereon and patterned to form a molybdenum (Mo) -tantalum (Ta) alloy film as shown in FIG. A second scanning line conductor layer (107) having a wiring width of 9 microns covering the first scanning line conductor layer (103) and a second auxiliary capacitor having a wiring width of 14 microns covering the first auxiliary capacitance line conductor layer (105). A line conductor layer (109) is formed to obtain 480 scanning lines Yj and auxiliary capacitance lines Cj. The patterning of the molybdenum (Mo) -tantalum (Ta) alloy film is performed by depositing a molybdenum (Mo) -tantalum (Ta) alloy film, applying a photoresist on the molybdenum (Mo) -tantalum (Ta) alloy film, and then drying. After that, the four regions (A1 ′), (A2 ′), (A3 ′), and (A4 ′) shown in FIG. 6 are divided and exposed sequentially, developed, etched, the photoresist is removed, and the second scan is performed. A line conductor layer (107) and 480 second auxiliary capacitance line conductor layers (109) are obtained.

  As shown in FIG. 6, exposure regions (A1 ′), (A2 ′), (A3 ′), and (A4 ′) in patterning the molybdenum (Mo) -tantalum (Ta) alloy film are made of aluminum (Al). The exposure areas (A1), (A2), (A3), (A4) and the double exposure area for patterning the film are set to be arranged at different positions in a plane. Further, a region Y (A1 ′) corresponding to the double exposure regions (A1 ′, A2 ′), (A3 ′, A4 ′) of the second scanning line conductor layer (107) and the second auxiliary capacitance line conductor layer (109). , A2 ′), Y (A3 ′, A4 ′), C (A1 ′, A2 ′), and C (A3 ′, A4 ′) are also doubled so as to reduce wiring thinning or disconnection. The wiring width of the mask corresponding to the exposure areas (A1, A2) and (A3, A4) was set to be about 1 micron thicker than other areas in advance.

  However, the wiring width may be narrowed or disconnection may occur due to mask accuracy, mask misalignment, or distortion of the substrate (101). For example, the region Yj (A1 ′, A2) of the second scanning line conductor layer (107) It is assumed that a disconnection occurs in ').

  However, in this embodiment, the region Y (A1) corresponding to the double exposure regions (A1, A2), (A3, A4) of the first scanning line conductor layer (103) and the first auxiliary capacitance line conductor layer (105). , A2), Y (A3, A4), C (A1, A2), C (A3, A4), the second scanning line conductor layer (107) and the second auxiliary capacitance line conductor layer (109). Regions Y (A1 ', A2'), Y (A3 ', A4'), C (A1 ', A2'), C corresponding to the double exposure regions (A1 ', A2'), (A3 ', A4') (A3 ′, A4 ′) are different from each other in plan view.

  For this reason, even if a disconnection occurs in the region Yj (A1, A2) corresponding to the double exposure region (A1, A2) of the first scanning line conductor layer (103) of the scanning line Yj, the second of the scanning line Yj. The scanning line conductor layer (107) acts redundantly and the disconnection of the scanning line Yj is prevented. Even if a disconnection occurs in the region Yj (A1 ′, A2 ′) corresponding to the double exposure region (A1 ′, A2 ′) of the second scanning line conductor layer (107) of the scanning line Yj, the scanning line Yj The first scanning line conductor layer (103) acts redundantly, and disconnection of the scanning line Yj is prevented.

Next, as shown in FIG. 4C, as the insulating film 121, a silicon oxide film (SiO ₂ ), an amorphous silicon (a-Si: H) thin film 122, a silicon nitride film SiN _x ( 124) is continuously deposited without exposure to the atmosphere. Thereafter, by exposing from the back surface of the substrate (101) using the scanning line Yj as a mask, the silicon nitride film (SiN _x ) (124) is patterned to form a channel protective film (125) self-aligned with the scanning line Yj To do.

Thereafter, an n ⁺ -type amorphous silicon thin film is deposited, and the amorphous silicon (a-Si: H) thin film and the n ⁺ -type amorphous silicon thin film are patterned into an island shape, as shown in FIG. As shown, a semiconductor film (123) and an island-shaped n ⁺ -type amorphous silicon thin film (126) are obtained. At this time, patterning is performed so that an amorphous silicon (a-Si: H) thin film and an n ⁺ -type amorphous silicon thin film are wired in a region corresponding to the signal line Xi, and a wiring width of 3 microns is formed. One signal line conductor layer (111) and a second signal line conductor layer (113) are formed. The patterning of the amorphous silicon (a-Si: H) thin film and the n ⁺ type amorphous silicon thin film is divided into four regions (A1), (A2), (A3), and (A4) similar to FIG. Then, each was sequentially exposed.

  Thereafter, an ITO film is deposited and patterned to be laminated on the pixel electrode (151), the first signal line conductor layer (111) and the second signal line conductor layer (113), and the first signal line conductor layer A third signal line conductor layer (115) having substantially the same wiring width as (111) and the second signal line conductor layer (113) is formed. The ITO film is patterned by depositing the ITO film, applying a photoresist on the ITO film and drying it, and then, as in FIG. 5, the four regions (A1), (A2), (A3), ( A4) and sequentially exposing, developing, etching, removing the photoresist, and as shown in FIGS. 4 (e) and 7, the pixel electrode (151) and the third signal line conductor layer (115) Get.

  The region (A1) and the region (A2) have double exposure regions (A1, A2) that are exposed to overlap each other so that no exposure is lost in the first to fourth exposures, and the region (A1) And the region (A3), the region (A3) and the region (A4), the region (A2) and the region (A4) are also exposed to overlap each other, the double exposure regions (A1, A3), (A3, A4), (A2, A4). The overlap length (OLL) of each double exposure area (A1, A2), (A1, A3), (A3, A4), (A2, A4) is set to 6 microns. A1, A2), (A3, A4) are between the adjacent first signal line conductor layers (111), so as to avoid the area where the TFT (131) is disposed, and double exposure areas (A1, A3), ( A2, A4) are set between the adjacent scanning lines Yj so as to avoid the TFT (131) arrangement region. Again, as described above, the overlap length (OLL) of each double exposure area (A1, A2), (A1, A3), (A3, A4), (A2, A4) is the accuracy of alignment between masks. However, it is desirable to be 10 microns or less.

  Further, here, the double exposure region of the first signal line conductor layer (111) and the second signal line conductor layer (113) and the double exposure region of the third signal line conductor layer (115) are set at substantially the same position. However, it may be different to increase redundancy.

  A region X (corresponding to the double exposure regions (A1, A3), (A2, A4) of the first, second and third signal line conductor layers (111), (113), (115) thus formed. In A1, A3) and X (A2, A4), the mask width, mask misalignment, or distortion of the substrate (101) may cause the wiring width to narrow or disconnection. The wiring width was set to be about 1 micron thicker than other regions in advance.

However, for example, it is assumed that disconnection occurs at Xi (A1, A3). Next, a molybdenum (Mo) film and an aluminum (Al) film are successively deposited by sputtering and patterned to form a molybdenum (Mo) film and an aluminum (Al) film as shown in FIGS. A fourth signal line conductor layer (117) made of a laminate with a film and a drain electrode (143) integral with the fourth signal line conductor layer (117) are formed. At the same time, a source electrode (141) made of a laminate of a molybdenum (Mo) film and an aluminum (Al) film and electrically connected to the pixel electrode (151) is obtained. At the same time, the island-shaped n ⁺ -type amorphous silicon thin film (126) is patterned to form an ohmic contact layer (129) and a source electrode (141) interposed between the drain electrode (143) and the semiconductor film (123). And an ohmic contact layer (127) interposed between the semiconductor film (123) and the semiconductor film (123).

Here, exposure regions (A1 ′), (A2 ′) for patterning the laminate of the molybdenum (Mo) film and the aluminum (Al) film, and the island-like n ⁺ -type amorphous silicon thin film (126), As shown in FIG. 8, (A3 ′) and (A4 ′) are different in the double exposure region from the exposure regions (A1), (A2), (A3), and (A4) in patterning the ITO film. Is set.

  Region corresponding to double exposure region (A1 ', A3'), (A2 ', A4') of the fourth signal line conductor layer (117) composed of a laminate of molybdenum (Mo) film and aluminum (Al) film Also in X (A1 ', A3') and X (A2 ', A4'), the wiring width may be narrowed or disconnected due to mask accuracy, mask misalignment, or distortion of the substrate (101). Also, the wiring width of the corresponding mask is set beforehand to be about 1 micron thicker than other regions.

  However, for example, it is assumed that the disconnection also occurs in the region Xi (A2 ′, A4 ′) of the fourth signal line conductor layer (117). However, in this embodiment, the region X (corresponding to the double exposure regions (A1, A3), (A2, A4) of the first, second and third signal line conductor layers (111), (113), (115). A1, A3), Y (A2, A4) and a region X (A1 ′) corresponding to the double exposure regions (A1 ′, A3 ′), (A2 ′, A4 ′) of the fourth signal line conductor layer (117) , A3 ′) and Y (A2 ′, A4 ′) are different from each other in a plane. Therefore, the region Xi (A1, A3) corresponding to the double exposure region (A1, A3) of the first, second and third signal line conductor layers (111), (113), (1115) constituting the signal line Xi. Even if disconnection occurs, the fourth signal line conductor layers (111), (113), and (115) constituting the signal line Xi act redundantly, and the signal line Xi is prevented from being disconnected. Similarly, a disconnection occurs in the region Xi (A2 ′, A4 ′) corresponding to the double exposure region (A2 ′, A4 ′) of the fourth signal line conductor layer (117) constituting the signal line Xi. However, the first, second, and third signal line conductor layers (111), (113), and (115) constituting the signal line Xi act redundantly to prevent the signal line Xi from being disconnected.

  As described above, according to this embodiment, the disconnection failure of the signal line Xi and the scanning line Yj at the time of divided exposure is greatly reduced, and the manufacturing yield can be improved. In particular, even if the signal line Xi has a wiring width of 5 microns and the scanning line Yj has a wiring width of 9 microns, both having a fine wiring width smaller than 10 microns, the disconnection failure is greatly reduced.

The signal line Xi of this embodiment includes a first signal line conductor layer (111) and a second signal line conductor layer made of an amorphous silicon (a-Si: H) thin film and an n ⁺ type amorphous silicon thin film. (113) has a laminated structure of a third signal line conductor layer (115) made of an ITO film and a fourth signal line conductor layer (117) made of a laminate of molybdenum (Mo) and aluminum (Al). The first signal line conductor layer (111) and the second signal line conductor layer (113) are formed simultaneously with the formation of the TFT (131), and the third signal line conductor layer (115) is formed simultaneously with the patterning of the pixel electrode (151). Therefore, the manufacturing process does not increase.

  In the embodiment described above, the double exposure areas (A1, A2) and (A1 ′, A2 ′) and the double exposure areas (A3, A4) and (A3 ′, A4 ′) do not overlap in a plane. In particular, the exposure is performed so as to separate one signal line Xi, but the signal line Xi may not be separated if it does not overlap in a plane. Similarly, the double exposure areas (A1, A3) and (A1 ′, A3 ′), and the double exposure areas (A2, A4) and (A2 ′, A4 ′) are not particularly overlapped in a plane. Although the exposure is performed so as to separate the scanning lines Yj, the scanning lines Yj may not be separated if they do not overlap in a plane. However, when the double exposure region is separated from at least one signal line Xi or one scanning line Yj, the visibility of the boundary line of the exposure region is reduced.

  In the embodiment described above, the exposure areas (A1), (A2), (A3), (A4) and (A1 ′), (A2 ′), (A3 ′), (A4 ′) are rectangular. As a result, the boundary of each exposure region is linear. In the area formed based on the exposure areas (A1) and (A1 ′) and the area formed based on the exposure areas (A2) and (A2 ′), the accuracy of the mask, the distortion of the substrate, etc. As a result, the TFT characteristics, the parasitic capacitance affecting the pixel electrode, and the like are different, and the display state is slightly different, and the boundary of each exposure region may be visually recognized.

  Therefore, if each exposure area (A1), (A2), (A3), (A4) and (A1 '), (A2'), (A3 '), (A4') is made rectangular as described above, For example, as shown in FIG. 9, it is preferable to provide unevenness and make the boundary of each exposure region non-linear so that the boundary of each exposure region is less visible. In other words, if configured as described above, the display pixels corresponding to the exposure regions (A1) and (A1 ′) and the display pixels corresponding to the exposure regions (A2) and (A2 ′) are present in the boundary region of the exposure region. Since the display pixels corresponding to the exposure areas (A1) and (A2 ′) and the display pixels corresponding to the exposure areas (A2) and (A1 ′) are mixed, the boundary area is the exposure areas (A1) and (A1 The display pixel corresponding to ') and the display pixels corresponding to the exposure regions (A2) and (A2') are in an intermediate display state, and therefore the boundary is difficult to see.

  Next, another embodiment of the present invention will be described with reference to FIG. The display device array substrate (500) of this embodiment is formed on a transparent insulating substrate (501) made of glass in the same manner as in the above-described embodiment, although not shown, 640 × 3 signal lines Xi (i = 1, 2,..., 1920) and 480 scanning lines Yj (j = 1, 2,..., 480) are arranged substantially orthogonal to each other, and a source electrode (at the intersection of each signal line Xi and scanning line Yj) 681) includes a display pixel region (511) having a TFT (621) (see FIG. 11) electrically connected to a pixel electrode (671) made of ITO.

As shown in FIG. 11, the TFT (621) has a gate insulating film (641) made of silicon oxide (SiO ₂ ) on a channel region (633) of a semiconductor film (631) made of a polycrystalline silicon (p-Si) thin film. ) Is disposed on the gate electrode (651) electrically connected to the scanning line Yj. The drain region (635) of the semiconductor film (631) includes a first signal line conductor layer (551) made of ITO formed simultaneously with the pixel electrode (671) via the gate insulating film (641) and the interlayer insulating film (661). ) And a signal line Xi composed of a second signal line conductor layer (553) made of aluminum and wired thereon. The source region (637) of the semiconductor film (631) is also electrically connected to the pixel electrode (671) by the source electrode (681) made of aluminum via the gate insulating film (641) and the interlayer insulating film (661). Has been.

  Each signal line Xi is drawn to the upper side in FIG. 10 and electrically connected to the signal line driving circuit unit (521), and each scanning line Yj is drawn to the left side in FIG. 10 to scan the scanning line driving circuit unit (531). ) Is electrically connected. The signal line driver circuit portion (521) and the scanning line driver circuit portion (531) are integrally formed simultaneously with the formation of the display pixel region (511).

  By the way, the array substrate for display device (500) of this embodiment is divided into approximately four sections as shown in FIG. 10, and is formed by repeating film formation, resist application, drying, exposure and patterning. .

  The signal line driver circuit portion (521) and the scanning line driver circuit portion (531) each include an electrode wiring therein, but in the double exposure region, wiring thinning or disconnection may still occur.

  Therefore, taking the electrode wiring in the signal line drive circuit section (521) as an example, as shown in FIG. 12, this electrode wiring (523) is connected to the pixel electrode (671) in the display pixel region (511). A first electrode wiring layer (525) made of ITO having a wiring width of 5 microns formed simultaneously, and a second electrode wiring layer (527) made of aluminum having the same wiring width laminated thereon are included. In this embodiment, the first electrode wiring layer (525) and the second electrode wiring layer (527) have the same wiring width. For example, the first electrode wiring layer (525) has a 3 micron wiring width and the second electrode wiring layer (525) has the same wiring width. It may be configured to be covered with a layer (527).

  Then, the area E (A1, A2) corresponding to the double exposure area (A1, A2) of the first electrode wiring layer (525) and the double exposure area (A1 ', A2' of the second electrode wiring layer (527) The first electrode wiring layer (525) and the second electrode wiring layer (527) are patterned so as to be different from each other in the area E (A1 ′, A2 ′) corresponding to ().

  In this way, the electrode wiring layer (523) is configured to be electrically connected to each other by at least two conductor layers (525) and (527), and the double exposure regions (A1, A2) of each layer are further configured. ), (A1 ′, A2 ′) are different from each other in a plane, so that even if a wiring failure such as disconnection occurs in at least one electrode wiring layer, the other electrode wiring layer acts redundantly. Will not break.

  Such double exposure regions (A1, A2), (A1 ′, A2 ′) are switch elements such as TFTs that constitute the drive circuit portions (521), (531) as in the display pixel region (511). It is desirable to position so as to avoid. This is because the TFT corresponding to the double exposure region may have a different channel length and channel width compared to other TFTs, and the operation characteristics itself may be impaired. Although omitted, the display pixel region (511) can be configured in substantially the same manner as in the above-described embodiment.

  In this embodiment, one electrode wiring of the signal line driving circuit unit has been described. However, the electrode wiring of the scanning line driving circuit unit can be similarly configured. The constituent material of the electrode wiring is not limited to this example, and various electrode materials can be used.

  The above-described embodiments have been described by taking TFTs using an amorphous silicon (a-Si: H) thin film as a semiconductor layer and TFTs using a polycrystalline silicon (p-Si) thin film as a semiconductor layer. The semiconductor layer constituting the TFT may be microcrystalline silicon or single crystal silicon.

  Further, the display device array substrate using TFT as a switching element and an active matrix liquid crystal display device using the same have been described as an example. However, as a switching element, a two-terminal nonlinearity such as MIM is used in addition to TFT. An element etc. can be used suitably.

  Further, if a polymer dispersed liquid crystal or the like is used as the liquid crystal composition, an alignment film or a polarizing plate can be dispensed with. Furthermore, if it is configured as a reflection type, the pixel electrode may be formed of a highly reflective material such as aluminum (Al) instead of the ITO film, or a reflector may be attached to the rear surface of the array substrate.

FIG. 1 is a partial schematic front view of an array substrate for a display device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the active matrix type liquid crystal display device cut along line A-A ′ in FIG. 1. FIG. 3 is a conceptual diagram of divided exposure of the array substrate for a display device according to one embodiment of the present invention. FIG. 4 is a partial schematic cross-sectional view for explaining a manufacturing process of the display device array substrate of FIG. FIG. 5 is a partial schematic front view for explaining the manufacturing process of the display device array substrate of FIG. 1. FIG. 6 is a partial schematic front view for explaining the manufacturing process of the display device array substrate of FIG. 1. FIG. 7 is a partial schematic front view for explaining the manufacturing process of the display device array substrate of FIG. 1. FIG. 8 is a partial schematic front view for explaining the manufacturing process of the display device array substrate of FIG. 1. FIG. 9 is a partial schematic front view for explaining another manufacturing process of the array substrate for display device of FIG. FIG. 10 is a partial schematic front view of an array substrate for a display device according to another embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of the TFT in the display pixel region in FIG. FIG. 12 is a schematic configuration diagram of one-electrode wiring in the signal line driving circuit unit in FIG. FIG. 13 is a conceptual diagram of divided exposure. FIG. 14 is a conceptual diagram for explaining the problems of the prior art.

Explanation of symbols

(1) ... Active matrix type liquid crystal display device
(100) ... Array substrate for display device
(131)… TFT
(300)… Counter substrate
(400) ... Liquid crystal composition

Claims (14)

After depositing a first conductive film on the substrate, applying a photoresist on the first conductive film and drying, the photoresist is applied to a first region and a second region overlapping with a part of the first region. A first wiring formed by partitioning and exposing each , developing the photoresist, etching the first conductive film, and then removing the photoresist ;
A second conductive film is deposited on the substrate on which the first wiring is formed , a photoresist is applied on the second conductive film and dried, and then the photoresist is applied to the third region and a part of the third region. Each of the first region and the fourth region overlapped with each other, exposed to light , developed the photoresist, etched the second conductive film, and then removed the photoresist along the first wiring and the first region . In an electrode substrate comprising a multi-layered electrode wiring comprising a second wiring layered on the wiring ,
A first double-exposure area exposed by both exposure of the first area and exposure of the second area; a second exposure area exposed by both exposure of the third area and exposure of the fourth area; It is set not to overlap the double exposure area ,
The first wiring has a portion that passes through the first double exposure region, extends over the first region and the second region, and overlaps the second double exposure region,
The second wiring is formed so as to pass through the second double exposure region, straddle the third region and the fourth region, and has a portion overlapping the first double exposure region. An electrode substrate.   2. A display pixel region in which a plurality of pixel electrodes are arranged, and a peripheral region arranged around the display pixel region, wherein at least the electrode wiring is arranged in the display pixel region. The electrode substrate as described. The electrode substrate according to claim 2, wherein at least one of the first wiring and the second wiring of the electrode wiring is formed in the same process as the pixel electrode. 4. The electrode substrate according to claim 3, wherein the first wiring of the electrode wiring is made of ITO formed in the same process as the pixel electrode.   The electrode substrate according to claim 2, wherein the pixel electrode is electrically connected to the electrode wiring through at least a switch element.   The switching element is a thin film transistor having a source electrode electrically connected to the pixel electrode, the gate electrode of the thin film transistor being electrically connected to a scanning line, and the drain electrode being electrically connected to a signal line. 6. The electrode substrate according to claim 5, wherein at least one of the signal line and the scanning line includes the electrode wiring.   2. A display pixel region in which a plurality of pixel electrodes are arranged, and a peripheral region disposed around the display pixel region, wherein at least the electrode wiring is disposed in the peripheral region. Electrode substrate. 8. The electrode substrate according to claim 7, wherein at least one of the first wiring and the second wiring of the electrode wiring is formed in the same process as the pixel electrode. 9. The electrode substrate according to claim 8, wherein the first wiring of the electrode wiring is made of ITO formed in the same process as the pixel electrode. The electrode substrate according to claim 1, wherein a wiring width of the second wiring is wider than a wiring width of the first wiring . The electrode substrate according to claim 10, wherein the first wiring is covered with the second wiring . Wherein at least one of the first double exposure region and the second double exposure region, the electrode substrate according to claim 1, characterized in that uneven. After depositing a first conductive film on the substrate, applying a photoresist on the first conductive film and drying, the photoresist is applied to a first region and a second region overlapping with a part of the first region. A first wiring formed by partitioning and exposing each of the resist, developing the photoresist, etching the first conductive film and then removing the photoresist, and a substrate on which the first wiring is formed After depositing the second conductive film, applying a photoresist on the second conductive film and drying, the photoresist is partitioned into a third region and a fourth region overlapping a part of the third region. A second wiring layered along the first wiring and on the first wiring by respectively exposing, developing the photoresist, etching the second conductive film, and then removing the photoresist. Wiring and A first electrode substrate having an electrode wiring of a multilayer structure consisting of,
A pixel electrode formed on the first electrode substrate;
A counter substrate including an electrode disposed to face the pixel electrode;
A light modulation layer held between the first electrode substrate and the counter substrate ;
A flat display device characterized by comprising: The flat display device according to claim 13, wherein the light modulation layer is mainly composed of a liquid crystal composition.

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