KR100318534B1 - Liquid crystal display and manufacturing method thereof - Google Patents

Abstract

A common wiring including a gate line in the horizontal direction, a gate wiring including the gate electrode, a common signal line connecting portion parallel to the gate line, a common signal line in the vertical direction, and a common electrode extending in the horizontal direction from the common signal line is formed on the substrate. Here, the common electrode is inclined at a predetermined angle with respect to the gate line. On the gate insulating film covering the gate wiring and the common wiring, a data wiring including a source electrode, a drain electrode, and a data line defining a pixel crossing the gate line is formed, and the drain electrode overlaps the common signal line to form a storage capacitor. Connected with In the pixel, a pixel electrode linearly formed alternately with the common electrode extends to the branch of the pixel signal line. A protective film is formed on the data wiring and the pixel wiring, and an alignment film for aligning the liquid crystal molecules perpendicularly to the data line is formed on the protective film.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device having an electrode formed on the same substrate for applying a horizontal electric field to liquid crystal molecules and a thin film transistor which is an electric field application means.

The prior art as a liquid crystal driving method by a horizontal electric field is shown in US Patent No. 5,598, 285.

However, the liquid crystal display device disclosed in U.S. Patent No. 5,598,285 has an upper portion and a lower portion of a pixel in which a common signal line, which is connected to the common electrode and the common electrode and transmits a common signal, is adjacent to each other among the common electrode and the pixel electrode for applying a horizontal electric field There is a problem that the distortion of the liquid crystal drive occurs. Since the black matrix is formed wide to cover the distortion, the aperture ratio decreases.

In addition, a coupling effect or distorted driving occurs between a data line applying a voltage to the pixel electrode and a pixel electrode or a common electrode parallel thereto, and light leaks, thereby causing cross talk. There is a problem. In order to cover this, the common electrode adjacent to the data line is formed to be wider than necessary to reduce the aperture ratio.

In addition, since the common electrode and the pixel electrode are formed in parallel with the long direction of the pixel surrounded by the gate line and the data line in parallel with the data line, it is not easy to increase the number of electrodes.

An object of the present invention is to improve the aperture ratio of a liquid crystal display device of a horizontal electric field drive system.

Another object of the present invention is to provide a liquid crystal display device capable of easily adjusting the number of electrodes for applying a horizontal electric field.

1 is a layout view schematically illustrating a structure of a substrate for a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

4 and 5 are cross-sectional views taken along the lines IV-IV 'and V-V' in FIG. 3, respectively.

6A to 9C are views illustrating a manufacturing process of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

In order to solve the above technical problem, in the present invention, a common signal line in which the common electrode extends is formed in parallel with the data line, and the liquid crystal molecules are initially aligned perpendicularly to the data line.

In the liquid crystal display according to the present invention, a gate line and a data line are formed to cross a pixel, and a pixel electrode is formed on the pixel to face a common electrode, which is a branch of a common signal line parallel to the data line, and to face the common electrode at regular intervals. have. Also, a thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode, respectively, is formed in the pixel, and the liquid crystal molecules driven by the common electrode and the pixel electrode are formed on the substrate. An alignment film which is rubbed to be oriented in the vertical direction with respect to the data line is formed.

The rubbing direction perpendicular to the data line may be parallel to the gate line, and the common electrode and the pixel electrode may or may not be parallel to the gate line. When not parallel, the common electrode and the pixel electrode are preferably inclined 5 to 45 degrees with respect to the gate line.

In addition, the liquid crystal display further includes a pixel signal line on which the pixel electrode extends, and the pixel signal line and the common signal line overlap each other to form a storage capacitor. In addition, in order to improve the aperture ratio, the common electrode and the pixel electrode may be formed of ITO of the same layer. The redundant data line further overlaps the data line, and at least one of the data line and the redundant data line is formed of the same layer as the pixel electrode. Here, the thickness of the pixel electrode and the common electrode is preferably 1,000 Å or less, and the pixel electrode and the common electrode are preferably formed to be in direct contact with the alignment layer.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

In the liquid crystal display according to the present invention, the common signal line is formed along the data line in the long direction of the pixel, and the liquid crystal molecules are initially oriented perpendicularly to them, while the common electrode is formed in the short direction of the pixel.

First, a liquid crystal display according to a first embodiment of the present invention will be described. 1 is a layout view briefly illustrating a configuration of a unit pixel in a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, the gate line 20 is formed in the horizontal direction on the transparent insulating substrate 100, and a part of the gate line 20 becomes the gate electrode 21. A common signal line connection part 26 is formed above and below the pixel in parallel with the gate line 20, and a vertical signal direction in which the common signal line 24 connecting the common signal line connection part 26 is a long direction of the pixel is formed at left and right edges of the pixel. It is formed. A plurality of common electrodes 28 extending in a branch of the common signal line 24 and receiving common signals from the common signal line 24 in parallel to each other are formed in the horizontal direction, which is a short direction of the pixel. Here, the common electrode 28 is inclined at an arbitrary angle with respect to the gate line 20, and is preferably inclined in a range of 5 to 45 °.

The gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 20 and 21 and the common wirings 24, 26 and 28.

The semiconductor layer 40 of the thin film transistor made of amorphous silicon, which is a semiconductor, is formed on the gate insulating layer 30 on the gate electrode 21, and the amorphous silicon doped with phosphorus (P) is heavily doped on the amorphous silicon layer 40. Resistive contact layers 51 and 52 are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed in the vertical direction on the gate insulating layer 30. 60). In addition, the drain electrode 62 is connected to the common signal line connecting portion 26 horizontally and the pixel signal line 64 formed in the periphery of the pixel overlapping the common signal line 24, respectively, and the common electrode in the pixel. A pixel electrode 68 which is formed linearly alternately with 28 extends into the branch of the pixel signal line 64.

The gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor.

A protective film 70 made of an insulating material such as silicon nitride is formed on the data wires 60, 61, 62, the pixel wires 64, 68, and the semiconductor layer 40 that is not covered by the data wires. An alignment film 80 for aligning the liquid crystal molecules is formed thereon.

Here, in order to prevent orientation defects due to a step in the alignment layer 80, the common electrode 28 and the pixel electrode 68 may be formed to be 1,000 μm or less, and the protective layer 70 may use an organic film having good planarization. .

In FIG. 1, the horizontal arrow direction (→) is a rubbing direction of the alignment layer 80 for initial alignment of the liquid crystal molecules, and the portion enclosed by the thick line represents the opening of the black matrix. The black matrix may be formed on the same substrate as the common electrode 28 and the pixel electrode 68 and may be formed on another substrate.

In the liquid crystal display according to the first exemplary embodiment of the present invention, the common signal line 24 is formed in the long direction of the pixel parallel to the data line 60, and is perpendicular to the liquid crystal molecules parallel to the gate line 20. Since is rubbed so as to be initially oriented, even if a voltage difference occurs between the data line 60 and the common signal line 24, even if the liquid crystal molecules are driven, they are driven in the same direction as the initial alignment direction and displayed dark, so that no crosstalk occurs. Accordingly, the aperture ratio of the pixel can be increased by forming the common signal line 24 adjacent to the data line 60 to be as narrow as possible.

In addition, unlike the conventional structure, the number of the electrodes 28 and 68 can be easily adjusted by forming the common electrode 28 and the pixel electrode 68 in a short direction of the pixel.

Here, as shown in FIG. 1, the common electrode 28 and the pixel electrode 68 are inclined by θ with respect to the initial alignment direction. This is to determine the direction of return to the driven liquid crystal molecules due to the voltage difference generated between the common electrode 28 and the pixel electrode 68.

In this structure, the pixel signal lines 64 are formed adjacent to the gate lines 20 to minimize the light leakage therebetween.

In the liquid crystal display according to the first embodiment, the common wirings 24, 26, 28 are formed on the same layer as the gate wirings 20, 21, but may be formed of different layers, which will be described in detail with reference to the second embodiment. Let's do it.

3 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 4 and 5 are cut along lines IV-IV 'and V-V' in FIG. One is a cross section of each.

3 to 5, the gate line 20 is formed in the horizontal direction on the transparent insulating substrate 100, and at the end of the gate line 20, the gate pad 22 receiving the scan signal from the outside is formed. The portion of the gate line 20 is connected to the gate electrode 21. The common signal line 24 is formed in the vertical direction in the longitudinal direction of the pixel at the left and right edges of the pixel, and the first common signal line connection part 26 extends out of the pixel from the common signal line 24 and the common signal line 24 Some are curved. Here, as shown in FIGS. 4 and 5, the gate wirings 20, 21, 22 and the common wirings 24 and 26 may include the lower layers 211, 221: 241 and 261 of chromium and the upper portion of the aluminum-neodium alloy. Membranes 212, 222: 242, 262.

The gate insulating film 30 made of silicon nitride or the like is covered over the gate wirings 20, 21, 22 and the common wirings 24, 26.

The semiconductor layer 40 of the thin film transistor made of amorphous silicon, which is a semiconductor, is formed on the gate insulating layer 30 on the gate electrode 21, and the amorphous silicon doped with phosphorus (P) is heavily doped on the amorphous silicon layer 40. Resistive contact layers 51 and 52 are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of ITO, which is one of the transparent conductive materials, are formed on the ohmic contact layers 51 and 52, respectively. The source electrode 61 is vertically disposed on the gate insulating layer 30. The data pad 60 is connected to the formed data line 60, and a data pad 63 receiving an image signal from the outside is connected to an end of the data line 60. In addition, the drain electrode 62 is connected to the pixel signal line 64 overlapping the common signal line 24. In the pixel, the pixel electrode 68 extending in the horizontal direction from the pixel signal line 64 is formed. The common electrode 66 is formed between the pixel electrodes 68, respectively.

In the structure according to the second embodiment, since the common electrode 66 and the pixel electrode 68 are made of ITO, which is a transparent conductive material, the aperture ratio is improved, and is formed at about 500 GPa to minimize light leakage due to uneven rubbing due to a step. can do.

A protective film 70 made of an insulating material such as silicon nitride is formed on the data wirings 60, 61, 62, and 63, the pixel wirings 64 and 68, the common electrode 66, and the semiconductor layer 40 that is not covered by the data wiring. The passivation layer 70 includes a common signal line 24 together with a contact hole 76, 73, 71, and a gate insulating layer 30 that expose the common electrode 66, the data pad 63, and the data line 60. Contact holes 74 and 72 are formed to expose the four ends of the gate and the gate pad 22.

Here, the protective film 70 may be an organic film having a good planarization.

Next, redundancy data wires 90 and 93 connected to the data wires 60 and 63 through the contact holes 71 and 73 are formed along the data wires 60 and 63 in the upper portion of the protective film 70. In addition, a redundant gate pad 92 connected to the gate pad 22 is formed through the contact hole 72, and the common electrode 66 and the common signal line 24 are connected through the contact holes 74 and 76. The second common signal line connection part 96 to be connected overlaps with the common signal line 24. In this case, the second common signal line connection part 96 also connects the common signal line 24 formed vertically at both edges of the pixel. Here, the redundant wirings 90, 92, 93, and the second common signal line connection part 96 have the same chromium lower layers 901, 921, and the same as the gate wirings 20, 21, 22, and the common wirings 24, 28. 931 and 961 and upper films 902, 922, 932 and 962 of the aluminum-neodium alloy film.

Now, a method of manufacturing a liquid crystal display substrate according to a second embodiment of the present invention will be described. 6A to 9C are cross-sectional views illustrating a process of manufacturing a substrate for a liquid crystal display as shown in FIGS. 3 to 5.

First, as shown in FIGS. 6A to 6C, a chromium (Cr) film and a aluminum-neodium (Al-Nd) alloy film are formed on a transparent insulating substrate 100 such as glass with a thickness of about 500 kPa and about 2,500 kPa. Deposited in sequence and patterned using a first mask to form a gate line consisting of the gate line 20, the gate electrode 21 and the gate pad 22, the common signal line 24 in the vertical direction, and the first common signal line connection in the horizontal direction. A common wiring made up of 26 is formed. In this case, various conductive materials may be used as the gate wiring metal, and a single layer using chromium, aluminum, an aluminum alloy, molybdenum, or the like may be formed, or the gate wiring may be formed by a double layer combining these metals. Here, the gate wirings 20, 21, 22 and the common wirings 24, 26 are the lower films 211, 221: 241, 261 of chromium and the upper films 212, 222: 242, 262 of aluminum-neodium alloy. This is the case of double layer consisting of). Although not shown in cross section, the gate line is formed of a double layer.

Next, as shown in FIGS. 7A to 7C, an insulating gate insulating film 30 such as silicon nitride or an organic insulating film is formed on the entire surface of the substrate to have a thickness of 3,000 to 5,000 GPa, and an amorphous silicon layer having a thickness of about 500 to 2,000 GPa ( 40) and an amorphous silicon layer 50 heavily doped with impurities such as phosphorous having a thickness of about 500 mm 3 are sequentially deposited. The doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned together using a second mask to form an island shape on the gate electrode 21.

As shown in FIGS. 8A to 8C, an indium tin oxide (ITO), which is a transparent conductive material, is stacked at about 1,000 GPa or less, or about 500 GPa, and patterned using a third mask to cross the gate line 20 to cross each other. The data line 60 including the data line 60, the source and drain electrodes 61 and 62, and the data pad 63, and the pixel signal line 64 and the pixel signal line overlapping the common signal line 24 in the vertical direction. The common electrode 66 is formed between the pixel wires and the pixel electrodes 68 by the horizontal pixel electrodes 68 connected to the 64. Next, the doped amorphous silicon layer 50, which is not covered by the source electrode 61 and the drain electrode 62, is etched to separate the doped amorphous silicon layer 50 from both sides of the gate electrode 21 to form a resistive contact layer 51. 52), revealing the semiconductor layer 40.

Next, as shown in FIGS. 9A to 9C, a protective film 70 having a thickness of 1,500 to 2,500 Å is formed on the entire surface of the substrate 100 by using silicon nitride or an organic insulating film, and the protective film is formed by a patterning process using a fourth mask. 70 and the gate insulating layer 30 are etched together to form the upper layer (the upper layer of the upper and lower ends of the data line 60, the upper layer 222 of the gate pad 22, the data pad 63, and the common signal line 24). Contact holes 71, 72, 73, 74, and 76 are formed to expose 242 and common electrode 66, respectively. In this case, the common electrode 66 and the pixel electrode 68 may be exposed. Then, the driving voltage applied to the two electrodes 66 and 68 may be lowered to drive the liquid crystal molecules. When the driving voltage is lowered, the aperture ratio may be improved by forming a wide interval between the two electrodes 66 and 68. When the insulating film does not remain on the two electrodes 66 and 68, afterimages may be minimized.

Finally, as shown in FIGS. 3 to 5, a single film or a plurality of films of chromium, molybdenum, molybdenum alloy or aluminum, aluminum alloy, which are low resistance metals, are deposited, and patterned using a fifth mask to form a date line ( 60, a redundant data line 90, redundant data pad 93, and redundant circuit, which have similar shapes to the data pad 63 and the gate pad 22, and are connected to each other through the contact holes 71, 72, and 73, respectively. The second common signal line connection part 96 connecting the common signal line 24 and the common electrode 66 is formed through the contact holes 74 and 76 while forming the gate pad 92. Here again, the redundant wirings 90, 92, 93 and the second common signal line connecting portion 96 have the same chromium lower layers 901, 921, and the same as the gate wirings 20, 21, 22 and the common wirings 24, 28. 931 and 961 and upper films 902, 922, 932 and 962 of the aluminum-neodium alloy film.

Thereafter, an alignment layer is formed on the surface of the substrate and subjected to a process such as rubbing to give the orientation of the liquid crystal material. The alignment direction is aligned perpendicular to the data line 60 and the common signal line 24 as in the first embodiment. Good to do.

In the thin film transistor substrate for the liquid crystal display device and the manufacturing method thereof according to the second embodiment of the present invention, a protective film covering the redundant wirings 90, 92, 93 and the second common signal line connection part 96 may be added. In this case, the upper layers 922 and 932 of the pad portion must be exposed. At this time, the common electrode 66 and the pixel electrode 68 of the pixel also remove the insulating film, which is a protective film, unlike the first embodiment in order to minimize the driving voltage and residual image and improve the aperture ratio, as described above. ) And the pixel electrode 68 may be formed in direct contact with each other.

In addition, by forming the gate line 20 and the second common signal line connection part 96 in different layers, they can be formed adjacent to each other and the aperture ratio can be improved in the long direction of the pixel. Further, even when the pixel signal line 64 is formed in the long direction of the pixel, and the common signal line 24 overlapping the pixel signal line is formed to have a narrow width, the storage capacitance can be sufficiently secured, so that the common signal line 24 and the pixel signal line 64 are provided. By forming the width of the narrower the aperture ratio in the short direction of the pixel can be improved.

In addition, since the gate line 20 is positioned below the second common signal line connection part 96 adjacent thereto, the side crosstalk can be removed by changing the path of the incident light causing the side crosstalk to be blocked by the black matrix. have.

In addition, as described in the first embodiment, the common signal line 24 is formed in the long direction of the pixel in parallel with the data line 60, and the liquid crystal molecules are initially aligned and perpendicular to the gate line 20. The side crosstalk generated at the portion adjacent to the data line can be eliminated. As such, crosstalk can be eliminated without overlapping the data line 60 and the common signal line 24 adjacent thereto, thereby minimizing parasitic capacitance generated therebetween. Therefore, the delay with respect to the signal transmitted through the data line 60 can be reduced and applied to the liquid crystal display of the large screen. In addition, the common signal transmitted through the common signal line 24 is not distorted, and thus afterimage or flicker may be reduced.

As in the exemplary embodiment of the present invention, the common signal line may be formed in the long direction of the pixel in parallel with the data line to improve the aperture ratio, reduce light leakage, and reduce delay or distortion of the signal. In addition, the common electrode and the pixel electrode may be formed of a transparent conductive material to improve the aperture ratio, and the residual material or the driving voltage may be minimized by removing the insulating material thereon. In addition, the number of these can be easily adjusted by arranging the common electrode and the pixel electrode in the long direction of the pixel.

Claims (14)

(Correction) a gate line formed on a transparent substrate, A data line formed on the substrate and insulated from and intersecting the gate line; A pixel region defined by an intersection of the gate line and the data line and having a linear common electrode which is a branch of a common signal line formed in parallel with the data line, and a linear pixel electrode which faces in parallel with the common electrode at regular intervals; , A thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the data line, and the pixel electrode, respectively; And an alignment layer formed on the substrate and rubbed to align liquid crystal molecules driven by the common electrode and the pixel electrode in a direction perpendicular to the data line. In claim 1, And the common electrode and the pixel electrode are not parallel to the gate line. In claim 2, The common electrode and the pixel electrode are inclined 5 to 45 ° with respect to the gate line. In claim 1, The liquid crystal display device wherein the data line and the common signal line do not overlap. The method of claim 3 or 4, And the gate line and the rubbing direction are parallel to each other. In claim 1, And the common electrode and the pixel electrode are parallel to the gate line. In claim 1, A pixel signal line connected to the pixel electrode; And the pixel signal line overlaps the common signal line. In claim 1, The common electrode and the pixel electrode are formed of the same layer, the liquid crystal display device made of ITO, In claim 8, And a data pad formed at an end of the data line. And a gate pad formed at an end of the gate line. In claim 9, A redundant data line overlapping the data line, the parallel data line being connected to the data line; And a redundant data pad and a redundant gate pad formed of a conductive material layer such as the redundant data line, And the data pad, the gate pad, the redundant data pad, and the redundant gate pad are connected to each other. In claim 10, And at least one of the data line and the redundant data line is formed of the same layer as the pixel electrode. In claim 11, The thickness of the pixel electrode and the common electrode is less than 1,000Å. In claim 12, The pixel electrode and the common electrode are in direct contact with the alignment layer. In claim 1, And the pixel is longer in the data line direction than the length in the gate line direction.